X25057 ICMIC | Alldatasheet

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©Xicor, Inc. 1994 – 1997 Patents Pending 7033-1.1 5/8/97 T1/C0/D0 SH 1 Characteristics subject to change without notice 4K X25057 512 x 8 Bit 5MHz Low Power SPI Serial E 2PROM with IDLock™ Memory

FEATURES

  • 5MHz Clock Rate
  • IDLock™ Memory — IDLock First or Last Page, Any 1/4 or Lower 1/2 of E2PROM Array
  • Low Power CMOS —<1 ∝ A Standby Current — <3mA Active Current during Write — <400 ∝ A Active Current during Read
  • Built-in Inadvertent Write Protection — Powe r-Up/Power -Down Protection Circuitry — Write Enable Latch — Write Protect Pin
  • SPI Modes (0,0 & 1,1)
  • 512 x 8 Bits — 16 Byte Page Mode
  • Self-Timed Write Cycle — 5ms Write Cycle Time (Typical)
  • High Reliability — Endurance: 100,000 Cycles/Byte —Data Retention: 100 Years — ESD: 2000V on all pins
  • 8-Lead MSOP Package •8- Lead TSSOP Package
  • 8 -Lead SOIC Package
  • 8-Lead PDIP Package

DESCRIPTION

The X25057 is a CMOS 4K-bit serial E 2PROM, internally organized as 512 x 8. The X25057 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. IDLock is a programmable locking mechanism which allows the user to lock system ID and parametric data in different portions of the E 2PROM memory space, ranging from as little as one page to as much as 1/2 of the total ar ray. The X25057 also features a WP pin that can be used for hardwire protection of the part, disabling all write attempts, as well as a Write Enable Latch that must be set before a write operation can be initiated. The X25057 utilizes Xicor’s proprietary Direct Write TM cell, providing a minimum endurance of 100,000 cycles per byte and a minimum data retention of 100 years. FUNCTIONAL DIAGRAM COMMAND DECODE AND CONTROL LOGIC WRITE CONTROL LOGIC DATA REGISTER Y DECODE LOGIC X DECODE LOGIC HIGH VOLTAGE CONTROL 4K E 2PROM ARRAY (512 x 8) SO SI SCK CS WP 8 16

7033 FRM F01

This X25057 device has been acquired by IC MICROSYSTEMS from Xicor, Inc. ICmic IC MICROSYSTEMS TM

Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is a serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is HIGH, the X25057 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25057 will be in the standby power mode. CS LOW enables the X25057, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is LOW, nonvolatile writes to the X25057 are disabled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW while CS is still LOW will interrupt a write to the X25057. If the internal write cycle has already been initiated, WP going low will have no affect on this write. PIN NAMES

7033 FRM T01

The X25057 is a 512 x 8 E 2PROM designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The X25057 contains an 8- bit instruction register. It is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW and the WP input must be HIGH during the entire operation. Table 1 contains a list of the instructions and their opcodes. All instructions, addresses and data are transferred MSB first. Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock and then start it again to resume opera- tions where left off. Symbol Description CS Chip Select Input SO Serial Output SI Serial Input SCK Serial Clock Input WP Write Protect Input VSS Ground VCC Supply Voltage NC No Connect VCC NC SI SCK 7033 FRM F02.1 SO CS VSS WP

8 Lead MSOP

7033 FRM F02.2 NC VCC CS SO

8 Lead TSSOP

7033 FRM F02

8 Lead SOIC/PDIP

*0.197" *0.244" 0.120" 0.193" 0.122" 0.252" Not to scale *SOIC Measurement

previously written IDLock byte. See Table 1.

  • The device is in the low power, standby state.
  • A HIGH to LOW transition on CS is required to enter an active state and receive an instruction.
  • SO pin is at high impedance.
  • The “Write Enable” latch is reset. Data P rotection The following circuitry has been included to prevent inad- vertant writes:
  • The “Write Enable” latch is reset upon power-up. •A WREN instruction must be issued to set the “Write Enable” latch.
  • CS must come HIGH at the proper clock count in order to start a write cycle.

Table 1. Instruction Set and Block Lock Protection Byte Definition

7033 FRM T03

*Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.

Figure 4. WREN/WRDI Sequence Figure 5. Byte Write Operation Sequence

7033 FRM F06

Figure 7. IDLock Operation Sequence

ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin with Lead Temperature *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)

7033 FRM T06

7033 FRM T07

Notes: (1)V IL Min. and V IH Max. are for reference only and are not 100% tested. (2)t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiat ed. These parameters are periodically sampled and not 100% tested. Limits Symbol Parameter Min. Max. Units Test Conditions ICC1 V CC Supply Current (Write) 3 mA SCK = V CC x 0. 1/V CC x 0.9 @ 5MHz, SO = Open, CS = VSS ICC2 V CC Supply Current (Read ) 400 ∝ A SCK = V CC x 0. 1/V CC x 0.9 @ 5MHz, SO = Open, CS = VSS ISB VCC Supply Current (Standby) 1 ∝ A CS = V CC , V IN = VSS or V CC ILI Input Leakage Current 10 ∝ A VIN = VSS to V CC ILO Output Leakage Current 10 ∝ A VOUT = VSS to V CC V IL (1) Input LOW Voltage –0.5 VCC x 0.3 V V IH (1) Input HIGH Voltage VCC x 0.7 V CC + 0.5 V VOL1 Output LOW Voltage 0.4 V VCC > 3.3V, I OL = 2.1mA VOL2 Output LOW Voltage 0.4 V 2V < V CC = 3.3V, I OL = 1mA VOL3 Output LOW Voltage 0.4 V VCC = 2V, I OL = 0.5mA VOH1 Output HIGH Voltage VCC – 0.8 V VCC > 3.3V, I OH = -1.0mA VOH2 Output HIGH Voltage VCC – 0.4 V 2V < V CC = 3.3V, I OH = -0.4mA VOH3 Output HIGH Voltage VCC – 0.2 V VCC = 2V, I OH = -0.25mA Symbol Parameter Min. Max. Units t PUR (2) Power-up to Read Operation 1 ms t PUW (2) Power-up to Write Operation 5 ms RECOMMENDED OPERATING CONDITIONS

7033 FRM T04

Temperature Min. Max. Commercial 0°C +70 °C Industrial –40 °C +85 °C

7033 FRM T05

X25057 4.5V to 5.5V X25057-2.7 2.7V to 5.5V X25057-1.8 1.8V to 3.6V

A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Data Input Timing

7033 FRM T10

Notes: (3)This parameter is periodically sampled and not 100% tested. (4)t WC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Symbol Parameter Voltage Min. Max. Units fSCK Clock Frequency 2.7V–5.5V 1.8V–3.6V 3.3 MHz tCYC Cycle Time 2.7V–5.5V 1.8V–3.6V 200 300 ns tLEAD CS Lead Time 2.7V–5.5V 1.8V–3.6V 100 150 ns tLAG CS Lag Time 2.7V–5.5V 1.8V–3.6V 100 150 ns tWH Clock HIGH Time 2.7V–5.5V 1.8V–3.6V 130 ns tWL Clock LOW Time 2.7V–5.5V 1.8V–3.6V 130 ns tSU Data Setup Time 20 ns tH Data Hold Time 20 ns t RI (3) Data In Rise Time 2 ∝ s t FI (3) Data In Fall Time 2 ∝ s tCS CS Deselect Time 100 ns t WC (4) Write Cycle Time 10 ms A.C. TEST CONDITIONS

7033 FRM T09

Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Level V CC X 0.5 EQUIVALENT A. C. LOAD CIRCUIT OUTPUT 2061 Ο 3025 Ο 30pF OUTPUT 3.3V 2696 Ο 5288 Ο 30pF OUTPUT 2800 Ο 5600 Ο 30pF CAPACITANCE T A = +25 °C, f = 1MHz, V CC = 5.0V.

7033 FRM T08

Symbol Parameter Max. Units Conditions C OUT (3) Output Capacitance (SO) 8 pF VOUT = 0V C IN (3) Input Capacitance (SCK, SI, CS, WP) 6 pF VIN = 0V 7033 FRM F09.1

Notes: (5)This parameter is periodically sampled and not 100% tested. Figure 8. Serial Output Timing

7033 FRM F10

Figure 9. Serial Input Timing

7033 FRM F11

0.118 ± 0.002 (3.00 ± 0.05) 0.040 ± 0.002 (1.02 ± 0.05) 0.150 (3.81) REF. 0.193 (4.90) REF. 0.030 (0.76) 0.036 (0.91) 0.032 (0.81) 0.007 (0.18) 0.005 (0.13) 0.008 (0.20) 0.004 (0.10) 0.0216 (0.55) ° TYP R 0.014 (0.36) 0.118 ± 0.002 (3.00 ± 0.05) 8-LEAD MINIATURE SMALL OUTLINE GULL WING PACKAGE TYPE M NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)

3003 FRM 01

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN M ILLIMETERS) 8-LEAD PLASTIC, TSSOP, PACKAGE TYPE V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) ° – 8 ° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)

0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7 ° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) ° – 8 ° X 45 ° 3926 FRM F22.1 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.250" 0.050" TYPICAL 0.050" TYPICAL 0.030" TYPICAL

8 PLACES FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

NOTE: 1.ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) REF. PIN 1 INDEX 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) PIN 1 SEATING PLANE 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) TYP . 0.010 (0.25) 15 ° 8-LEAD PLASTIC DUAL IN -LINE PACKAGE TYPE P HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) MAX. 0.325 (8.25) 0.300 (7.62)

ORDERING INFORMATION

Blank = Commercial = 0 °C to +70 °C I = Industrial = –40 °C to +85 °C Package 8-Lead MSOP LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4, 486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2.A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. V = 8-Lead TSSOP S = 8-Lead SOIC AAA = 1.8 to 3.6V, 0 to +70 °C G – V VCC Limits Blank = 4.5V to 5.5V 2.7 = 2.7V to 5.5V 1.8 = 1.8V to 3.6V EYWW XXX AAC = 1.8 to 3.6V, -40 to +85 °C AAO = 2.7 to 5.5V, 0 to +70 °C AAP = 2.7 to 5.5V, -40 to +85 °C AAF = 4.5 to 5.5V, 0 to +70 °C AAG = 4.5 to 5.5V, -40 to +85 °C 8-Lead TSSOP AG = 1.8 to 3.6V, 0 to +70 °C EYWW 5057XX AH = 1.8 to 3.6V, -40 to +85 °C F = 2.7 to 5.5V, 0 to +70 °C G = 2.7 to 5.5V, -40 to +85 °C Blank = 4.5 to 5.5V, 0 to +70 °C I = 4.5 to 5.5V, -40 to +85 °C 8-Lead SOIC/PDIP X25057 G XXX M = 8-Lead MSOP Blank = 8-Lead SOIC P = 8-Lead PDIP G = RoHS compliant leadfree AG = 1.8 to 3.6V, 0 to +70 °C AH = 1.8 to 3.6V, -40 to +85 °C F = 2.7 to 5.5V, 0 to +70 °C G = 2.7 to 5.5V, -40 to +85 °C Blank = 4.5 to 5.5V, 0 to +70 °C I = 4.5 to 5.5V, -40 to +85 °C P = 8-Lead PDIP G= RoHS Compliant Lead Free package Blank = Standard package. Non lead free