X25040P

X25040 ICMIC | Alldatasheet

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Technical content

This X25040 device has been acquired by IC MICROSYSTEMS from Xicor, Inc. 4K X25040 512 x 8 Bit ©Xicor, Inc. 1994, 1995, 1996 Patents Pending Characteristics subject to change without notice 6451-3.6 6/10/96 T5/C1/D0 NS Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.

FEATURES

• 1MHz Clock Rate
• SPI Modes (0,0 & 1,1)
• 512 X 8 Bits — 4 Byte Page Mode
• Low Power CMOS —150 µA Standby Current —3mA Active Current
• 2.7V To 5.5V Power Supply
• Block Lock Protection — Protect 1/4, 1/2 or all of E 2PROM Array
• Built-in Inadvertent Write Protection — Power -Up/Power -Down protection circuitry —Write Latch — Write Protect Pin
• Self-Timed Write Cycle — 5ms Write Cycle Time (Typical)
• High Reliability — Endurance: 100,000 cycles per byte —Data Retention: 100 Years — ESD protection: 2000V on all pins
• 8-Lead PDlP Package
• 8-Lead SOIC Package

DESCRIPTION

The X25040 is a CMOS 4096-bit serial E 2PROM, internally organized as 512 x 8. The X25040 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X25040 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25040 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25040 disabling all write attempts, thus providing a mechanism for limiting end user capability of altering the memory. The X25040 utilizes Xicor’s proprietary Direct Write™ cell, providing a minimum endurance of 100,000 cycles per byte and a minimum data retention of 100 years. COMMAND DECODE AND CONTROL LOGIC WRITE CONTROL AND TIMING LOGIC WRITE PROTECT LOGIC X DECODE LOGIC

512 BYTE

32 X 32

64 X 32

6451 FHD F01

SPI Serial E 2PROM with Block Lock TM Protection ICmic IC MICROSYSTEMS TM

Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte ad- dresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is HIGH, the X25040 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25040 will be in the standby power mode. CS LOW enables the X25040, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is LOW, nonvolatile writes to the X25040 are disabled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvola- tile writes operate normally. WP going LOW while CS is still LOW will interrupt a write to the X25040. If the internal write cycle has already been initiated, WP going LOW will have no affect on a write. Hold (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. PIN CONFIGURATION PIN NAMES Symbol Description CS Chip Select Input SO Serial Output SI Serial Input SCK Serial Clock Input WP Write Protect Input VSS Ground VCC Supply Voltage HOLD Hold Input

6451 PGM T01

6451 FHD F02.1 CS SO WP VSS VCC HOLD SCK SI DIP/SOIC X25040

(SPI) of many popular microcontroller families. inputs must be HIGH during the entire operation.

6451 PGM T02

progress. During a write, all other bits are set to “1”. when set to a “0”, the latch is reset. tion. The X25040 is divided into four 1024-bit segments. One, two, or all four of the segments may be protected. unable to alter (write) data within the selected segments. The partitioning is controlled as illustrated below.

6451 PGM T03

Table 1. Instruction Set *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

Data input on the SI line is latched on the rising edge of SCK. Data is output on the SO line by the falling edge of SCK. Read Sequence When reading from the E 2PROM memory array, CS is first pulled LOW to select the device. The 8-bit READ instruction is transmitted to the X25040, followed by the 8-bit address. Bit 3 of the Read Data instruction con- tains address A 8. This bit is used to select the upper or lower half of the address. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached ($1FF) the address counter rolls over to address $000 allowing the read cycle to be continued indefinitely. The read operation is termi- nated by taking CS HIGH. Refer to the read E 2PROM array operation sequence illustrated in Figure 1. To read the status register, the CS line is first pulled LOW to select the device followed by the 8-bit RDSR instruction. After the read status register opcode is sent, the contents of the status register are shifted out on the SO line. Figure 2 illustrates the read status register sequence. Write Sequence Prior to any attempt to write data into the X25040, the “write enable” latch must first be set by issuing the WREN instruction (See Figure 3). CS is first taken LOW, then the WREN instruction is clocked into the X25040. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the E 2PROM memory array, the user issues the WRITE instruction, followed by the address and then the data to be written. This is minimally a twenty-four clock operation. CS must go LOW and remain LOW for the duration of the operation. The host may continue to write up to 4 bytes of data to the X25040. The only restriction is the 4 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written. For the write operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of data byte N is clocked in. If it is brought HIGH at any other time the write operation will not be completed. Refer to Figures 4 and 5 below for a detailed illustration of the write sequences and time frames in which CS going HIGH are valid. To write to the status register, the WRSR instruction is followed by the data to be written. Data bits 0, 1, 4, 5, 6 and 7 must be “0”. Figure 6 illustrates this sequence. While the write is in progress following a status register or E 2PROM write sequence, the status register may be read to check the WIP bit. During this time the WIP bit will be HIGH. Hold Operation The HOLD input should be HIGH (at V IH) under normal operation. If a data transfer is to be interrupted HOLD can be pulled LOW to suspend the transfer until it can be resumed. The only restriction is the SCK input must be LOW when HOLD is first pulled LOW and SCK must also be LOW when HOLD is released. The HOLD input may be tied HIGH either directly to V CC or tied to VCC through a resistor.

Figure 1. Read E2PROM Array Operation Sequence Figure 2. Read Status Register Operation Sequence

• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset. Data Protection The following circuitry has been included to prevent inadvertent writes:
• The “write enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “write enable” latch.
• CS must come HIGH at the proper clock count in order to start a write cycle. 0123456789 1 0 1 1 1 2 1 3 1 4 76543210 DATA OUT CS SCK SI SO MSB HIGH IMPEDANCE INSTRUCTION

6451 ILL F13

6451 FHD F14

Figure 3. Write Enable Latch Sequence Figure 4. Byte Write Operation Sequence

6451 ILL F05

Figure 5. Page Write Operation Sequence Figure 6. Write Status Register Operation Sequence

6451 FHD F07

6451 ILL F08

*COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin with Respect to V Lead Temperature CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V. Symbol Test Max. Units Conditions C OUT (2) Output Capacitance (SO) 8 pF V OUT = 0V C IN(2) Input Capacitance (SCK, SI, CS, WP, HOLD)6 p F V IN = 0V 6451 PGM T09.1 RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0 °C +70 °C Industrial –40 °C +85 °C Military –55 °C +125 °C 6451 PGM T05.1 Supply Voltage Limits X25040 5V ±10% X25040-3 3V to 5.5V X25040-2.7 2.7 to 5.5V 6451 PGM T06.1 POWER-UP TIMING Symbol Parameter Min. Max. Units tPUR (2) Power-up to Read Operation 1 ms tPUW (2) Power-up to Write Operation 5 ms

6451 PGM T08

Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Max. Units Test Conditions ICC VCC Supply Current (Active) 3 mA SCK = V CC x 0.1/VCC x 0.9 @ 1MHz, SO = Open ISB VCC Supply Current (Standby) 150 µA CS = VCC , VIN = VSS or VCC – 0.3V ILI Input Leakage Current 10 µAV IN = VSS to VCC ILO Output Leakage Current 10 µAV OUT = VSS to VCC VIL(1) Input LOW Voltage –1 V CC x 0.3 V VIH(1) Input HIGH Voltage V CC x 0.7 VCC + 0.5 V VOL Output LOW Voltage 0.4 V I OL = 2mA VOH Output HIGH Voltage V CC –0.8 V I OH = –1mA 6451 PGM T07.3

EQUIVALENT A.C. LOAD CIRCUIT AT 5V V CC A.C. TEST CONDITIONS Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Level VCC x 0.5

6451 PGM T10

A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing Symbol Parameter Min. Max. Units fSCK Clock Frequency 0 1 MHz tCYC Cycle Time 1000 ns tLEAD CS Lead Time 500 ns tLAG CS Lag Time 500 ns tWH Clock HIGH Time 400 ns tWL Clock LOW Time 400 ns tSU Data Setup Time 100 ns tH Data Hold Time 100 ns tRI Data In Rise Time 2 µs tFI Data In Fall Time 2 µs tHD HOLD Setup Time 200 ns tCD HOLD Hold Time 200 ns tCS CS Deselect Time 500 ns tWC (4) Write Cycle Time 10 ms 6451 PGM T11.1 Data Output Timing Symbol Parameter Min. Max. Units fSCK Clock Frequency 0 1 MHz tDIS Output Disable Time 500 ns tV Output Valid from Clock LOW 400 ns tHO Output Hold Time 0 ns tRO (3) Output Rise Time 300 ns tFO (3) Output Fall Time 300 ns tLZ HOLD HIGH to Output in Low Z 100 ns tHZ HOLD LOW to Output in High Z 100 ns 6451 PGM T12.1 Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. 6451 FHD F12.1 2.16KΩ 3.07KΩ OUTPUT 100pF

6451 FHD F10

MSB OUT MSB–1 OUT LSB OUT ADDR LSB IN tCYC tV tHO tWL tWH tDIS 6451 FHD F09.1 tLAG

6451 FHD F11

3926 FHD F01

NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) REF. PIN 1 INDEX 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) PIN 1 SEATING PLANE 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.020 (0.51) TYP. 0.010 (0.25) 15° 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) MAX. 0.325 (8.25) 0.300 (7.62)

0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8° X 45° 3926 FHD F22.1 8-LEAD PLASTIC SMALL OUTLINE GULL WING P ACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 0.250" 0.050" TYPICAL 0.050" TYPICAL 0.030" TYPICAL

8 PLACESFOOTPRINT

ORDERING INFORMATION

Blank = 5V ±10% 3 = 3V to 5.5V 2.7V = 2.7V to 5.5V Temperature Range Blank = Commercial = 0 °C to +70 °C I = Industrial = –40 °C to +85 °C M = Military = –55 °C to +125°C Package P = 8-Lead Plastic DIP S = 8-Lead SOIC G = RoHS compliant lead free Blank = 8-Lead SOIC P = 8-Lead Plastic DIP Blank = 5V D = 3V to 5.5V, 0 °C to +70 °C E = 3V to 5.5V, –40 °C to +85 °C F = 2.7V to 5.5V, 0 °C to +70 °C G = 2.7V to 5.5V, –40 °C to +85 °C LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implie d, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to disco ntinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with app ropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Part Mark Convention X25040 X G X G= RoHS Compliant Lead Free package Blank = Standard package. Non lead free