X24C01A ICMIC | Alldatasheet
Document overview
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Technical content
This X24C01A d evice has been acquired by IC MICROSYSTEMS from Xicor, Inc.
DESCRIPTION
The X24C01A is a CMOS 1024 bit serial E 2PROM, internally organized 128 x 8. The X24C01A features a serial interface and software protocol allowing oper ation on a simple two wire bus. Three address inputs allow up to eight devices to share a common two wire bus. Xicor E 2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. Available in an eight pin DIP and SOIC package.
FEATURES
- 2.7V to 5.5V Power Supply
- Low Power CMOS — Active Current Less Than 1 mA —Standby Current Less Than 50 µA
- Internally Organized 128 x 8
- Self Timed Write Cycle — Typical Write Cycle Time of 5 ms
- 2 Wire Serial Interface — Bidirectional Data Transfer Protocol
- Four Byte Page Write Operation — Minimizes Total Write Time Per Byte
- High Reliability — Endurance: 100,000 Cycles —Data Retention: 100 Years
- New Hardwire – Write Control Function © Xicor, 1991 Patents Pending Characteristics subject to change without notice 1K X24C01A 128 x 8 Bit Serial E 2PROM FUNCTIONAL DIAGRAM
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+COMPARATOR H.V. GENERATION TIMING & CONTROL WORD ADDRESS COUNTER XDEC YDEC DOUT ACK E2PROM 32x32 DATA REGISTER START CYCLE (8) V CC R/W PIN (4) V SS (5) SDA (6) SCL (3) A 2 (2) A 1 (1) A 0 DOUT LOAD INC CK (7) WC 3841-1 ICmic IC MICROSYSTEMS TM
Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire -ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Guide- lines for Calculating Typical Values of Bus Pull-Up Resistors graph. Address (A 0, A 1, A 2) The address inputs are used to set the least significant three bits of the seven bit slave address. These inputs can be static or actively driven. If used statically they must be tied to V SS or V CC as appropriate. If actively driven, they must be driven to V SS or to V CC . WRITE CONTROL (WC) The Write Control input c ontrols the ability to write to the device. When WC is LOW (tied to V SS ) the X24C01A will be enabled to perform write operations. When WC is HIGH (tied to V CC ) the internal high voltage circuitry will be disabled and all writes will be disabled. DEVICE OPE RATION The X24C01A supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X24C01A will be considered a slave in all applications. VCC WC SCL SDA VSS X24C01A PIN CONFIGURATION
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A0–A 2 Address Inputs SDA Serial Data SCL Serial Clock WC Write Control VSS Ground VCC +5V
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Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are re- served for indicating start and stop conditions. Refer to Figures 1 and 2. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA wh en SCL is HIGH. The X24C01A continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. DIP/SOIC
Figure 1. Data Validity Figure 2. Definition of Start and St op transmitting device has released the bus. to acknowledge that it received the eight bits of data. after the receipt of each subsequent eight bit word. place the device into a known state. Figure 3. Acknowledge Response From Receiver
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begins the internal write cycle to the nonvolatile memory. address, acknowledge and data transfer sequence. defined by the state of the A 0, A 1 and A 2 inputs. selected, when set to zero a write operation is selected. Figure 5. Byte Write Figure 6. Page Write
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The X24C01A is capable of an four byte page write operation. It is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data word is transferred, the master can transmit up to three more words. After the receipt of each word, the X24C01A will respond with an acknowledge. After the receipt of each word, the two low order address bits are internally incremented by one. The high order five bits of the address remain constant. If the master should transmit more than four words prior to generating the stop condition, the address coun ter will “roll over” and the previously written data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowledge and data transfer sequence. Acknowledge Polling The disabling of the inputs, during the internal write operation, can be used to take advantage of the typical 5 ms write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation the X24C01A initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the X24C01A is still busy with the write operation no ACK will be returned. If the X24C01A has completed the write operation an ACK will be returned and the master can then proceed with the next read or write operation (See Flow 1). READ OPERATIONS Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read and sequential read. It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition. Flow 1. ACK Polling Sequence
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ADDRESS AND R/W = 0 ACK RETURNED? NEXT OPERATION A WRITE? ISSUE BYTE ADDRESS PROCEED ISSUE STOP NO YES YES PROCEED ISSUE STOP NO
acknowledge and by issuing a stop condition. Figure 7. Current Address Read
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Figure 8. Random Read
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an acknowledge and by issuing a stop condition. Figure 9. Sequential Read Figure 10. Typical System Configuration
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ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin with Lead Temperature (Soldering, *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0 °C 70 °C Industrial –40 °C +85 °C Military –55 °C +125 °C
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X24C01A 4.5V to 5.5V X24C01A-3.5 3.5V to 5.5V X24C01A-3 3V ± 5.5V X24C01A-2.7 2.7V to 5.5V
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D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified) Limits Symbol Parameter Min. Max. Units Test Conditions lCC1 Power Supply Current 1 mA SCL = V CC x 0.1/V CC x 0.9 Levels (read) @ 100 KHz, SDA = Open, All Other Inputs = GND or V CC – 0.3V ICC2 Power Supply Current 2 mA SCL = V CC x 0.1/V CC x 0.9 Levels (write) @ 100 KHz, SDA = Open, All Other Inputs = GND or V CC – 0.3V I SB (1) Standby Current 50 ∝ A SCL = SDA = V CC – 0.3V, All Other Inputs = GND or V CC , V CC = 5.5V I SB (1) Standby Current 30 ∝ A SCL = SDA = V CC – 0.3V, All Other Inputs = GND or V CC, VCC = 3.3V + 10% ILI Input Leakage Current 10 ∝ A VIN = GND to V CC ILO Output Leakage Current 10 ∝ A VOUT = GND to V CC V lL (2) Input Low Voltage –1.0 VCC x 0.3 V V IH (2) Input High Voltage VCC x 0.7 VCC + 0.5 V VOL Output Low Voltage 0.4 V IOL = 3 mA
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CAPACITANCE T A = 25 °C, f = 1.0MHZ, V CC = 5V Symbol Test Max. Units Conditions C I/O (3) Input/Output Capacitance (SDA) 8 pF VI/O = 0V C IN (3) Input Capacitance (A 0, A 1, A 2, SCL, WC) 6 pF VIN = 0V
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Notes: (1) Must perform a stop command prior to measurement. (2) V IL min. and V IH max. are for reference only and are not tested. (3) This parameter is periodically sampled and not 100% tested.
A.C. CONDITIONS OF TEST Input Pulse Levels VCC x 0.1 to V CC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Levels VCC x 0.5
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Note: (4)t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested.
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EQUIVALENT A.C. LOAD CIRCUIT
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5.0V 1533 Ο 100pF Output Read & Write Cycle L imits Symbol Parameter Min. Max. Units fSCL SCL Clock Frequency 0 100 KHz TI Noise Suppression Time Constant at SCL, SDA Inputs 100 ns tAA SCL Low to SDA Data Out Valid 0.3 3.5 ∝ s tBUF Time the Bus Must Be Free Before a New Transmission Can Start 4.7 ∝ s tHD:STA Start Condition Hold Time 4.0 ∝ s tLOW Clock Low Period 4.7 ∝ s tHIGH Clock High Period 4.0 ∝ s tSU:STA Start Condition Setup Time 4.7 ∝ s tHD:DAT Data In Hold Time 0 ∝ s tSU:DAT Data In Setup Time 250 ns tR SDA and SCL Rise Time 1 ∝ s tF SDA and SCL Fall Time 300 ns tSU:STO Stop Condition Setup Time 4.7 ∝ s tDH Data Out Hold Time 300 ns
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A.C. CHARACTERISTICS LIMITS (Over recommended operating conditions unless otherwise specified) Bus Timing POWER -UP TIMING Symbol Parameter Max. Units t PUR (4) Power-Up to Read Operation 1 ms t PUW (4) Power-Up to Write Operation 5 ms
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tSU:STA tHD:STA tHD:DAT tSU:DAT tLOW tSU:STO tR tBUF SCL SDA IN SDA OUT tDH tAA tF tHIGH
Symbol Parameter Min. Typ. (5) Max. Units t WR (6) Write Cycle Time 5 10 ms
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The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the X24C01A bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. Write Cycle Timing SDA 8th BIT WORD n ACK tWR STOP CONDITION START CONDITION X24C01A ADDRESS SCL
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Guidelines for Calculating Typical Values of Bus Pull-Up Resistors SYMBOL TABLE Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance OUTPUTS INPUTS WAVEFORM
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BUS CAPACITANCE (pF) MIN. RESISTANCE MAX. RESISTANCE RMAX = CBUS tR RMIN = IOL MIN VCC MAX =1.8K Ο Notes: (5) Typical values are for T A = 25 °C and nominal supply voltage (5V). (6) t WR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device requires to perform the internal write operation. RESISTANCE (K Ο )
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MIL LIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) REF. PIN 1 INDEX 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) PIN 1 SEATING PLANE 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) TYP. 0.010 (0.25) 15 ° 8-LEAD PLASTIC DUAL IN -LINE PACKAGE TYPE P HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) MAX. 0.325 (8.25) 0.300 (7.62) PACKAGING INFORMATION
0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7 0.016 (0.41) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8 ° X 45 ° 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESIS IN M ILLIMETERS) PACKAGING INFORMATION
ORDERING INFORMATION
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or re garding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time an d without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Device VCC Limits Blank= 5V ± 10% 3.5 = 3.5V to 5.5V 3 = 3.3 ± 10% Temperature Range Blank = Commercial = 0 °C to +70 °C I = Industrial = –40 °C to +85 °C M = Military = –55 °C to +125 °C Package P = 8-Lead Plastic DIP S8 = 8-Lead SOIC X24C01A P T G -V G = RoHS compliant Lead Free package Blank = Standard package , non lead free