X24645 ICMIC | Alldatasheet

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Technical content

Advanced 2-Wire Serial E 2PROM with Block Lock TM Protection 64K 8192 x 8 Bit This X24645 device has been acquired by IC MICROSYSTEMS from Xicor, Inc.  Xicor, 1995, 1996 Patents Pending Characteristics subject to change without notice 2783-3.5 5/13/96 T1/C0/D0 NS 1 X24645 FUNCTIONAL DIAGRAM

FEATURES

  • 2.7V to 5.5V Power Supply
  • Low Power CMOS — Active Read Current Less Than 1mA —Active Write Current Less Than 3mA —Standby Current Less Than 1 ∝ A
  • Internally Organized 8192 x 8
  • New Programmable Block Lock Protection — Software Write Protection —Programmable hardware Write Protect
  • Block Lock (0, 1/4, 1/2, or all of the E 2PROM array)
  • 2 Wire Serial Interface
  • Bidirectional Data Transfer Protocol
  • 32 Byte Page Write Mode — Minimizes Total Write Time Per Byte
  • Self Timed Write Cycle — Typical Write Cycle Time of 5ms
  • High Reliability — Endurance: 100,000 Cycles —Data Retention: 100 Years
  • Available Packages — 8-Lead PDIP —8-Lead SOIC (JEDEC) —14-Lead SOIC (JEDEC) — 20 -Lead TSSOP

DESCRIPTION

The X24645 is a CMOS 65,536-bit serial E 2PROM, internally organized 8192 x 8. The X24645 features a serial interface and software protocol allowing operation on a simple two wire bus. Two device select inputs (S 1, S 2) allow up to four devices to share a common two wire bus. A Write Protect Register at the highest address location, 1FFFh, provides three new write protection features: Software Write Protect, Block Write Protect, and Hardware Write Protect. The Software Write Protect feature prevents any nonvolatile writes to the X24645 until the WEL bit in the write protect register is set. The Block Write Protection feature allows the user to individually write protect four blocks of the array by programming two bits in the write protect register. The Programmable Hardware Write Protect feature allows the user to install the X24645 with WP tied to V CC , program the entire memory array in place, and then enable the hardware write protection by programming a WPEN bit in the write protect register. After this, selected blocks of the array, including the write protect register itself, are permanently write protected, as long as WP remains HIGH. START STOP LOGIC CONTROL LOGIC SLAVE ADDRESS REGISTER +COMPARATOR H.V. GENERATION TIMING & CONTROL WORD ADDRESS COUNTER XDEC YDEC DOUT ACK E2PROM

256 X 256

2783 ILL F01

ICmic E 2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. PIN DESC RIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pull- up resistor selection graph at the end of this data sheet. Device Select (S 1, S 2) The device select inputs (S 1, S 2) are used to set the first and second bits of the 8-bit slave address. This allows up to four X24645 devices to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to V SS or V CC as appropriate. If actively driven, they must be driven with CMOS levels (driven to V CC or V SS ). Write Protect (WP) The write protect input controls the hardware write protect feature. When held LOW, hardware write protection is disabled and the X24645 can be written normally. When this input is held HIGH, and the WPEN bit in the write protect register is set HIGH, write protection is enabled, and nonvolatile writes are disabled to the selected blocks as well as the write protect register itself. PIN NAMES 2783 FRM T01.1 Symbol Description S1, S2 Device Select Inputs SDA Serial Data SCL Serial Clock WP Write Protect VSS Ground VCC Supply Voltage NC No Connect PIN CONFIGURATIONS VCC WP SCL SDA NC VSS X24645 8-LEAD DIP & SOIC NC NC NC VSS NC NC NC VCC WP SCL SDA NC X24645 14 -LEAD SOIC NC VCC WP NC NC NC SCL SDA NC NC 2783 ILL F02.4 NC NC NC NC NC VSS NC NC X24645 20 -LEAD TSSOP

Figure 3. Acknowledge Response From Receiver after the transmitting device has released the bus. that it received the eight bits of data. Refer to Figure 3. after the receipt of each subsequent 8-bit word. place the device into a known state.

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Figure 6. Page W rite The X24645 is capable of a 32-byte page write operation. each byte, the X24645 will respond with an acknowledge. host can then proceed with the read or write operation.

2783 ILL F09

Figure 7. Current Address Read Figure 8. Random Read ninth clock cycle and then issue a stop condition. ed by one or the exact address of the last byte written. sequence of address, acknowledge and data transfer. first perform a “dummy” write operation. and the slave address with the R/W bit set HIGH.

2783 ILL F11

Figure 10. Typical System Configuration acknowledge and data transfer sequence.

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Figure 9. Sequential Read

Figure 11. Write Protect Register If WEL = “0” then “no A CK” after first byte of input data. “1” and then writing 0000011x to address 1FFFh. when the part powers -up again. changed (the device remains at step 2).

control the programmable hardware write protect feature. when either the WP pin is LOW or the WPEN bit is “0”. block-protected sections in the memory array. Table 1. Block Protect Bits

2783 FRM T02

Table 2. Write Protect Status Table

ABSOLUT E MAXIMUM RATINGS* Temperature under Bias Voltage on any Pin with Lead Temperature (Solde ring, *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. D.C. OPERATING CHARACTERISTICS 2783 FRM T06.2 CAPACITANCE T A = +25 °C, f = 1MHz, V CC = 5V 2783 FRM T07.1 Notes: (1)Must perform a stop command prior to measurement. (2)V IL min. and V IH max. are for reference only and are not 100% tested. (3)This parameter is periodically sampled and not 100% tested. Limits Symbol Parame ter Min. Max. Units Test Conditions ICC1 VCC Supply Current (Read) 1 mA SCL = V CC X 0.1/V CC X 0.9 Levels @ 100KHz, SDA = Open, All Other Inputs = V SS or V CC – 0.3V ICC2 VCC Supply Current (Write) 3 mA ISB1 (1) VCC Standby Current 50 ∝ A SCL = SDA = V CC , All Other Inputs = VSS or V CC – 0.3V, VCC = 5V ± 10% ISB2 (1) VCC Standby Current 1 ∝ A SCL = SDA = V CC , All Other Inputs = VSS or V CC – 0.3V, VCC = 2.7V ILI Input Leakage Current 10 ∝ A VIN = VSS to V CC ILO Output Leakage Current 10 ∝ A VOUT = VSS to V CC VlL (2) Input LOW Voltage –1 VCC x 0.3 V VIH (2) Input HIGH Voltage VCC x 0.7 VCC + 0.5 V VOL Output LOW Voltage 0.4 V IOL = 3mA, V CC = 4.5V Symbol Parameter Max. Units Test Conditions CI/O (3) Input/Output Capacitance (SDA) 8 pF VI/O = 0V CIN (3) Input Capacitance (S 1, S2, SCL) 6 pF VIN = 0V RECOMMENDED OPERATING CONDITIONS

2783 FRM T04

Temperature Min. Max. Commercial 0 °C +70 °C Industrial –40 °C +85 °C Military –55 °C +125 °C 2783 FRM T05 Supply Voltage Limits X24645 4.5V to 5.5V X24645-2.7 2.7V to 5.5V

A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read & Write Cycle Limits 2783 FRM T09.2 POWER-UP TIMING (4)

2783 FRM T10

Notes: (4)t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiated. These parameters are peri odically sampled and not 100% tested. Symbol Parameter Min. Max. Units fSCL SCL Clock Frequency 0 100 KHz TI Noise Suppression Time Constant at SCL, SDA Inputs 100 ns tAA SCL LOW to SDA Data Out Valid 0.3 3.5 ∝ s tBUF Time the Bus Must Be Free Before a New Transmission Can Start 4.7 ∝ s tHD:STA Start Condition Hold Time 4 ∝ s tLOW Clock LOW Period 4.7 ∝ s tHIGH Clock HIGH Period 4 ∝ s tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 4.7 ∝ s tHD :DAT Data In Hold Time 0 ∝ s tSU:DAT Data In Setup Time 250 ns tR SDA and SCL Rise Time 1 ∝ s tF SDA and SCL Fall Time 300 ns tSU:STO Stop Condition Setup Time 4.7 ∝ s tDH Data Out Hold Time 300 ns Symbol Parameter Max. Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 5 ms A.C. CONDITIONS OF TEST

2783 FRM T08

Input Pulse Levels VCC x 0.1 to V CC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Levels VCC X 0.5 EQUIVALENT A.C. LOAD CIRCUIT 2783 ILL F16.1 1.53K Ο 100pF OUTPUT

Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the X24645 bus interface circuits are di sabled, SDA is allowed to remain HIGH, and the device does not respond to its slave address. Bus Timing

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tSU:STA tHD:STA tHD:DAT tSU:DAT tLOW tSU:STO tR tBUF SCL SDA IN SDA OUT tDH tAA tF tHIGH Write Cycle Limits

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Symbol Parameter Min. Typ. (5) Max. Units TWR (6) Write Cycle Time 5 10 ms Bus Timing

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Notes: (5)Typical values are for T A = 25 °C and nominal supply voltage (5V). (6)t WR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. Guideline s for Calculating Typical Values of Bus Pull-Up Resistors

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BUS CAPACITANCE (pF) MIN. RESISTANCE MAX. RESISTANCE RMAX = CBUS tR RMIN = IOL MIN VCC MAX =1.8K Ο RESISTANCE (K Ο )

3926 FHD F01

NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) REF. PIN 1 INDEX 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) PIN 1 SEATING PLANE 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) TYP. 0.010 (0.25) 15 ° 8-LEAD PLASTIC DUAL IN -LINE PACKAGE TYPE P HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) MAX. 0.325 (8.25) 0.300 (7.62)

0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7 ° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) ° – 8 ° X 45 ° 3926 FHD F22.1 8-LEAD PLASTIC SMAL L OUTLINE GULL WING PACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050" TYPICAL 0.050" TYPICAL 0.030" TYPICAL

8 PLACES FOOTPRINT

0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.020 (0.51) PIN 1 PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7 ° 0.016 (0.41) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° – 8 ° X 45 ° 3926 FHD F10.1 14 -LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050" Typical 0.050" Typical 0.030" Typical

14 Places FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 20 -LEAD PLASTIC, TSSOP PACKAGE TYPE V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) BSC .025 (.65) BSC .252 (6.4) .300 (6.6) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) ° – 8 ° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)

3926 FHD F45

ORDERING INFORMATION

G = RoHS Compliant Lead Free package Blank = Standard package. Non lead free VCC Range Blank = 5V ±10% 2.7 = 2.7V to 5.5V Temperature Range Blank = 0 °C to +70 °C I = –40 °C to +85 °C M = –55 °C to +125 °C Package P = 8-Lead Plastic DIP S8 = 8-Lead SOIC (JEDEC) P = 8-Lead Plastic DIP S = 14-Lead SOIC Blank = 8-Lead SOIC (JEDEC) V = 20-Lead TSSOP G = RoHS compliant lead free Blank = 4.5V to 5.5V, 0 °C to +70 °C I = 4.5V to 5.5V, –40 °C to +85 °C F = 2.7V to 5.5V, 0 °C to +70 °C G = 2.7V to 5.5V, –40 °C to +85 °C X24645 XG X LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no res ponsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life suppor t device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. S = 14-Lead SOIC V = 20 -Lead TSSOP