X24026 ICMIC | Alldatasheet
Document overview
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Technical content
∧ Xicor, Inc. 1994, 1995, 1996 Patents Pending 7020-1.2 2/24/97 T1/C0/D2 SH 1 Characteristics subject to change without notice 2K X24026 256 x 8 Bit Serial E2PROM
FEATURES
- 2.7V to 5.5V Power Supply
- Low Power CMOS — Active Current Less Than 1mA —Standby Current Less Than 50 µA
- Internally Organized 256 x 8
- Self Timed Write Cycle — Typical Write Cycle Time of 5 ms
- 2 Wire Serial Interface — Bidirectional Data Transfer Protocol
- Four Byte Page Write Operation — Minimizes Total Write Time Per Byte
- High Reliability — Endurance: 100,000 Cycles —Data Retention: 100 Years — ESD Protection > 2KV
DESCRIPTION
The X24026 is a CMOS 2048 bit serial E 2PROM, internally organized 256 x 8. The X24026 features a serial interface and software protocol allowing o peration on a simple two wire bus. Xicor E 2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. Available in DICE form with ISO 7816 compatible pin out. This X24026 device has been acquired by IC MICROSYSTEMS from Xicor, Inc. FUNCTIONAL DIAGRAM START STOP LOGIC CONTROL LOGIC SLAVE ADDRESS REGISTER +COMPARATOR H.V. GENERATION TIMING & CONTROL WORD ADDRESS COUNTER XDEC YDEC DOUT ACK E PROM 2
64 X 32
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Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire -ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Guidelines for Calculating Typical Values of Bus Pull-Up Resistors graph. DIE CONFIGURATION PIN DESCRIPTIONS
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The X24026 supports a bidirectional bus oriented proto- col. X24026 will be considered a slave in all applications. HIGH to LOW transition of SDA when SCL is HIGH. command until this condition has been met. Figure 1. Data Validity
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issued after the transmitting device has released the bus. eight bits of data. Refer to Figure 3. receipt of each subsequent eight bit word. the device into a known state . Figure 2. Definition of Start and Stop Figure 3. Acknowledge Response from Receiver
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4). For the X24026 this is fixed as 1010[B]. The next three significant bits are reserved address bits. selected, when set to zero a write operations is selected . X24026 outputs an acknowledge on the SDA line. execute a read or write operation. begins the internal write cycle to the nonvolatile memory. address, acknowledge and data transfer sequence. Figure 5. Byte Write Figure 6. Page Write
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The X24026 is capable of a four byte page write opera- tion. It is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data word is transferred, the master can transmit up to three more words. After the receipt of each word, the X24026 will respond with an acknowledge. After the receipt of each word, the two low order address bits are internally incremented by one. The high order six bits of the address remain constant. If the master should transmit more than four words prior to generating the stop condition, the address counter will “roll o ver” and the previously written data will be overwritten. As with the byte write operation, all inputs are disabled until comple- tion of the internal write cycle. Refer to Figure 6 for the address, acknowledge and data transfer sequence. Acknowledge Polling The disabling of the inputs, during the internal write oper- ation, can be used to take advantage of the typical 5 ms write cycle time. Once the st op condition is issued to indicate the end of the host’s write operation the X24026 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition fol- lowed by the slave address for a write operation. If the X24026 is still busy with the write operation no ACK will be returned. If the X24026 has completed the write oper- ation an ACK will be returned and the master can then proceed with the next read or write operation. READ OPERATIONS Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read and sequential read. It should be noted that the ninth clock cycle of the read operation is not a “don’t care .” To terminate a read opera- tion, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition . Flow 1. ACK Polling Sequence
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ISSUE SLAVE_ ADDRESS AND R/W = 0 ACK RETURNED? NEXT OPERATION A WRITE? ISSUE BYTE ADDRESS PROCEED ISSUE STOP NO YES YES PROCEED ISSUE STOP NO
sequence of address, acknowledge and data transfer. Figure 7. Current Address Read
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Figure 9. Sequential Read
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ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin with *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS
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Temperature Min. Max. Commercial 0°C 70 °C Supply Voltage Limits X24026 4.5V to 5.5V X24026-2.7 2.7V to 5.5V D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified).
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CAPACITANCE TA = 25 °C, f = 1 MHz, V CC = 5V
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Notes: (1)Mu st perform a stop command prior to measurement. (2)V IL min. and V IH max. are for reference only and are not tested. (3)This parameter is periodically sampled and not 100% tested. Symbol Parameter Limits Units Test Conditions Min. Max. lCC1 Power Supply Current (read) 1 mA SCL = V CC x 0.1/V CC x 0.9 Levels @
100 KHz, SDA = Open lCC2 Power Supply Current (write) 2
ISB (1) Standby Current 50 ∝ A SCL = SDA = V CC – 0.3V, V CC = 5V ±10% ISB (2) Standby Current 30 ∝ A SCL = SDA = V CC – 0.3V, V CC = 3V ILI Input Leakage Current 10 ∝ A VIN = GND to V CC ILO Output Leakage Current 10 ∝ A VOUT = GND to V CC VlL (2) Input Low Voltage –1.0 VCC x 0.3 V VIH (2) Input High Voltage VCC x 0.7 VCC + 0.5 V VOL Output Low Voltage 0.4 V IOL = 3 mA Symbol Parameter Max. Units Test Conditions CI/O (3) Input/Output Capacitance (SDA) 8 pF VI/O = 0V CIN (3) Input Capacitance (SCL) 6 pF V IN = 0V
A.C. CONDITIONS OF TEST
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EQUIVALENT A.C. LOAD CIRCUIT Input Pulse Levels VCC x 0.1 to V CC x 0.9 Input Rise and Fall Times 10 ns Input and Output Timing Levels VCC x 0.5
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1533 Ο OUTPUT 100pF 5.0V A.C. CHARACTERISTICS (Over recommended operating conditions) DATA INPUT TIMING
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Notes: (4)t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. Symbol Parameter Min. Max. Units fSCL SCL Clock Frequency 0 100 KHz TI Noise Suppression Time Constant at SCL, SDA Inputs 100 ns tAA SCL Low to SDA Data Out Valid 0.3 3.5 ∝ s tBUF Time the Bus Must Be Free Before a New Transmission Can Start 4.7 ∝ s tHD:STA Start Condition Hold Time 4.0 ∝ s tLOW Clock Low Period 4.7 ∝ s tHIGH Clock High Period 4.0 ∝ s tSU:STA Start Condition Setup Time 4.7 ∝ s tHD:DAT Data In Hold Time 0 ∝ s tSU:D AT Data In Setup Time 250 ns tR SDA and SCL Rise Time 1 ∝ s tF SDA and SCL Fall Time 300 ns tSU:STO Stop Condition Setup Time 4.7 ∝ s tDH Data Out Hold Time 300 ns Symbol Parameter Max. Units t PUR (4) Power-up to Read Operation 1 ms t PUW (4) Power-up to Write Operation 5 ms
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tSU:STA t HD:STA tHD:DAT tSU:DAT tLOW tSU:STO tR tBUF SCL SDA IN SDA OUT tDH tAA tF tHIGH
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The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the X24026 bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. Write Cycle Timing Notes: (5)Typical values are for T A = 25 °C and nominal supply voltage (5V) (6)t WR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximu m time the device requires to perform the internal write operation. Symbol Parameter Min. Typ. (5) Max. Units t WR (6) Write Cycle Time 5 10 ms
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Guidelines for Calculating Typical Values of Bus Pull-Up Resistors SYMBOL TABLE
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BUS CAPACITANCE (pF) MIN. RESISTANCE MAX. RESISTANCE R MAX =CBUS tR RMIN = I OL MIN V CC MAX =1.8K Ο WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance RESISTANCE (K Ο )
8 PAD CHIP ON BOARD SMART CARD MODULE TYPE X
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3.369 ± 0.002 (85.57 ± 0.05) 2.125 ± 0.002 (53.98 ± 0.05) 0.593 ± 0.002 (15.06 ± 0.05) 3° MAX. DRAFT ANGLE (ALL AROUND) NOTES: 1. ALL DIMENSIONS ARE IN INCHES AND (MILLIMETERS). 2. SPECIFIED DIMS ARE MEASURED AT BOTTOM OF CAVITY. 3. MATERIAL: WHITE PVC MOLDED PLASTIC WITH ANTI-STATIC ADDITIVE. 4. SURFACE FINISH SUITABLE FOR OFFSET PRINTING. 0.430 ± 0.002 (10.92 ± 0.05) 0.475 ± 0.010 (12.07 ± 0.25) 0.478 ± 0.002 (12.14 ± 0.05) R. 0.125 (3.18) (4x) 0.31 ± 0.0005 (.079 ± 0.0127) SCALE: 5x A A MOLD GATE DETAIL SECTION A-A X24026 SMART CARD TYPE Y
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0.465 ± 0.002 (11.81 ± 0.05) A SECTION A-A A 0.285 (7.24) MAX. 0.420 ± 0.002 (10.67 ± 0.05) 0.210 ± 0.002 (5.33 ± 0.05) 0.105 ± 0.002 (2.67 ± 0.05) TYP. (8x) (8x) 0.105 ± 0.002 (2.67 ± 0.05) 0.008 ± 0.001 (0.20 ± 0.03) 0.233 ± 0.002 (5.92 ± 0.05) 0.174 ± 0.002 (3.71 ± 0.05) DIE 0.0235 (0.60) MAX. 0.015 (0.38) MAX. 0.008 (0.20) MAX. GLOB SIZE FR4 TAPE SEE DETAIL SHEET 3 COPPER, NICKEL PLATED, GOLD FLAS H 0.270 (6.86) MAX. SEE NOTE 7 SHT 2 . 0.069 (1.75) MIN EPOXY FREE AREA (TYP.) 0.088 (2.24) MIN EPOXY FREE AREA (TYP.) NOTE: 1.ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
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X24026: 256 x 8 CMOS Serial E 2PROM Device X24026 P T G Temperature Range Blank = Commercial = 0 °C to +70 °C Package Y = ISO, SmartCard LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by de scription regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose fa ilure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2.A critical component is any component of a life support device or system whos e failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. H = DICE (Waffle Packs) – V VCC Range 2.7 = 2.7V to 5.5V W = Wafer form X = COB SmartCard Module Blank = 4.5V to 5.5V G=RoHS Compliant Lead Free package Blank = Standard package. Non lead free