WM9711

WM9711_06 WOLFSON | Alldatasheet

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w WM9711L Low Power Audio CODEC for Portable Applications WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ Production Data, August 2006, Rev 4.3 Copyright ©2004 Wolfson Microelectronics plc

DESCRIPTION

The WM9711L is a highly integrated input / output device designed for mobile computing and communications. The device can connect directly to mono or stereo microphones, stereo headphones and a mono speaker, reducing total component count in the system. Additionally, phone input and output pins are provided for seamless integration with wireless communication devices. The WM9711L also offers five GPIO pins for interfacing to buttons or other digital devices. To monitor the battery voltage in portable systems, the WM9711L has two uncommitted comparator inputs. All device functions are accessed and controlled through a single AC-Link interface compliant with the AC’97 standard. Additionally, the WM9711L can generate interrupts to indicate low battery, dead battery, thermal cut-out and GPIO conditions. The WM9711L operates at supply voltages from 1.8 to 3.6 Volts. Each section of the chip can be powered down under software control to save power. The device is available in a small leadless 7x7mm QFN package, ideal for use in hand- held portable systems.

FEATURES

• AC’97 Rev 2.2 compatible stereo codec - DAC SNR 94dB, THD –87dB - ADC SNR 92dB, THD –87dB - Variable Rate Audio, supports all WinCE sample rates - Tone Control, Bass Boost and 3D Enhancement
• On-chip 45mW headphone driver
• On-chip 400mW mono speaker driver
• Stereo, mono or differential microphone input - Automatic Level Control (ALC)
• Auxiliary mono DAC (ring tone or DC level generation)
• Seamless interface to wireless chipset
• Up to 5 GPIO pins
• 2 comparator inputs for battery monitoring
• 1.8V to 3.6V supplies
• 7x7mm QFN

APPLICATIONS

• Personal Digital Assistants (PDA)
• Smartphones
• Handheld and Tablet Computers BLOCK DIAGRAM

w PD Rev 4.3 August 2006 TABLE OF CONTENTS

w PD Rev 4.3 August 2006

w PD Rev 4.3 August 2006 PIN CONFIGURATION

ORDERING INFORMATION

-25 to +85oC 48-lead QFN (Pb-free) MSL3 260oC WM9711LGEFL/RV -25 to +85oC 48-lead QFN (Pb-free, tape and reel) MSL3 260oC Note: Reel quantity = 2,200

w PD Rev 4.3 August 2006 PIN DESCRIPTION PIN NAME TYPE Clock Crystal Connection 1 / External Clock Input XTLOUT Digital Output Clock Crystal Connection 2 DGND1 Supply Digital Ground (return path for both DCVDD and DBVDD) SDATAOUT Digital Input Serial Data Output from Controller / Input to WM9711L BITCLK Digital Output Serial Interface Clock Output to Controller DGND2 Supply Digital Ground (return path for both DCVDD and DBVDD) SDATAIN Digital Output Serial Data Input to Controller / Output from WM9711L DCVDD Supply Digital Core Supply SYNC Digital Input Serial Interface Synchronisation Pulse from Controller RESETB Digital Input Reset (Active Low, resets all registers to their default) CREF Analogue Input Reference for analogue comparators (COMP1,2,3) AVDD2 Supply Connect to AVDD DNC Do not connect Leave this pin floating DNC Do not connect Leave this pin floating DNC Do not connect Leave this pin floating DNC Do not connect Leave this pin floating AGND1 Supply Connect to AGND PCBEEP Analogue Input Line Input to analogue audio mixers, typically used for beeps PHONE Analogue Input Phone Input (RX) MIC1 Analogue Input Left Microphone Input MIC2 Analogue Input Right Microphone Input LINEINL Analogue Input Left Line Input LINEINR Analogue Input Right Line Input AVDD Supply Analogue Supply (feeds audio DACs, ADCs, PGAs, mic boost, mixers) AGND Supply Analogue Ground VREF Analogue Output Internal Reference Voltage (buffered CAP2) MICBIAS Analogue Output Bias Voltage for Microphones (buffered CAP2 × 1.8) COMP1 Analogue Input Comparator Input 1 COMP2 Analogue Input Comparator Input 2 COMP3 Analogue Input Comparator Input 3 CAP2 Analogue In / Out Internal Reference Voltage (normally AVDD/2, if not overdriven) MONOOUT Analogue Output Mono Output, intended for Phone TX signal SPKGND Supply Speaker Ground (feeds output buffers on pins 35 and 36) LOUT2 Analogue Output Left Output 2 (Speaker, Line or Headphone) ROUT2 Analogue Output Right Output 2 (Speaker, Line or Headphone) OUT3 Analogue Output Analogue Output 3 (from AUXDAC or headphone pseudo-ground) SPKVDD Supply Speaker Supply (feeds output buffers on pins 35 and 36) HPOUTL Analogue Output Headphone Left Output HPGND Supply Headphone Ground (feeds output buffers on pins 37, 39, 41) HPOUTR Analogue Output Headphone Left Output AGND2 Supply Chip Substrate, connect to AGND HPVDD Digital In / Out Headphone Supply (feeds output buffers on pins 37, 39, 41) GPIO1 Digital In / Out GPIO Pin 1 GPIO2 / IRQ Digital In / Out GPIO Pin 2 or IRQ (Interrupt Request) Output GPIO3 Digital In / Out GPIO Pin 3 GPIO4 Digital In / Out GPIO Pin 4 (On reset, pin level configures device power up status. See Applications section for external components configuration) GPIO5 / SPDIF_OUT Digital In / Out GPIO Pin 5 or SPDIF Digital Audio Output Note: It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.

w PD Rev 4.3 August 2006 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION MIN MAX Digital supply voltages (DCVDD, DBVDD) -0.3V +3.63V Analogue supply voltages (AVDD, HPVDD, SPKVDD) -0.3V +3.63V Voltage range digital inputs DGND -0.3V DBVDD +0.3V Voltage range analogue inputs AGND -0.3V AVDD +0.3V Voltage range, COMP3 (pin31) +5V Operating temperature range, TA -25oC +85oC RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital input/output buffer supply range DBVDD 1.8 3.6 V Digital core supply range DCVDD 1.8 3.6 V Analogue supply range AVDD, HPVDD, SPKVDD 1.8 3.6 V Digital ground DCGND, DBGND V Analogue ground AGND, HPGND, SPKGND V Difference AGND to DGND Note 1 -0.3 +0.3 V Notes: AGND is normally the same potential as DGND. AVDD, DCVDD and DBVDD can all be different Digital supplies (DCVDD, DBVDD) must not exceed analogue supplies (AVDD, HPVDD, SPKVDD) by more than 0.3V

w PD Rev 4.3 August 2006

ELECTRICAL CHARACTERISTICS

DBVDD=3.3V, DCVDD = 3.3V, AVDD=HPVDD=SPKVDD =3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 18-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC to Line-Out (HPOUTL/R or MONOOUT with 10kΩ / 50pF load) Full-scale output AVDD = 3.3V, PGA gains set to 0dB V rms Signal to Noise Ratio (A-weighted) SNR dB Total Harmonic Distortion THD -3dB output -87 -80 dB Power Supply Rejection PSRR 20Hz to 20kHz dB Speaker Output (LOUT2/ROUT2 with 8Ω bridge tied load, INV=1) Output Power PO Output power is very closely correlated with THD; see below. Output Power at 1% THD PO 400 mW Abs. Max Output Power POmax 500 mW Total Harmonic Distortion THD PO=200mW -66 0.05 dB Signal to Noise Ratio (A-weighted) SNR 100 dB Headphone Output (HPOUTL/R, OUT3 or LOUT2/ROUT2 with 16Ω or 32Ω load) HPVDD=1.8V, RL=32Ω mW PO=10mW, RL=16Ω -76 PO=10mW, RL=32Ω -73 PO=20mW, RL=16Ω -75 Total Harmonic Distortion (Note 1) THD PO=20mW, RL=32Ω -78 dB Signal to Noise Ratio (A-weighted) SNR AVDD=3.3V dB Note: All THD values are valid for the output power level quoted above – for example, at HPVDD=3.3V and RL=16Ω, THD is –76dB when output power is 10mW. Higher output power is possible, but will result in a deterioration in THD.

w PD Rev 4.3 August 2006 AUDIO INPUTS Test Conditions DBVDD=3.3V, DCVDD = 3.3V, AVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 18-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT LINEINL/R, MICL/R and PHONE pins AVDD = 3.3V 1.0 AVDD = 1.8V 0.545 Full Scale Input Signal Level (for ADC 0dB Input at 0dB Gain) VINFS differential input mode (MS = 01) half of the value listed above V rms 0dB PGA gain Input Resistance RIN 12dB PGA gain kΩ Input Capacitance pF Line input to ADC (LINEINL, LINEINR, PHONE) Signal to Noise Ratio (A-weighted) SNR dB Total Harmonic Distortion THD -6dBFs -87 -80 dB Power Supply Rejection PSRR 20Hz to 20kHz dB Microphone input to ADC (MIC1/2 pins) Signal to Noise Ratio (A-weighted) SNR 20dB boost enabled dB Total Harmonic Distortion THD 20dB boost enabled -80 dB Power Supply Rejection Ratio PSRR TBD dB Common Mode Rejection Ratio CMRR Differential mic mode TBD dB AUXILIARY MONO DAC (AUXDAC) Test Conditions AVDD = 3.3V, TA = +25oC, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Resolution bits Full scale output voltage AVDD=3.3V Vrms Signal to Noise Ratio (A-weighted) SNR dB Total Harmonic Distortion THD -62 -50 dB COMPARATORS Test Conditions AVDD = 3.3V, TA = +25oC, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT COMP1, COMP2 and COMP3 (pins 29, 30, 31) Input Voltage AGND AVDD V Input leakage current <10 nA Comparator Input Offset (COMP1, COMP2 only) -50 +50 mV COMP2 delay (COMP2 only) 24.576MHz crystal 10.9 s

w PD Rev 4.3 August 2006 REFERENCE VOLTAGES Test Conditions DBVDD=3.3V, DCVDD = 3.3V, AVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 18-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio ADCs, DACs, Mixers Reference Input/Output CAP2 pin 1.6 1.65 1.7 V Buffered Reference Output VREF pin 1.6 1.65 1.7 V Microphone Bias Bias Voltage VMICBIAS 2.88 2.97 3.06 V Bias Current Source IMICBIAS mA Output Noise Voltage Vn 1K to 20kHz nV/√Hz DIGITAL INTERFACE CHARACTERISTICS Test Conditions DBVDD = 3.3V, DCVDD = 3.3V, TA = +25oC, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Logic Levels (all digital input or output pins) – CMOS Levels Input HIGH level VIH DBVDD×0.7 V Input LOW level VIL DBVDD×0.3 V Output HIGH level VOH source current = 2mA DBVDD×0.9 Output LOW level VOL sink current = 2mA DBVDD×0.1 Clock Frequency Master clock (XTLIN pin) 24.576 MHz AC’97 bit clock (BIT_CLK pin) 12.288 MHz AC’97 sync pulse (SYNC pin) kHz Note: All audio and non-audio sample rates and other timing scales proportionately with the master clock. For signal timing on the AC-Link, please refer to the AC’97 specification (Revision 2.2)

w PD Rev 4.3 August 2006 HEADPHONE / SPEAKER OUTPUT THD VERSUS POWER Headphone Power vs THD+N (32Ohm load) -100 -80 -60 -40 -20 Power (mW) THD+N (dB) Headphone Power vs THD+N (16Ohm load) -100 -80 -60 -40 -20 Power (mW) THD+N (dB)

w PD Rev 4.3 August 2006 POWER CONSUMPTION The power consumption of the WM9711L depends on the following factors. Supply voltages: Reducing the supply voltages also reduces digital supply currents, and therefore results in significant power savings especially in the digital sections of the WM9711L. Operating mode: Significant power savings can be achieved by always disabling parts of the WM9711L that are not used (e.g. audio ADC, DAC, AUXDAC, speaker driver, etc.) Mode Description 26h 14:8 24h 15:0 Other Settings Total Power V I (mA) V I (mA) V I (mA) (mW) OFF (lowest possible power) 1111111 0111111111111111 58h, SVD = 1 3.3 0.0005 3.3 3.3 0.00165 Clocks stopped 2.5 0.0004 2.5 2.5 0.001 1.8 0.0003 1.8 1.8 0.00054 LPS (Low Power Standby) 1111111 0111111111111111 3.3 0.005 3.3 3.3 0.0165 VREF maintained using 1MOhm string 2.5 0.004 2.5 2.5 0.01 1.8 0.003 1.8 1.8 0.0054 Standby Mode (ready to playback) 1110111 0111111111111111 3.3 0.56 3.3 3.3 1.848 VREF maintained using 50kOhm string 2.5 0.37 2.5 2.5 0.925 1.8 0.241 1.8 1.8 0.4338 "Idle" Mode 1100111 0111111111111111 3.3 1.1 3.3 3.3 3.63 VREF maintained using 50kOhm string 2.5 0.76 2.5 2.5 1.9 use LPS mode instead, if possible 1.8 0.508 1.8 1.8 0.9144 Phone Call - using headphone / ear speaker 0110011 0111100010101100 0Eh, bit 7 = 1 3.3 2.36 3.3 3.3 7.788 HPOUTL, HPOUTR and OUT3 active (mic gain boost) 2.5 1.838 2.5 2.5 4.595 AC-Link stopped 1.8 1.218 1.8 1.8 2.1924 Phone Call - using loudspeaker 1110011 0111101100110100 0Eh, bit 7 = 1 3.3 2.385 3.3 3.3 7.8705 AC-Link stopped (mic gain boost) 2.5 1.837 2.5 2.5 4.5925 1.8 1.218 1.8 1.8 2.1924 Record from mono microphone 1000110 0110101111111111 0Eh, bit 7 = 1 3.3 3.27 3.3 11.21 3.3 2.6 56.364 with MICBIAS (mic gain boost) 2.5 2.66 2.5 7.78 2.5 2.13 31.425 all analogue outputs disabled 1.8 1.838 1.8 5.21 1.8 1.41 15.2244 Record phone call 0000000 0000000010001000 0Eh, bit 7 = 1 3.3 9.461 3.3 12.22 3.3 2.62 80.1933 both sides mixed to mono (mic gain boost) 2.5 7.46 2.5 8.552 2.5 2.1 45.28 call using headphone / ear speaker 1.8 5.318 1.8 5.799 1.8 1.48 22.6746 DAC Playback - using loudspeaker 1000001 0001111101110111 3.3 3.45 3.3 9.884 3.3 2.6 52.5822 2.5 2.549 2.5 6.755 2.5 2.1 28.51 1.8 1.738 1.8 4.606 1.8 1.41 13.9572 DAC Playback - using headphone 0000001 0001110011101111 3.3 3.62 3.3 9.8 3.3 2.6 52.866 2.5 2.71 2.5 6.78 2.5 2.1 28.975 1.8 1.748 1.8 4.606 1.8 1.47 14.0832 DAC Playback - to Line-out 0000001 0001110011110111 3.3 3.62 3.3 9.8 3.3 2.6 52.866 2.5 2.71 2.5 6.78 2.5 2.1 28.975 1.8 1.748 1.8 4.606 1.8 1.41 13.9752 Maximum Power (everything on) 0000000 0000000000000000 0Eh, bit 7 = 1 3.3 9.593 3.3 12.26 3.3 2.62 80.7609 (mic gain boost) 2.5 7.37 2.5 8.563 2.5 2.12 45.1325 1.8 5.388 1.8 5.8 1.8 1.48 22.8024 AVDD DCVDD DBVDD Table 1 Supply Current Consumption (Simulation) Notes: All figures are at TA = +25oC, audio sample rate fs = 48kHz, with zero signal (quiescent). The power dissipated in the headphone and speaker is not included in the above table.

w PD Rev 4.3 August 2006 DEVICE DESCRIPTION INTRODUCTION The WM9711L is designed to meet the mixed-signal requirements of portable and wireless computer systems. It includes audio recording and playback, analogue comparators for battery alarms, and GPIO functions, all controlled through a single 5-wire AC-Link interface. SOFTWARE SUPPORT The basic audio features of the WM9711L are software compatible with standard AC’97 device drivers. However, to better support its unique and additional functions, Wolfson Microelectronics supplies custom device drivers for selected CPUs and operating systems. Please contact your local Wolfson Sales Office for more information. AC’97 COMPATIBILITY The WM9711L uses an AC’97 interface to communicate with a microprocessor or controller. The audio and GPIO functions are largely compliant with AC’97 Revision 2.2. The following differences from the AC’97 standard are noted: Pinout: The function of some pins has been changed to support device specific features. The PHONE and PCBEEP pins have been moved to different locations on the device package. Audio mixing: The WM9711L handles all the audio functions of a smartphone, including audio playback, voice recording, phone calls, phone call recording, ring tones, as well as simultaneous use of these features. The AC’97 mixer architecture does not fully support this. The WM9711L therefore uses a modified AC’97 mixer architecture with three separate mixers. Tone Control, Bass Boost and 3D Enhancement: These functions are implemented in the digital domain and therefore affect only signals being played through the audio DACs, not all output signals as stipulated in AC’97. Some other functions are additional to AC’97: On-chip BTL loudspeaker driver On-chip BTL driver for ear speaker (phone receiver) Auxiliary mono DAC for ring tones, system alerts etc.

2 Analogue Comparators for Battery Alarm

Programmable Filter Characteristics for Tone Control and 3D Enhancement

w PD Rev 4.3 August 2006 AUDIO PATHS OVERVIEW LINEL PGA L LOUT2 Pin 35 MONOOUT Pin 33 R ROUT2 Pin 36 OUT3 Pin 37 LINER MICR DACR LINER MICR DACR PHONE PCBEEP MONOMIX PHONE PCBEEP MONOMIX MICL MICL ALCL ALCR ALCL ALCR Left Channel

18 Bit ADC

5C:1-0 (ASS) 5C:3 (HPF) 5C:4 (ADCO) ALC:5Ch/60h/62h

12 Bit Resistor

2Eh/64h/12h:0(EN) AUXDAC AUXDAC SPKRMIX SPKRMIX FROM LINEL PGA FROM DACL to SPKR MIXER to SPKR MIXER Left Channel

18 Bit DAC

18h:12-8 00000 = +12dB 11111 = -34.5dB headphone mixer L 18h:15 10h:15 0Ah:15-12 Phone Mixer 18h:13 0Ah7:4 1Ah:13-11 10h:12-8 00000 = +12dB 11111 = -34.5dB 0Ch:0-4 00000 = +12dB 11111 = -34.5dB 0Eh:12-8 00000 = +12dB 11111 = -34.5dB 1Ah: 10-8 1Ah:14 0 = 0dB 1 = 20dB 18h:4-0 00000 = +12dB 11111 = -34.5dB 10h:5-0 00000 = +12dB 11111 = -34.5dB 0Eh:5-0 00000 = +12dB 11111 = -34.5dB headphone mixer R 0Ah:15-12 Speaker Mixer 10h:14 18h:14 0Ch:14 0Ah:11-8 Right Channel 5C:1-0 (ASS) 5C:3 (HPF) 5C:4 (ADCO) 1Ah: 2-0 Zero- cross detect 02h:12-8 00000 = 0dB 11111 = -46.5dB Zero- cross detect 04h:12-8 00000 = 0dB 11111 = -46.5dB HPOUTL Pin 39 Zero- cross detect 06h:4-0 00000 = 0dB 11111 = -46.5dB Zero- cross detect 16h:4-0 00000 = 0dB 11111 = -46.5dB Zero- cross detect 04h:4-0 00000 = 0dB 11111 = -46.5dB HPOUTR Pin 41 Zero- cross detect 02h:4-0 00000 = 0dB 11111 = -46.5dB 0dB / 20dB OEh:6-5 (MS) ALC:5Ch/60h/62h 0Eh:6-5 (MS) 5Ch:8 (DS) 02h:6 (INV) 02h:7 (ZC) 02h:15 (MUTE) 04h:7 (ZC) 04h:15 (MUTE) 06h:7 (ZC) 06h:15 (MUTE) 16h:7 (ZC) 16h:15 (MUTE) 04h:7 (ZC) 04h:15 (MUTE) 02h:7 (ZC) 02h:15 (MUTE) 16h:10-9 (OUT3SRC) 16h:8 (SRC) 1Ah:14 0 = 0dB 1 = 20dB 1Ch:6 (GRR=1) 1Ch:5-0 11111 = +30dB 00000 = -17.25dB 1Ch:6 (GRR=0) 1Ch:3:0 0000 = 0db 1111 = +22.5dB 1Ch:6 (GRL=1) 1Ch:13-8 11111 = +30dB 00000 = -17.25dB 1Ch:13 (GRL=0) 1Ch:11:8 0000 = 0db 1111 = +22.5dB Slot 3 Tone and 3D 08h / 22h / 20h:13 (3DE) Slot 4 Tone and 3D 08h / 22h / 20h:13 (3DE) AC Link AC Link AC Link PCM PGA PCM PGA ADC PGA ADC PGA PHONE PGA MICL PGA LINER PGA MICR PGA Right Channel PR3 (REF disable) & 58h:10 (SVD) 3.6k 4.5k 10h:13 0Ch:15 0Ch:15 6dB -> -15dB 6dB -> -15dB 6dB -> -15dB 6dB -> -15dB 6dB -> -15dB 18h:13 18h:15 18h:14 10h:13 10h:15 10h14 14h:15-12 0Eh:13+7 14h:15-12 14h:11-7 14h:11-8 14h:11-7 14h:11-8 1Ah:13-11 12h:15-12 12h:7-4 12h:15-12 12h:11-8 6dB -> -15dB 6dB -> -15dB 0dB / 20dB 6dB -> -15dB 6dB -> -15dB 6dB -> -15dB 6dB -> -15dB 0dB / 20dB 6dB -> -15dB 6dB -> -15dB 6dB -> -15dB 6dB -> -15dB 16h:8 (SRC) 1Ch:15 (Mute) Gain Ranges: Gain Ranges: 1Ch:15 (Mute) 14h:15-12 0Eh:14+7 14h:15-12 ADC Left 20h:7 (Loopback) AC Link ADC Right 20h:7 (Loopback) 6dB -> -15dB 0dB / 20dB MICBIAS Pin 28 LINEINL Pin 23 PCBEEP Pin 19 PHONE Pin 20 MIC1 Pin 21 LINEINR Pin 24 MIC2 Pin 22 AVDD Pin 25 VREF Pin 27 AGND Pin 24 CAP2 Pin 32 1Ah[10:8] = 011 1Ah[10:8] = 100 1Ah[10:8] = 101 1Ah[10:8] = 110 1Ah[10:8] = 111 1Ah[2:0] = 011 1Ah[2:0] = 100 1Ah[2:0] = 111 1Ah[2:0] = 101 1Ah[2:0] = 110 MS = 01 MS = 10 or 11 Note: MS bits also affect ADC input path from MICs Note: MS bits also affect sidetone path Note: MS bits also affect sidetone path Figure 1 Audio Paths Overview

w PD Rev 4.3 August 2006 AUDIO INPUTS The following sections give an overview of the analogue audio input pins and their function. For more information on recommended external components, please refer to the “Applications Information” section. LINE INPUT The LINEINL and LINEINR inputs are designed to record line level signals, and/or to mix into one of the analogue outputs. Both pins are directly connected to the record selector. The record PGA adjusts the recording volume, controlled by register 1Ch or by the ALC function. For analogue mixing, the line input signals pass through a separate PGA, controlled by register 10h. The signals can be routed into all three output mixers (headphone, speaker and phone). Each LINEIN-to-mixer path has an independent mute bit. When the line inputs are not used, the line-in PGA can be switched off to save power (see “Power Management” section). LINEINL and LINEINR are biased internally to the reference voltage VREF. Whenever the inputs are muted or the device placed into standby mode, the inputs remain biased to VREF using special anti- thump circuitry to suppress any audible clicks when changing inputs. REGISTER ADDRESS BIT LABEL DEFAULT 12:8 LINEINL VOL 01000 (0dB) LINEINL input gain 00000: +12dB … (1.5dB steps) 11111: -34.5dB 4:0 LINEINR VOL 01000 (0dB) LINEINR input gain similar to LINEINLVOL L2H Mute LINEIN path to headphone mixer 1: Mute, 0: No mute (ON) L2S Mute LINEIN path to speaker mixer 1: Mute, 0: No mute (ON) 10h L2P Mute LINEIN path to phone mixer 1: Mute, 0: No mute (ON) Table 2 Line Input Control MICROPHONE INPUT The MIC1 and MIC2 inputs are designed for direct connection to single-ended mono, stereo or differential mono microphone. If the microphone is mono, the same signal appears on both left and right channels. In stereo mode, MIC1 is routed to the left and MIC2 to the right channel. For voice recording, the microphone signal is directly connected to the record selector. The record PGA adjusts the recording volume, controlled by register 1Ch or by the ALC function. For analogue mixing, the signal passes through a separate PGA, controlled by register 0Eh. The microphone signal can be routed into the phone mixer (for normal phone call operation) and/or the headphone mixer (using register 14h, see “Audio Mixers / Sidetone Control” section), but not into the speaker mixer (to prevent acoustic feedback from the speaker into the microphone). When the microphone inputs are not used, the microphone PGA can be switched off to save power (see “Power Management” section). MIC1 and MIC2 are biased internally to the reference voltage VREF. Whenever the inputs are muted or the device placed into standby mode, the inputs remain biased to VREF using special anti-thump circuitry to suppress any audible clicks when changing inputs. It is also possible to use the LINEINL and LINEINR pins as a second differential microphone input. This is achieved by setting the DS bit (register 5Ch, bit 11) to ‘1’. This disables the line-in audio paths

w PD Rev 4.3 August 2006 and routes the signal from LINEINL and LINEINR through the differential mic path, as if it came from the MIC1 and MIC2 pins. Only one differential microphone be used at a time. The DS bit only has an effect when MS = 01 (differential mode). REGISTER ADDRESS BIT LABEL DEFAULT Mute MIC1 path to phone mixer 1: Mute, 0: No mute (ON) M22P Mute MIC2 path to phone mixer 1: Mute, 0: No mute (ON) 12:8 LMICVOL 01000 (0dB) Left microphone volume Only used when MS = 11 Similar to MICVOL 20dB Microphone gain boost (Note 1) 1: 20dB boost ON 0: No boost (0dB gain) Microphone mode select Single-ended mono (left) left = right = MIC1 (pin 21) Volume controlled by MICVOL Differential mono mode left = right = MIC1 – MIC2 Volume controlled by MICVOL Single-ended mono (right) left = right = MIC2 (pin 22) Volume controlled by MICVOL 6:5 MS : Stereo mode MIC1 = left, MIC2 = right Left Volume controlled by LMICVOL Right volume controlled by MICVOL 0Eh Mic Volume 4:0 MICVOL 01000 (0dB) Microphone volume to mixers 00000: +12dB … (1.5dB steps) 11111: -34.5dB Reg 5Ch Additional Analogue Functions DS Differential Microphone Select 0 : Use MIC1 and MIC2 1: Use LINEL and LINER (Note 2) Table 3 Microphone Input Control Note: The 20dB gain boost acts on the input to the phone mixer only. A separate microphone boost for recording can be enabled using the BOOST bit in register 1Ah. When the LINEL and LINER are selected for differential microphone select then the MIC1 and MIC2 input pins become disabled, these signals can therefore not be routed internally to the device. MICROPHONE BIAS The MICBIAS output (pin 28) provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. The internal MICBIAS circuitry is shown below. Note that the maximum source current capability for MICBIAS is 3mA. The external biasing resistors and microphone cartridge therefore must limit the MICBIAS current to 3mA.

w PD Rev 4.3 August 2006 AGND MICBIAS = 1.8 x CAP2 = 0.9 X AVDD CAP2 WM9711L Figure 2 Microphone Bias Schematic PHONE INPUT Pin 20 (PHONE) is a mono, line level input designed to connect to the receive path of a telephony device. The pin connects directly to the record selector for phone call recording (Note: to record both sides of a phone call, one ADC channel should record the PHONE signal while the other channel records the MIC signal). The RECVOL PGA adjusts the recording volume, controlled by register 1Ch or by the ALC function. To listen to the PHONE signal, the signal passes through a separate PGA, controlled by register 0Ch. The signal can be routed into the headphone mixer (for normal phone call operation) and/or the speaker mixer (for speakerphone operation), but not into the phone mixer (to prevent forming a feedback loop). When the phone input is not used, the phone-in PGA can be switched off to save power (see “Power Management” section). PHONE is biased internally to the reference voltage VREF. Whenever the input is muted or the device placed into standby mode, the input remains biased to VREF using special anti-thump circuitry to suppress any audible clicks when changing inputs. REGISTER ADDRESS BIT LABEL DEFAULT Mute PHONE path to headphone mixer 1: Mute, 0: No mute (ON) P2S Mute PHONE path to speaker mixer 1: Mute, 0: No mute (ON) 0Ch Phone Input 4:0 PHONE VOL 01000 (0dB) PHONE input gain 00000: +12dB … (1.5dB steps) 11111: -34.5dB Table 4 Phone Input Control

w PD Rev 4.3 August 2006 PCBEEP INPUT Pin 19 (PCBEEP) is a mono, line level input intended for externally generated signal or warning tones. It is routed directly to the record selector and all three output mixers, without an input amplifier. The signal gain into each mixer can be independently controlled, with a separate mute bit for each signal path. REGISTER ADDRESS BIT LABEL DEFAULT Mute PCBEEP path to headphone mixer 1: Mute, 0: No mute (ON) 14:12 B2HVOL 010 (0dB) PCBEEP to headphone mixer gain 000: +6dB … (3dB steps) 111: -15dB B2S Mute PCBEEP path to speaker mixer 1: Mute, 0: No mute (ON) 10:8 B2SVOL 010 (0dB) PCBEEP to speaker mixer gain 000: +6dB … (3dB steps) 111: -15dB B2P Mute PCBEEP path to phone mixer 1: Mute, 0: No mute (ON) 0Ah PCBEEP input 6:4 B2PVOL 010 (0dB) PCBEEP to phone mixer gain 000: +6dB … (3dB steps) 111: -15dB Table 5 PCBEEP Control

w PD Rev 4.3 August 2006 AUDIO ADC The WM9711L has a stereo sigma-delta ADC to digitise audio signals. The ADC achieves high quality audio recording at low power consumption. The ADC sample rate can be controlled by writing to a control register (see “Variable Rate Audio”). It is independent of the DAC sample rate. To save power, the left and right ADCs can be separately switched off using the PD11 and PD12 bits, whereas PR0 disables both ADCs (see “Power Management” section). If only one ADC is running, the same ADC data appears on both the left and right AC-Link slots. HIGH PASS FILTER The WM9711L audio ADC incorporates a digital high-pass filter that eliminates any DC bias from the ADC output data. The filter is enabled by default. For DC measurements, it can be disabled by writing a ‘1’ to the HPF bit (register 5Ch, bit 3). ADC SLOT MAPPING By default, the output of the left audio ADC appears on slot 3 of the SDATAIN signal (pin 8), and the right ADC data appears on slot 4. However, the ADC output data can also be sent to other slots, by setting the ASS (ADC slot select) control bits as shown below. REGISTER ADDRESS BIT LABEL DEFAULT 0: Filter enabled (for audio) 1: Filter disabled (for DC measurements) 5Ch Additional Function Control 1:0 ASS ADC to slot mapping 00: Left = Slot 3, Right = Slot 4 (default) 01: Left = Slot 7, Right = Slot 8 10: Left = Slot 6, Right = Slot 9 11: Left = Slot 10, Right = Slot 11 Table 6 ADC Slot Mapping

w PD Rev 4.3 August 2006 RECORD SELECTOR The record selector determines which input signals are routed into the audio ADC. The left and right channels can be selected independently. This is useful for recording a phone call: one channel can be used for the RX signal and the other for the TX signal, so that both sides of the conversation are digitised. REGISTER ADDRESS BIT LABEL DEFAULT 1: Boost ADC input signal by 20dB 0 :No boost 13:12 R2P Record to phone path enable 00: Left ADC and Right ADC to phone mixer 01 : Left ADC to phone mixer 10: Right ADC to phone imixer 11 : Muted R2PBOOST 20dB Boost for ADC to phone signal 1: Boost signal by 20dB 0 :No boost 10:8 RECSL 000 Left ADC signal source 000: MIC* (pre-PGA) 001-010: Reserved (do not use this setting) 011: Speaker mix 100: LINEINL (pre-PGA) 101: Headphone Mix (left) 110: Phone Mix 111: PHONE (pre-PGA) 1Ah Record Select 2:0 RECSR 000 Right ADC signal source 000: MIC* (pre-PGA) 001-010: Reserved (do not use this setting) 011: Speaker mix 100: LINEINR (pre-PGA) 101: Headphone Mix (right) 110: Phone Mix 111: PHONE (pre-PGA) Table 7 Audio Record Selector Note: *In stereo mic mode, MIC1 is routed to the left ADC and MIC2 to the right ADC. In all mono mic modes, the same signal (MIC1, MIC2 or MIC1-MIC2) is routed to both the left and right ADCs. See “Microphone Input” section for details.

w PD Rev 4.3 August 2006 RECORD GAIN The amplitude of the signal that enters the audio ADC is controlled by the Record PGA (Programmable Gain Amplifier). The PGA gain can be programmed either by writing to the Record Gain register, or by the Automatic Level Control (ALC) circuit (see next section). When the ALC is enabled, any writes to the Record Gain register have no effect. Two different gain ranges can be implemented: the standard gain range defined in the AC’97 standard, or an extended gain range with smaller gain steps. The ALC circuit always uses the extended gain range, as this has been found to result in better sound quality. The output of the Record PGA can also be mixed into the phone and/or headphone outputs (see “Audio Mixers”). This makes it possible to use the ALC function for the microphone signal in a smartphone application. REGISTER ADDRESS BIT LABEL DEFAULT Mute Audio ADC (both channels) 1: Mute (OFF) 0: No Mute (ON) GRL Gain range select (left) 0: Standard (0 to 22.5dB, 1.5dB step size) 1: Extended (-17.25 to +30dB, 0.75dB steps) Record Volume (left) Standard (GRL=0) Extended (GRL=1) 13:8 RECVOLL 000000 XX0000: 0dB XX0001: +1.5dB … (1.5dB steps) XX1111: +22.5dB 000000: -17.25dB 000001: -16.5dB … (0.75dB steps) 111111: +30dB ZC Zero Cross Enable 0: Record Gain changes immediately 1: Record Gain changes when signal is zero or after time-out GRR Gain range select (right) Similar to GRL 1Ch Record Gain 5:0 RECVOLR 000000 Record Volume (right) Similar to RECVOLL Table 8 Record Gain Register

w PD Rev 4.3 August 2006 AUTOMATIC LEVEL CONTROL The WM9711L has an automatic level control that aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary. hold time decay time attack time input signal signal after ALC PGA gain ALC target level Figure 3 ALC Operation The ALC function is enabled using the ALCSEL control bits. When enabled, the recording volume can be programmed between –6dB and –28.5dB (relative to ADC full scale) using the ALCL register bits. HLD, DCY and ATK control the hold, decay and attack times, respectively: Hold time is the time delay between the peak level detected being below target and the PGA gain applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is above target. Decay (Gain Ramp-Up) Time is the time that it takes for the PGA gain to ramp up across 90% of its range (e.g. from –15B up to 27.75dB). The time it takes for the recording level to return to its target value therefore depends on both the decay time and on the gain adjustment required. If the gain adjustment is small, it will be shorter than the decay time. The decay time can be programmed in power-of-two (2n) steps, from 24ms, 48ms, 96ms, etc. to 24.58s. Attack (Gain Ramp-Down) Time is the time that it takes for the PGA gain to ramp down across 90% of its range (e.g. from 27.75dB down to –15B gain). The time it takes for the recording level to return to its target value therefore depends on both the attack time and on the gain adjustment required. If the gain adjustment is small, it will be shorter than the attack time. The attack time can be programmed in power-of-two (2n) steps, from 6ms, 12ms, 24ms, etc. to 6.14s. When operating in stereo, the peak detector takes the maximum of left and right channel peak values, and any new gain setting is applied to both left and right PGAs, so that the stereo image is preserved. However, the ALC function can also be enabled on one channel only. In this case, only one PGA is controlled by the ALC mechanism, while the other channel runs independently with its PGA gain set through the control register.

w PD Rev 4.3 August 2006 REGISTER ADDRESS BIT LABEL DEFAULT 15:14 ALCSEL (OFF) ALC function select 00 = ALC off (PGA gain set by register) 01 = Right channel only 10 = Left channel only 11 = Stereo (PGA registers unused) Note: Ensure that RECVOLL and RECVOLR settings (reg. 1Ch) are the same before entering this mode. 13:11 MAXGAIN 111 (+30dB) PGA gain limit for ALC 111 = +30dB 110 = +24dB ….(6dB steps) 001 = -6dB 000 = -12dB 10:9 ZC TIMEOUT Programmable zero cross timeout 11 217 x MCLK period 10 216 x MCLK period 01 215 x MCLK period 00 214 x MCLK period 62h ALC / Noise Gate Control ALCZC ALC Zero Cross enable (overrides ZC bit in register 1Ch) 0: PGA Gain changes immediately 1: PGA Gain changes when signal is zero or after time-out 15:12 ALCL 1011 (-12dB) ALC target – sets signal level at ADC input 0000 = -28.5dB FS 0001 = -27.0dB FS … (1.5dB steps) 1110 = -7.5dB FS 1111 = -6dB FS 11:8 HLD 0000 (0ms) ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms … (time doubles with every step) 1111 = 43.691s 7:4 DCY 0011 (192ms) ALC decay (gain ramp-up) time 0000 = 24ms 0001 = 48ms 0010 = 96ms … (time doubles with every step) 1010 or higher = 24.58s 60h ALC Control 3:0 ATK 0010 (24ms) ALC attack (gain ramp-down) time 0000 = 6ms 0001 = 12ms 0010 = 24ms … (time doubles with every step) 1010 or higher = 6.14s Table 9 ALC Control

w PD Rev 4.3 August 2006 MAXIMUM GAIN The MAXGAIN register sets the maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled. PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled. (Note: If ATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed to prevent clipping when long attack times are used). NOISE GATE When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise pumping”, i.e. loud hissing noise during silence periods. The WM9711L has a noise gate function that prevents noise pumping by comparing the signal level at the input pins (i.e. before the record PGA) against a noise gate threshold, NGTH. Provided that the noise gate function is enabled (NGAT = 1), the noise gate cuts in when: Signal level at ADC [dB] < NGTH [dB] + PGA gain [dB] + Mic Boost gain [dB] This is equivalent to: Signal level at input pin [dB] < NGTH [dB] The PGA gain is then held constant (preventing it from ramping up as it normally would when the signal is quiet). If the NGG bit is set, the ADC output is also muted when the noise gate cuts in. The table below summarises the noise gate control register. The NGTH control bits set the noise gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 1.5dB steps. Levels at the extremes of the range may cause inappropriate operation, so care should be taken with set–up of the function. Note that the noise gate only works in conjunction with the ALC function, and always operates on the same channel(s) as the ALC (left, right, both, or none). REGISTER ADDRESS BIT LABEL DEFAULT Noise gate function enable 1 = enable 0 = disable NGG Noise gate type 0 = PGA gain held constant 1 = mute ADC output 62h ALC / Noise Gate Control 4:0 NGTH(4:0) 00000 Noise gate threshold -76.5dBfs -75dBfs … 1.5 dB steps 11110 -31.5dBfs 11111 -30dBfs Table 10 Noise Gate Control

w PD Rev 4.3 August 2006 AUDIO DACS STEREO DAC The WM9711L has a stereo sigma-delta DAC that achieves high quality audio playback at low power consumption. Digital tone control, adaptive bass boost and 3-D enhancement functions operate on the digital audio data before it is passed to the stereo DAC. (Contrary to the AC’97 specification, they have no effect on analogue input signals or signals played through the auxiliary DAC. Nevertheless, the ID2 and ID5 bits in the reset register, 00h, are set to ‘1’ to indicate that the WM9711L supports tone control and bass boost.) The DAC output has a PGA for volume control. The DAC sample rate can be controlled by writing to a control register (see “Variable Rate Audio”). It is independent of the ADC sample rate. The left and right DACs can be separately powered down using the PD13 and PD14 control bits, whereas the PR1 bit disables both DACs (see “Power Management” section). STEREO DAC VOLUME The volume of the DAC output signal is controlled by a PGA (Programmable Gain Amplifier). It can be mixed into the headphone, speaker and phone output paths (see “Audio Mixers”). REGISTER ADDRESS BIT LABEL DEFAULT Mute DAC path to headphone mixer 1: Mute, 0: No mute (ON) D2S Mute DAC path to speaker mixer 1: Mute, 0: No mute (ON) D2P Mute DAC path to phone mixer 1: Mute, 0: No mute (ON) 12:8 DACL VOL 01000 (0dB) Left DAC Volume 00000: +12dB … (1.5dB steps) 11111: -34.5dB 18h DAC Volume 4:0 DACR VOL 01000 (0dB) Right DAC Volume similar to DACLVOL AMUTE N/A Read-only bit to indicate auto-muting 1: DAC auto-muted 0: DAC not muted 5Ch Additional Functions (1) AMEN DAC Auto-Mute Enable 1: Automatically mutes analogue output of stereo DAC if digital input is zero 0: Auto-mute OFF Table 11 Stereo DAC Volume Control

w PD Rev 4.3 August 2006 TONE CONTROL / BASS BOOST The WM9711L provides separate controls for bass and treble with programmable gains and filter characteristics. This function operates on digital audio data before it is passed to the audio DACs. Bass control can take two different forms: Linear bass control: bass signals are amplified or attenuated by a user programmable gain. This is independent of signal volume, and very high bass gains on loud signals may lead to signal clipping. Adaptive bass boost: The bass volume is amplified by a variable gain. When the bass volume is low, it is boosted more than when the bass volume is high. This method is recommended because it prevents clipping, and usually sounds more pleasant to the human ear. Treble control applies a user programmable gain, without any adaptive boost function. Treble, linear bass and 3D enhancement can all produce signals that exceed full-scale. In order to avoid limiting under these conditions, it is recommended to set the DAT bit to attenuate the digital input signal by 6dB. The gain at the outputs should be increased by 6dB to compensate for the attenuation. Cut-only tone adjustment and adaptive bass boost cannot produce signals above full- scale and therefore do not require the DAT bit to be set. REGISTER ADDRESS BIT LABEL DEFAULT 0 = OFF 1 = ON BC Bass Cut-off Frequency 0 = Low (130Hz at 48kHz sampling) 1 = High (200Hz at 48kHz sampling) Bass Intensity Code BB=0 (Normal) BB=1 (Boost) 0000 +9dB 15 (max) 0001 +9dB 0010 +7.5dB (1.5dB steps) 0111 0dB (1.5dB steps) 1011-1101 -6dB 4-2 1110 -6dB 1 (min) 11:8 BASS 1111 (OFF) 1111 Bypass (OFF) DAT -6dB attenuation 0 = Off 1 = On TC Treble Cut-off Frequency 0 = High (8kHz at 48kHz sampling) 1 = Low (4kHz at 48kHz sampling) 08h DAC Tone Control 3:0 TRBL 1111 (Disabled) Treble Intensity 0000 or 0001 = +9dB 0010 = +7.5dB … (1.5dB steps) 1011 to 1110 = -6dB 1111 = Treble Control Disabled Table 12 DAC Tone Control Note: All cut-off frequencies change proportionally with the DAC sample rate.

w PD Rev 4.3 August 2006 3D STEREO ENHANCEMENT The 3D stereo enhancement function artificially increases the separation between the left and right channels by amplifying the (L-R) difference signal in the frequency range where the human ear is sensitive to directionality. The programmable 3D depth setting controls the degree of stereo expansion introduced by the function. Additionally, the upper and lower limits of the frequency range used for 3D enhancement can be selected using the 3DFILT control bits. REGISTER ADDRESS BIT LABEL DEFAULT (disabled) 3D enhancement enable 3DLC Lower Cut-off Frequency 0 = Low (200Hz at 48kHz sampling) 1 = High (500Hz at 48kHz sampling) 3DUC Upper Cut-off Frequency 0 = High (2.2kHz at 48kHz sampling) 1 = Low (1.5kHz at 48kHz sampling) 22h DAC 3D Control 3:0 3DDEPTH 0000 3D Depth 0000: 0% (minimum 3D effect) 0001: 6.67% 1110: 93.3% 1111: 100% (maximum) Table 13 Stereo Enhancement Control Note: All cut-off frequencies change proportionally with the DAC sample rate.

w PD Rev 4.3 August 2006 AUXILIARY DAC AUXDAC is a simple 12-bit mono DAC. It can be used to generate DC signals (with the numeric input written into a control register), or AC signals such as telephone-quality ring tones or system beeps (with the input signal supplied through an AC-Link slot). In AC mode (XSLE = 1), the input data is binary offset coded; in DC mode (XSLE = 0), there is no offset. The analogue output of AUXDAC is routed directly into the output mixers. The signal gain into each mixer can be adjusted at the mixer inputs using control register 12h. In slot mode (XSLE = 1), the AUXDAC also supports variable sample rates (See “Variable Rate Audio” section). When the auxiliary DAC is not used, it can be powered down by setting AXE = 0. This is also the default setting. REGISTER ADDRESS BIT LABEL DEFAULT 0: from AUXDACVAL (for DC signals) 1: from AC-Link slot selected by AUXDACSLT (for AC signals) 14:12 AUXDAC SLT 000 AUXDAC Input Selection 000 – Slot 5, bits 8-19 (with XSLE=1) 001 – Slot 6, bits 8-19 (with XSLE=1) 010 – Slot 7, bits 8-19 (with XSLE=1) 011 – Slot 8, bits 8-19 (with XSLE=1) 100 – Slot 9, bits 8-19 (with XSLE=1) 101 – Slot 10, bits 8-19 (with XSLE=1) 110 – Slot 11, bits 8-19 (with XSLE=1) 111 – RESERVED (do not use) 64h AUDAC Input Control 11:0 AUXDAC VAL 000h AUXDAC Digital Input (with XSLE=0) 000h: minimum FFFh: full-scale A2H Mute AUXDAC path to headphone mixer 1: Mute, 0: No mute (ON) 14:12 A2HVOL 010 (0dB) AUXDAC to headphone mixer gain 000: +6dB … (3dB steps) 111: -15dB A2S Mute AUXDAC path to speaker mixer 1: Mute, 0: No mute (ON) 10:8 A2SVOL 010 (0dB) AUXDAC to speaker mixer gain 000: +6dB … (3dB steps) 111: -15dB A2P Mute AUXDAC path to phone mixer 1: Mute, 0: No mute (ON) 6:4 A2PVOL 010 (0dB) AUXDAC to phone mixer gain 000: +6dB … (3dB steps) 111: -15dB 12h AUXDAC Output Control AXE 0: AUXDAC off 1: AUXDAC enabled Table 14 AUXDAC Control

w PD Rev 4.3 August 2006 ANALOGUE AUDIO OUTPUTS The following sections give an overview of the analogue audio output pins. For more information on recommended external components, please refer to the “Applications Information” section. HEADPHONE OUTPUTS – HPOUTL AND HPOUTR The HPOUTL and HPOUTR (pins 39 and 41) are designed to drive a 16Ω or 32Ω headphone or a line output. They can also be used as line-out pins. The output signal is produced by the headphone mixer. The signal volume on HPOUTL and HPOUTR can be independently adjusted under software control by writing to register 04h. When HPOUTL and HPOUTR are not used, the output drivers can be disabled to save power (see “Power Management” section). Both pins remain at the same DC level (the reference voltage VREF) when they are disabled, so that no click noise is produced. REGISTER ADDRESS BIT LABEL DEFAULT 1: Mute (OFF) 0: No Mute (ON) 13:8 HPOUTLVOL 000000 (0dB) HPOUTL Volume 000000: 0dB (maximum) 000001: -1.5dB … (1.5dB steps) 011111: -46.5dB 1xxxxx: -46.5dB ZC Zero Cross Enable 0: Change gain immediately 1: Change gain only on zero crossings, or after time-out 04h HPOUTL / HPOUTR Volume 5:0 HPOUTRVOL 00000 (0dB) HPOUTR Volume Similar to HPOUTLVOL Table 15 HPOUTL / HPOUTR Control

w PD Rev 4.3 August 2006 EAR SPEAKER OUTPUT – OUT3 Pin 37 (OUT3) has a buffer that can drive load impedances down to 16Ω. It can be used to: Drive an ear speaker (phone receiver). The speaker can be connected differentially between OUT3 and HPOUTL, or in single-ended configuration (OUT3 to HPGND). The ear speaker output is produced by the headphone mixer. The right signal must be inverted (OUT3INV = 1), so that the left and right channel are mixed to mono in the speaker [L–(-R) = L+R]. Eliminate the DC blocking capacitors on HPOUTL and HPOUTR. In this configuration, OUT3 produces a buffered midrail voltage (AVDD/2) and is connected to the headphone socket’s ground pin (see “Applications Information”) Produce the inverse of the MONOOUT signal, for a differential mono output. Note: OUT3 can only handle one of the above functions at any given time. REGISTER ADDRESS BIT LABEL DEFAULT 1: Mute (Buffer OFF) 0: No Mute (Buffer ON) Source of OUT3 signal inverse of HPOUTR (for BTL ear speaker) VREF (for capless headphone drive) mono mix of both headphone channels (for single-ended ear speaker) 10:9 OUT3 SRC inverse of MONOOUT (for differential mono output) ZC Zero Cross Enable 0: Change gain immediately 1: Change gain only on zero crossings, or after time-out 16h OUT3 Control 5:0 OUT3 VOL 000000 (0dB) OUT3 Volume 000000: 0dB (maximum) 000001: -1.5dB … (1.5dB steps) 011111: -46.5dB 1xxxxx: -46.5dB Table 16 OUT3 Control

w PD Rev 4.3 August 2006 LOUDSPEAKER OUTPUTS – LOUT2 AND ROUT2 The LOUT2 and ROUT2 outputs are designed to differentially drive an 8Ω mono speaker. They can also be used as a stereo line-out or headphone output. For speaker drive, the LOUT2 signal must be inverted (INV = 1), so that the left and right channel are added up in the speaker [R–(-L) = R+L]. REGISTER ADDRESS BIT LABEL DEFAULT 1: Mute (OFF) 0: No Mute (ON) 13:8 LOUT2VOL 00000 (0dB) LOUT2 Volume 000000: 0dB (maximum) 000001: -1.5dB … (1.5dB steps) 011111: -46.5dB 1xxxxx: -46.5dB ZC Zero Cross Enable 0: Change gain immediately 1: Change gain only on zero crossings, or after time-out INV LOUT2 Invert 0 = No Inversion (0° phase shift) 1 = Signal inverted (180° phase shift) 02h LOUT2/ROUT2 Volume 5:0 ROUT2VOL 00000 (0dB) ROUT2 Volume Similar to LOUT2VOL 16h SRC Source of LOUT2/ROUT2 signals 0: speaker mixer (for BTL speaker) 1: headphone mixer (for stereo output) Table 17 LOUT2 / ROUT2 Control Note: For BTL speaker drive, it is recommended that LOUT2VOL = ROUT2VOL.

w PD Rev 4.3 August 2006 PHONE OUTPUT (MONOOUT) The MONOOUT output (pin 33) is intended for connection to the TX side of a wireless chipset. The signal is generated in a dedicated mono mixer; it is not necessarily a mono mix of the stereo outputs HPOUTL/R or LOUT2/ROUT2 (see “Audio Mixers” section). The MONOOUT volume can be controlled by writing to register 06h. When MONOOUT is not used, the output buffer can be disabled to save power (see “Power Management” section). The MONOOUT pin remains at the same DC level (the reference voltage on the VREF pin), so that no click noise is produced when muting or un-muting. REGISTER ADDRESS BIT LABEL DEFAULT 1: Mute 0: No Mute ZC Zero Cross Enable 0: Change gain immediately 1: Change gain only on zero crossings, or after time-out 06h MONOOUT Volume 4:0 MONOOUT VOL 00000 (0dB) MONOOUT Volume 00000: 0dB (maximum) 00001: -1.5dB … (1.5dB steps) 11111: -46.5dB Table 18 MONOOUT Control THERMAL CUTOUT The speaker and headphone outputs can drive very large currents. To protect the WM9711L from becoming too hot, a thermal cutout has been built in. If the chip temperature reaches approximately 150°C, and the ENT bit is set, the WM9711L deasserts GPIO bit 11 in register 54h, a virtual GPIO that can be set up to generate an interrupt to the CPU (see “GPIO and Interrupt Control” section). REGISTER ADDRESS BIT LABEL DEFAULT 0: Disabled 1: Enabled 54h TI Thermal cutout (virtual GPIO) 1: Temperature below 150°C 0: Temperature above 150°C See also “GPIO and Interrupt Control” section. Table 19 Thermal Cutout Control

w PD Rev 4.3 August 2006 JACK INSERTION AND AUTO-SWITCHING In a phone application, a BTL ear speaker may be connected across OUT3 and HPOUTL, and a stereo headphone on HPOUTL and HPOUTR. Typically, only one of these two output devices is used at any given time: when no headphone is plugged in, the BTL ear speaker is active, otherwise the headphone is used. The presence of a headphone can be detected using GPIO1 (pin 44) and an external pull-up resistor (see “Applications Information” section for a circuit diagram). When the jack is inserted GPIO1 is pulled low by a switch on the socket. When the jack is removed GPIO1 is pulled high by a resistor. If the JIEN bit is set, the WM9711L automatically switches between headphone and ear speaker, as shown below. REGISTER ADDRESS BIT LABEL DEFAULT Jack Insert Enable – Takes output of GPIO1 logic 58h Additional Functional Control FRC Force Ear Speaker Mode See table below Table 20 Jack Insertion / Auto-Switching (1) JIEN FRC GPIO1 MODE DESCRIPTION OUT3 STATE HPOUTL VOLUME HPOUTR VOLUME OUT3 VOLUME HPOUTL/ HPOUTR STATE X Jack insert detection disabled (headphone and ear speaker can be used at the same time) Set by reg. 24h and 26h Jack insert detection enabled, headphone plugged in Disabled Set by reg. 04h X Jack insert detection enabled, headphone not plugged in X Force Ear Speaker Mode Set by reg. 24h and 26h Set by reg. 16h Set by reg. 04h Set by reg. 16h Set by reg. 24h and 26h X Invalid; do not use this setting Table 21 Jack Insertion / Auto-Switching (2)

w PD Rev 4.3 August 2006 DIGITAL AUDIO (SPDIF) OUTPUT The WM9711L supports the SPDIF standard using pin 47 as its output. Note that pin 47 can also be used as a GPIO pin. The GE5 bit (register 56h, bit 5) selects between GPIO and SPDIF functionality (see “GPIO and Interrupt control” section). Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or sub-frame in the V case). With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF bit in register 2Ah is ‘0’). Once the desired values have been written to this register, the contents should be read back to ensure that the sample rate in particular is supported, then SPDIF validity bit SPCV in register 2Ah should be read to ensure the desired configuration is valid. Only then should the SPDIF enable bit in register 2Ah be set. This ensures that control and status information start up correctly at the beginning of SPDIF transmission. REGISTER ADDRESS BIT LABEL DEFAULT SPDIF validity bit (read-only) 5:4 SPSA SPDIF slot assignment (ADCO = 0) 00: Slots 3, 4 01: Slots 6, 9 10: Slots 7, 8 11: Slots 10, 11 2Ah Extended Audio SEN SPDIF output enable 1 = enabled, 0 = disabled V Validity bit; ‘0’ indicates frame valid, ‘1’ indicates frame not valid DRS Double rate SPDIF support; not supported by WM9705 therefore fixed ‘0’ 13:1 SPSR SPDIF sample rate; WM9705 supports only 48kHz = ‘10’. This value is fixed. L Generation level; programmed as required by user 10:4 CC 0000000 Category code; programmed as required by user PRE Pre-emphasis; ‘0’ indicates not pre- emphasis, ‘1’ indicates 50/15us pre- emphasis COPY Copyright; ‘0’ indicates copyright is not asserted, ‘1’ indicates copyright AUDIB TBD Non-audio; ‘0’ indicates data is PCM, ‘1’ indicates non-PCM format (eg DD or DTS) 3Ah SPDIF Control Register PRO TBD Professional; ‘0’ indicates consumer, ‘1’ indicates professional 5Ch Additional Function Control ADCO Source of SPDIF data 0: SPDIF data comes from SDATAOUT (pin 5), slot selected by SPSA 1: SPDIF data comes from audio ADC Table 22 SPDIF Output Control

w PD Rev 4.3 August 2006 AUDIO MIXERS MIXER OVERVIEW The WM9711L has three separate low-power audio mixers to cover all audio functions required by smartphones, PDAs and handheld computers. The diagram below shows the routing of the analogue audio signals into the mixers. The numbers at the mixer inputs refer to the control register bits that control the volume and muting for that particular signal. PHONE_IN PCBEEP LINE_IN Stereo headphone / headset HPOUTL HPOUTR HPVOL (Reg 04h) MONOOUT (PHONE TX) OUT3VOL (Reg 16h) LOUT2 ROUT2 OUT2VOL (Reg 02h) loud speaker OUT3 ear speaker 0Ch [4:0] 10h [12:8,4:0] 18h [12:8,4:0] RECORD SELECT 0Eh [12:8,4:0] MICR MICL DIFF / STEREO/ MONO (Reg 20h) STEREO DAC AUX DAC (12-BIT) 1Ch / ALC dB 0Eh [7] M U X MONOOUT VREF 18h [15] 10h [15] 14h [15:12] 14h [11:7] 0Ch [15] 12h [15:12] 18h [13] 10h [13] 0Eh [14,13] 1Ah [13:11] 0Ah [15:12] HEAD PHONE/ EAR SPEAKER MIX PHONE MIX 12h [7:4] 0Ah [7:4] M U X 12h [11:8] 18h [14] 10h [14] 0Ah [11:8] 0Ch [14] BACK SPEAKER MIX SRC (Reg 16h) OUT3SRC (Reg 16h) STEREO ADC M U X PHONE MIX HEADPHONE MIX BACK SPKR MIX INV (Reg 02h) 1Ah [14] dB Figure 4 Audio Mixer Overview HEADPHONE MIXER The headphone mixer drives the HPOUTL and HPOUTR outputs. It also drives OUT3, if this pin is connected to an ear speaker (phone receiver). The following signals can be mixed into the headphone path: PHONE (controlled by register 0Ch, see “Audio Inputs”) LINE_IN (controlled by register 10h, see “Audio Inputs”) the output of the Record PGA (see “Audio ADC”, “Record Gain”) the stereo DAC signal (controlled by register 18h, see “Audio DACs”) the MIC signal (controlled by register 0Eh, see “Audio Inputs”) PC_BEEP (controlled by register 0Ah, see “Audio Inputs”) the AUXDAC signal (controlled by register 12h, see “Auxiliary DAC”) In a typical smartphone application, the headphone signal is a mix of PHONE and sidetone (for phone calls) and the stereo DAC signal (for music playback).

w PD Rev 4.3 August 2006 SPEAKER MIXER The speaker mixer drives the LOUT2 and ROUT2 output. The following signals can be mixed into the speaker path: PHONE (controlled by register 0Ch, see “Audio Inputs”) LINE_IN (controlled by register 10h, see “Audio Inputs”) the stereo DAC signal (controlled by register 18h, see “Audio DACs”) PC_BEEP (controlled by register 0Ah, see “Audio Inputs”) the AUXDAC signal (controlled by register 12h, see “Auxiliary DAC”) In a typical smartphone application, the speaker signal is a mix of AUXDAC (for system alerts or ring tone playback), PHONE (for speakerphone function), and PC_BEEP (for externally generated ring tones). MONO MIXER The mono mixer drives the MONOOUT pin. The following signals can be mixed into MONOOUT: LINE_IN (controlled by register 10h, see “Audio Inputs”) the output of the Record PGA (see “Audio ADC”, “Record Gain”) the stereo DAC signal (controlled by register 18h, see “Audio DACs”) the MIC signal (controlled by register 10h, see “Audio Inputs”) PC_BEEP (controlled by register 0Ah, see “Audio Inputs”) the AUXDAC signal (controlled by register 12h, see “Auxiliary DAC”) In a typical smartphone application, the MONOOUT signal is a mix of the amplified microphone signal (possibly with Automatic Gain Control) and (if enabled) an audio playback signal from the stereo DAC or the auxiliary DAC. SIDE TONE CONTROL The side tone path is into the headphone mixer and is either from the MIC or ALC path (with no 20dB boost) REGISTER ADDRESS BIT LABEL DEFAULT 0: selected 1 : not selected (path muted) 14:12 STVOL 010 (0dB) MIC Sidetone volume 000 : +6dB (max.) 001: +3dB … (3dB steps) 111 : -15dB (min.) 11:10 ALCM ALC side tone select 11: mute 10: mono – left 01: mono – right 00: stereo 14h Sidetone Control 9:7 ALCVOL 010 (0dB) ALC Sidetone volume Similar to STVOL Table 23 Side Tone Control

w PD Rev 4.3 August 2006 VARIABLE RATE AUDIO / SAMPLE RATE CONVERSION By using an AC’97 Rev2.2 compliant audio interface, the WM9711L can record and playback at all commonly used audio sample rates, and offer full split-rate support (i.e. the DAC, ADC and AUXDAC sample rates are completely independent of each other – any combination is possible). The default sample rate is 48kHz. If the VRA bit (register 20h) is set and the appropriate block is enabled, then other sample rates can be selected by writing to registers 2Ch, 32h and 2Eh. The AC- Link continues to run at 48k frames per second irrespective of the sample rate selected. However, if the sample rate is less than 48kHz, then some frames do not carry an audio sample. REGISTER ADDRESS BIT LABEL DEFAULT 0 (OFF) Variable Rate Audio 0: OFF (DAC and ADC run at 48kHz) 1: ON (sample rates determined by registers 2Ch, 2Eh and 32h) 2Ch Audio DAC Sample Rate 15:0 DACSR BB80h (48kHz) Audio DAC sample rate 1F40h: 8kHz 2B11h: 11.025kHz 2EE0h: 12kHz 3E80h: 16kHz 5622h: 22.05kHz 5DC0h: 24kHz 7D00h: 32kHz AC44h: 44.1kHz BB80h: 48kHz Any other value defaults to the nearest supported sample rate 32h Audio ADC Sample Rate 15:0 ADCSR BB80h (48kHz) Audio ADC sample rate similar to DACSR 2Eh AUXDAC Sample Rate 15:0 AUXDA CSR BB80h (48kHz) AUXDAC sample rate similar to DACSR Table 24 Audio Sample Rate Control

w PD Rev 4.3 August 2006 BATTERY ALARM PRINCIPLE OF OPERATION The WM9711L has two on-chip comparators that can be used to implement a battery alarm function, or other functions such as a window comparator. Each comparator has one of its inputs tied to any one of three device pins and the other tied to a voltage reference. The voltage reference can be either internally generated (VREF = AVDD/2) or externally connected on CREF (pin 12). The comparator output signals are passed to the GPIO logic block (see “GPIO and Interrupt Control” section), where they can be used to send an interrupt to the CPU via the AC-Link or via the IRQ pin, and / or to wake up the WM9711L from sleep mode. COMP1 (pin 29) corresponds to GPIO bit 15 and COMP2 (pin30) to bit 14. REGISTER ADDRESS BIT LABEL DEFAULT COMP1 Polarity (see also “GPIO and Interrupt Control”) 0: Alarm when COMP1 voltage is above VREF 1: Alarm when COMP1 voltage is below VREF 4Eh CP2 COMP2 Polarity (see also “GPIO and Interrupt Control”) 0: Alarm when COMP2 voltage is above VREF 1: Alarm when COMP2 voltage is below VREF 58h 15:13 COMP2 DEL Low Battery Alarm Delay 000: No delay 001: 0.17s (213 = 8192 AC-Link frames) 010: 0.34s (214 = 16384 AC-Link frames) 011: 0.68s (215 = 32768 AC-Link frames) 100: 1.4s (216 = 65536 AC-Link frames) 101: 2.7s (217 = 131072 AC-Link frames) 110: 5.5s (218 = 262144 AC-Link frames) 111: 10.9s (219 = 524288 AC-Link frames) Table 25 Comparator Control REGISTER ADDRESS BIT LABEL DEFAULT Comparator 1 Reference Voltage VREF = AVDD/2 C1REF WIPER/AUX4 (pin 12) Comparator 1 Signal Source AVDD/2 when C1REF=’1’. Otherwise comparator 1 is powered down COMP1/AUX1 (pin 29) COMP2/AUX2 (pin 30) 13:12 C1SRC BMON/AUX3 (pin 31) Comparator 2 Reference Voltage VREF = AVDD/2 C2REF WIPER/AUX4 (pin 12) Comparator 2 Signal Source AVDD/2 when C2REF=’1’. Otherwise comparator 2 is powered down COMP1/AUX1 (pin 29) COMP2/AUX2 (pin 30) 5Ch Additional Analogue Functions 10:9 C2SRC BMON/AUX3 (pin 31) Table 26 Comparator Reference and Source Control

w PD Rev 4.3 August 2006 COMP2 DELAY FUNCTION COMP2 has an optional delay function for use when the input signal is noisy. When COMP2 triggers and the delay is enabled (i.e. COMP2DEL is non-zero), then GPIO bit 14 does not change state immediately, and no interrupt is generated. Instead, the WM9711L starts a delay timer and checks COMP2 again after the delay time has passed. If COMP2 is still active, then the GPIO bit is set and an interrupt may be generated (depending on the state of the GW14 bit). If COMP2 is no longer active, the GPIO bit is not set, i.e. all register bits are as if COMP2 had never triggered. Note: If COMP2 triggers while the WM9711L is in sleep mode, and the delay is enabled, then the device starts the on-chip crystal oscillator in order to count the time delay. COMP2 TRIGGERS START TIMER COMP2? WAIT time=COMP2DEL SHUT DOWN TIMER Inactive Active SET GI14 END END [FALSE ALARM] COMP2 DEL? non-zero C2W? END 000 Figure 5 COMP2 Delay Flow Chart

w PD Rev 4.3 August 2006 COMP1 COMP2 VREF GPIO2/ IRQ GPIO PINS DEAD BAT LOW BAT GPIO / INTERRUPT LOGIC C VBATT WM9711L IALARM VOLTAGE REGULATOR AVDD, DCVDD, ... Figure 6 Battery Alarm Example Schematic The typical schematic for a dual threshold battery alarm is shown above. This alarm has two thresholds, “dead battery” (COMP1) and “low battery” (COMP2). R1, R2 and R3 set the threshold voltages. Their values can be up to about 1MΩ in order to keep the battery current [IALARM = VBATT / (R1+R2+R3)] to a minimum (higher resistor values may affect the accuracy of the system as leakage currents into the input pins become significant). Dead battery alarm: COMP1 triggers when VBATT < VREF × (R1+R2+R3) / (R2+R3) A dead battery alarm is the highest priority of interrupt in the system. It should immediately save all unsaved data and shut down the system. The GP15, GS15 and GW15 bits must be set to generate this interrupt. Low battery alarm: COMP2 triggers when VBATT < VREF × (R1+R2+R3) / R3 A low battery alarm has a lower priority than a dead battery alarm. Since the threshold voltage is higher than for a dead battery alarm, there is enough power left in the battery to give the user a warning and/or shut down “gracefully”. When VBATT gets close to the low battery threshold, spurious alarms are filtered out by the COMP2 delay function. The purpose of the capacitor C is to remove from the comparator inputs any high frequency noise or glitches that may be present on the battery (for example, noise generated by a charge pump). It forms a low pass filter with R1, R2 and R3. Low pass cutoff fc [Hz] = 1/ (2π C × (R1 || (R2+R3))) Provided that the cutoff frequency is several orders of magnitude lower than the noise frequency fn, this simple circuit can achieve excellent noise rejection. Noise rejection [dB] = 20 log (fn / fc)

w PD Rev 4.3 August 2006 GPIO AND INTERRUPT CONTROL The WM9711L has five GPIO pins that operate as defined in the AC’97 Revision 2.2 specification. Each GPIO pin can be set up as an input or as an output, and has corresponding bits in register 54h and in slot 12. The state of a GPIO output is determined by sending data through slot 12 of outgoing frames (SDATAOUT). Data can be returned from a GPIO input by reading the register bit, or examining slot 12 of incoming frames (SDATAIN). GPIO inputs can be made sticky, and can be programmed to generate and interrupt, transmitted either through the AC-Link or through a dedicated, level-mode interrupt pin (GPIO2/IRQ, pin 45). GPIO pins 2 to 5 are multi-purpose pins that can also be used for other (non-GPIO) purposes, e.g. as a SPDIF output or to signal pen-down. This is controlled by register 56h. Independently of the GPIO pins, the WM9711L also has three virtual GPIOs. These are signals from inside the WM9711L, which are treated as if they were GPIO input signals. From a software perspective, virtual GPIOs are the same as GPIO pins, but they cannot be set up as outputs, and are not tied to an actual pin. This allows for simple, uniform processing of different types of signals that may generate interrupts (e.g. pen down, battery warnings, jack insertion, high-temperature warning, or GPIO signals). Figure 7 GPIO logic

w PD Rev 4.3 August 2006 GPIO BIT SLOT1

2 BIT

PIN NO. enabled only when pin not used as IRQ GPIO Pin GPIO3 GPIO Pin GPIO4 GPIO Pin GPIO5 / SPDIF_OUT enabled only when pin not used as SPDIF_OUT 6-10 N/A Unused GPIO Logic not implemented for these bits Virtual GPIO [Thermal Cutout] Internal thermal cutout signal, indicates when internal temperature reaches approximately 150°C (see “Thermal Sensor”) 12-13 N/A Unused GPIO Logic not implemented for these bits Virtual GPIO [COMP2] Internal COMP2 output (Low Battery Alarm) enabled only when COMP2 is on Virtual GPIO [COMP1] Internal COMP1 output (Dead Battery Alarm) enabled only when COMP1 is on Table 27 GPIO Bits and Pins

w PD Rev 4.3 August 2006 The properties of the GPIOs are controlled through registers 4Ch to 52h, as shown below. REGISTER ADDRESS BIT LABEL DEFAULT n GCn GPIO Pin Configuration 0: Output 1: Input GC11-15 are always ‘1’ Unused bits GC6-GC10 are always ‘0’ GPIO Pin Polarity / Type 0: Active Low 1: Active High [GIn = pin level XNOR GPn) 4Eh n GPn Unused bits GP6-GP10, GP12 and GP13 are always ‘1’ 50h n GSn GPIO Pin Sticky 1: Sticky 0: Not Sticky Unused bits GS6-GS10, GS12 and GS13 are always ‘0’ 52h n GWn GPIO Pin Wake-up 1: Wake Up (generate interrupts from this pin) 0: No wake-up (no interrupts generated) Unused bits GW6-GW10, GW12 and GW13 are always ‘0’ 54h n GIn N/A GPIO Pin Status Read: Returns status of each GPIO pin Write: Sets output pin high or low. (Writing ‘0’ clears sticky bit) Unused bits GI6-GI10, GI12 and GI13 are always ‘0’ Table 28 GPIO Control The following procedure is recommended for handling interrupts: When the controller receives an interrupt, check register 54h. For each GPIO bit in descending order of priority, check if the bit is ‘1’. If yes, execute corresponding interrupt routine, then write ‘0’ to corresponding bit in 54h. If no, continue to next lower priority GPIO. After all GPIOs have been checked, check if interrupt still present or no. If yes, repeat procedure. If no, then jump back to process that ran before the interrupt. If the system CPU cannot execute such an interrupt routine, it may be preferable to switch internal signals (such as PENDOWN) directly onto the GPIO pins. However, in this case the interrupt signals cannot be made sticky, and more GPIO pins are tied up both on the WM9711L and on the CPU. REGISTER ADDRESS BIT LABEL DEFAULT 0: Pin 45 disconnected from GPIO logic set 4Ch, bit 2 to ‘0’ to output IRQ signal 1: Pin 45 connected to GPIO logic (IRQ disabled) 56h GPIO pins function select GE5 GPIO5 / SPDIF output select 0: Pin 48 = SPDIF (disconnected from GPIO logic) set 4Ch, bit 5 to ‘0’ to output SPDIF signal 1: Pin 48 connected to GPIO logic (SPDIF disabled) Table 29 Using GPIO Pins for Non-GPIO Functions

w PD Rev 4.3 August 2006 REGISTER ADDRESS BIT LABEL DEFAULT Inverts the IRQ signal (pin 45) 0: IRQ signal not inverted 1: IRQ signal inverted 58h Additional Functional Control WAKEEN Enables GPIO wake-up 0: Disabled 1: Enabled Table 30 Additional Functionality for GPIO Pins POWER MANAGEMENT The WM9711L includes the standard power down control register defined by the AC’97 specification (register 26h). Additionally, it also allows more specific control over the individual blocks of the device through register 24h. Each particular circuit block is ON when both the relevant bit in register 26h and the relevant bit in register 24h are set to ‘0’. DEFAULT REGISTER ADDRESS BIT LABEL NORMAL PIN 47 ‘HI’ DURING RESET 0 (ON) 1 (OFF) Disables HPOUTL, HPOUTR and OUT3 Buffer PR5 0 (ON) 1 (OFF) Disables internal clock PR4 0 (ON) 1 (OFF) Disables AC-link interface (external clock off) PR3 0 (ON) 1 (OFF) Disables VREF, analogue mixers and outputs PR2 0 (ON) 1 (OFF) Disables analogue mixers, LOUT2, ROUT2 (but not VREF) PR1 0 (ON) 1 (OFF) Disables stereo DAC PR0 0 (ON) 1 (OFF) Disables audio ADCs and input Mux REF Read-only bit, indicates VREF is ready (inverse of PR2) ANL Read-only bit, indicates analogue mixers are ready (inverse of PR3) DAC Read-only bit, indicates audio DACs are ready (inverse of PR1) 26h Powerdown/ Status register ADC Read-only bit, indicates audio ADCs are ready (inverse of PR0) Table 31 Powerdown and Status Register (Conforms to AC’97 Rev 2.2) As can be seen from the table above, most blocks are ‘ON’ by default. However, if pin 47 (GPIO4/ADA/MASK) is held high during reset, the WM9711L starts up with all blocks powered down by default, saving power. This is achieved by connecting a pull-up resistor (e.g. 100kΩ) from pin 47 to DBVDD. Note that the state of pin 47 during reset only affects register 26h.

w PD Rev 4.3 August 2006 Table 32 Extended Power Down Register (Additional to AC’97 Rev 2.2) Note: *When disabling a PGA, always ensure that it is muted first. ADDITIONAL POWER MANAGEMENT: AUXDAC: see “Auxiliary DAC” section. AUXDAC is OFF by default. SLEEP MODE Whenever the PR4 bit (reg. 26h) is set, the AC-Link interface is disabled, and the WM9711L is in sleep mode. There is in fact a very large number of different sleep modes, depending on the other control bits. For example, the low-power standby mode described below is a sleep mode. It is desirable to use sleep modes whenever possible, as this will save power. The following functions do not require a clock and can therefore operate in sleep mode: Analogue-to-analogue audio (DACs and ADCs unused), e.g. phone call mode GPIO and interrupts Battery alarm / analogue comparators The WM9711L can awake from sleep mode as a result of A warm reset on the AC-Link (according to the AC’97 specification) A signal on a GPIO pin (if the pin is configured as an input, with wake-up enabled – see “GPIO and Interrupt Control” section) A virtual GPIO event such as battery alarm, thermal sensor, etc. (see “GPIO and Interrupt Control” section) REGISTER ADDRESS BIT LABEL DEFAULT 0 (ON) Disables Crystal Oscillator PD14 0 (ON) Disables left audio DAC PD13 0 (ON) Disables right audio DAC PD12 0 (ON) Disables left audio ADC PD11 0 (ON) Disables right audio ADC PD10 0 (ON) Disables MICBIAS PD9 0 (ON) Disables left headphone mixer PD8 0 (ON) Disables right headphone mixer PD7 0 (ON) Disables speaker mixer PD6 0 (ON) Disables MONO_OUT buffer (pin 33) and phone mixer PD5 0 (ON) Disables OUT3 buffer (pin 37) PD4 0 (ON) Disables headphone buffers (HPOUTL/R) PD3 0 (ON) Disables speaker outputs (LOUT2, ROUT2) PD2 0 (ON) Disables Line Input PGA (left and right) * PD1 0 (ON) Disables Phone Input PGA * 24h Additional power down control PD0 0 (ON) Disables Mic Input PGA (left and right) * Note: When analogue inputs or outputs are disabled, they are internally connected to VREF through a large resistor (VREF=AVDD/2 except in OFF mode, when VREF itself is disabled). This maintains the potential at that node and helps to eliminate pops when the pins are re-enabled.

w PD Rev 4.3 August 2006 LOW POWER STANDBY MODE If all the bits in registers 26h and 24h are set, then the WM9711L is in low-power standby mode and consumes very little current. A 1MΩ resistor string remains connected across AVDD to generate VREF. This is necessary if the on-chip analogue comparators are used (see “Battery Alarm” section), and helps shorten the delay between wake-up and playback readiness. If VREF is not required, the 1MΩ resistor string can be disabled by setting the SVD bit, reducing current consumption further. REGISTER ADDRESS BIT LABEL DEFAULT 0: VREF enabled using 1MΩ string (low-power standby mode) 1 : VREF disabled, 1MΩ string disconnected (OFF mode) Table 33 Disabling VREF (for lowest possible power consumption) SAVING POWER AT LOW SUPPLY VOLTAGES The analogue supplies to the WM9711L can run from 1.8V to 3.6V. By default, all analogue circuitry on the IC is optimized to run at 3.3V. This set-up is also good for all other supply voltages down to 1.8V. However, at lower voltages, it is possible to save power by reducing the internal bias currents used in the analogue circuitry. This is controlled as shown below. REGISTER ADDRESS BIT LABEL DEFAULT 6:5 V[1:0] Analogue Bias optimization 11 : Lowest bias current, optimized for 1.8V 10 : Low bias current, optimized for 2.5V 01, 00 : Default bias current, optimized for 3.3V Table 34 Analogue Bias Selection

w PD Rev 4.3 August 2006 AC97 DATA AND CONTROL INTERFACE INTERFACE PROTOCOL The WM9711Lhas a single AC’97 interface for both data transfer and control. The AC-Link uses 5 wires: SDATAIN (pin 8) carries data from the WM9711L to the controller SDATAOUT (pin 5) carries data from the controller to the WM9711L BITCLK (pin 6) is a clock, normally generated by the WM9711L crystal oscillator and supplied to the controller. However, BITCLK can also be passed to the WM9711L from an off-chip generator. SYNC is a synchronization signal generated by the controller and passed to the WM9711L RESETB resets the WM9711L to its default state CONTROLLER e.g. CPU WM9711L RESETB SDATAIN SDATAOUT BITCLK SYNC 24.576MHz XTAL AC-LINK ANALOGUE INPUTS / OUTPUTS Figure 8 AC-Link Interface (typical case with BITCLK generated by the AC97 codec) The SDATAIN and SDATAOUT signals each carry 13 time-division multiplexed dat a streams (slots 0 to 12). A complete sequence of slots 0 to 12 is referred to as an AC-Link frame, and contains a total of 256 bits. The frame rate is 48kHz. This makes it possible to simultaneously transmit and receive multiple data streams (e.g. audio in, audio out, AUXDAC, GPIO, control) at sample rates up to 48kHz. Detailed information can be found in the AC’97 (Revision 2.2) specification, which can be obtained at www.intel.com/labs/media/audio/ Note: SDATAOUT and SYNC must be held low for when RESETB is applied. These signals must be held low for the entire duration of the RESETB pulse and especially during the low-to-high transition of RESETB. If either is set high during reset the AC'97 device may enter test modes. Information relating to this operation is available in the AC'97 specification or in Wolfson applications note WAN- 0104 available at www.wolfsonmirco.com.

w PD Rev 4.3 August 2006 REGISTER MAP Note: Highlighted bits differ from the AC’97 specification (newly added for non-AC’97 function, or same bit used in a different way, or for another function) Reg Name Default 00h Reset SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 6174h 02h LOUT2/ROUT2 Volume MU ZC INV 8000h 04h Headphone Volume MU ZC 8000h 06h MONOOUT Volume MU ZC 8000h 08h DAC Tone Control BB BC DAT TC 0F0Fh 0Ah PCBEEP Input B2H B2S B2P AAA0h 0Ch PHONE Volume P2H P2S C008h 0Eh MIC Volume M12P M22P 20dB 6808h 10h LINEIN Volume L2H L2S L2P E808h 12h AUXDAC Volume / Routing A2H A2S A2P AXE AAA0h 14h Sidetone Volume STM AD00h 16h OUT3 Volume MU SRC ZC 8000h 18h DAC Volume D2H D2S D2P E808h 1Ah Record Select BOOST R2P BST 3000h 1Ch Record Gain RMU GRL ZC GRR 8000h 20h General Purpose 3DE LB 0000h 22h DAC 3D Control 3DLC 3DUC 0000h 24h Powerdown PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 0000h 26h Powerdown Ctrl/Stat EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 REF ANL DAC ADC 000Fh FFF0h 28h Extended Audio ID ID1 ID0 REV1 REV0 AMAP LDAC SDAC CDAC VRM SPDIF DRA VRA 0405h 2Ah Ext’d Audio stst/ctrl SPCV SEN VRA 0410h 2Ch Audio DACs Sample Rate BB80h 2Eh AUXDAC Sample Rate BB80h 32h Audio ADCs Sample Rate BB80h 3Ah SPDIF control V DRS L PRE COPY AUD IB PRO 2000h 4Ch GPIO Pin Configuration GC5 GC4 GC3 GC2 GC1 F83Eh 4Eh GPIO Pin Polarity / Type C1P C2P TP GP5 GP4 GP3 GP2 GP1 FFFFh 50h GPIO Pin Sticky C1S C2S TS GS5 GS4 GS3 GS2 GS1 0000h 52h GPIO Pin Wake-Up C1W C2W TW GW5 GW4 GW3 GW2 GW1 0000h 54h GPIO Pin Status C1I C2I TI GI5 GI4 GI3 GI2 GI1 GPIO pins 56h GPIO Pin Assignment COM1 COM2 TCO GE5 GE2 F83Eh 58h GPIO pin sharing / Additional Functions JIEN JIF SVD WAKE EN IRQ INV 0008h 5Ah Vendor Reserved 5Ch Add. Function Control AMUTE C1 REF C2 REF DS AM EN AD CO HPF ENT 0000h 5Eh Vendor Reserved 60h ALC Control B032h 62h ALC / Noise Gate Control ALC ZC NG AT NGG 3E00h 64h AUXDAC input control XSLE 0000h 66h- 7Ah Vendor Reserved N/A 7Ch Vendor ID1 574Dh 7Eh Vendor ID2 4C12h RESERVED FOR TEST RESERVED. DO NOT WRITE TO THESE REGISTERS OUT3 Volume LOUT2 Volume ROUT2 Volume STVOL LINEINLVOL LINEINRVOL A2HVOL A2SVOL COMP2DEL RESERVED FOR TEST B2SVOL SPSR CC (Category Code) ADCSR (Audio ADCs Sample Rate) (Extended) RECVOLL ASCII character “L” Number “12” NGTH (threshold) AUXDAC VAL ASCII character “W” ASCII character “M” ALCSEL MAXGAIN ZC TIMEOUT AUXDACSLT ALCL (target level) HLD (hold time) DCY (decay time) ATK (attack time) C2SRC Die Revision 3DDEPTH DACSR (Audio DACs Sample Rate) AUXDACSR (Auxiliary DAC Sample Rate) SPSA V (BIAS) ASS C2SRC HPOUTR Volume HPOUTL Volume RECSL RECSR Left DAC Volume Right DAC Volume R2P ALCM LMICVOL (Left Only) B2HVOL ALCVOL Default for reg. 26h - pin 47 "high" during reset (recommended for lowest power) OUT3SRC A2PVOL Default for reg. 26h - pin 47 "low" (Extended) RECVOLR MONOOUT Volume BASS TRBL MICVOL (Mono /Right) MS B2PVOL PHONEIN Volume Table 35 WM9711L Register Map

w PD Rev 4.3 August 2006 REGISTER BITS BY ADDRESS Register 00h is a read-only register. Writing any value to this register resets all registers to their default, but does not change the contents of reg. 00h. Reading the register reveals information about the codec to the driver, as required by the AC’97 Specification, Revision 2.2 REG ADDR BIT LABEL DEFAULT 14:10 SE [4:0] 11000 Indicates a codec from Wolfson Microelectronics 9:6 ID9:6 0101 Indicates 18 bits resolution for ADCs and DACs ID5 Indicates that the WM9711L supports bass boost ID4 Indicates that the WM9711L has a headphone output ID3 Indicates that the WM9711L does not support simulated stereo ID2 Indicates that the WM9711L supports bass and treble control ID1 Indicates that the WM9711L does not support modem functions 00h ID0 Indicates that the WM9711L does not have a dedicated microphone ADC Intel’s AC’97 Component Specification, Revision 2.2, page 50 Register 02h controls the output pins LOUT2 and ROUT2. REG ADDR BIT LABEL DEFAULT 1 (mute) Mutes LOUT2 and ROUT2. 13:8 LOUT2 VOL 000000 (0dB) LOUT2 volume ZC 0 (OFF) Enables zero-cross detector INV 0 (not inverted) Inverts LOUT2 (for BTL speaker operation) 02h 5:0 ROUT2 VOL 000000 (0dB) ROUT2 volume Analogue Audio Outputs Register 04h controls the headphone output pins, HPOUTL and HPOUTR. REG ADDR BIT LABEL DEFAULT 1 (mute) Mutes HPOUTL and HPOUTR. 13:8 HPOUTL VOL 000000 (0dB) HPOUTL volume ZC 0 (OFF) Enables zero-cross detector 04h 5:0 HPOUTR VOL 000000 (0dB) HPOUTR volume Analogue Audio Outputs Register 06h controls the analogue output pin MONOOUT. REG ADDR BIT LABEL DEFAULT 1 (mute) Mutes MONOOUT. ZC 0 (OFF) Enables zero-cross detector 06h 5:0 MONOOUT VOL 000000 (0dB) MONOOUT volume Analogue Audio Outputs

w PD Rev 4.3 August 2006 Register 08h controls the bass and treble response of the left and right audio DAC (but not AUXDAC). REG ADDR BIT LABEL DEFAULT 0 (linear) Selects linear bass control or adaptive bass boost BC 0 (low) Selects bass cut-off frequency 11:8 BASS 1111 (OFF) Controls bass intensity DAT 0 (OFF) Enables 6dB pre-DAC attenuation TC 0 (high) Selects treble cut-off frequency 08h 3:0 TRBL 1111 (OFF) Controls treble intensity Audio DACs, Tone Control / Bass Boost Register 0Ah controls the analogue input pin PCBEEP. REG ADDR BIT LABEL DEFAULT 1 (mute) Mutes PCBEEP to headphone mixer path 14:12 B2HVOL 010 (0dB) Controls gain of PCBEEP to headphone mixer path B2S 1 (mute) Mutes PCBEEP to speaker mixer path 10:8 B2SVOL 010 (0dB) Controls gain of PCBEEP to speaker mixer path B2P 1 (mute) Mutes PCBEEP to phone mixer path 0Ah 6:4 B2PVOL 010 (0dB) Controls gain of PCBEEP to phone mixer path Analogue Inputs, PCBEEP Input Register 0Ch controls the analogue input pin PHONE. REG ADDR BIT LABEL DEFAULT 1 (mute) Mutes PHONE to headphone mixer path P2S 1 (mute) Mutes PHONE to speaker mixer path 0Ch 4:0 PHONEVOL 01000 (0dB) Controls PHONE input gain to all mixers (but not to ADC) Analogue Inputs, PHONE Input Register 0Eh controls the analogue input pins MIC1 and MIC2. REG ADDR BIT LABEL DEFAULT 1 (mute) Mutes MIC1 to phone mixer path M22P 1 (mute) Mutes MIC2 to phone mixer path 12:8 LMICVOL 01000 (0dB) Controls volume of MIC1 (left), in stereo mode only 20dB 0 (OFF) Enables 20dB gain boost 6:5 MS 00 (MIC1 only) Selects microphone mode. 00=MIC1 only, 01=differential, 10=MIC2 only, 11=stereo 0Eh 4:0 MICVOL 01000 (0dB) Controls mic volume (except MIC1 in stereo mode) Analogue Inputs, Microphone Input Register 10h controls the analogue input pins LINEINL and LINEINR. REG ADDR BIT LABEL DEFAULT 1 (mute) Mutes LINEIN to headphone mixer path L2S 1 (mute) Mutes LINEIN to speaker mixer path L2P 1 (mute) Mutes LINEIN to phone mixer path 12:8 LINEINLVOL 01000 (0dB) Controls LINEINL input gain to all mixers (but not to ADC) 10h 4:0 LINEINRVOL 01000 (0dB) Controls LINEINR input gain to all mixers (but not to ADC) Analogue Inputs, Line Input

w PD Rev 4.3 August 2006 Register 12h controls the output signal of the auxiliary DAC. REG ADDR BIT LABEL DEFAULT 1 (mute) Mutes AUXDAC to headphone mixer path 14:12 A2HVOL 010 (0dB) Controls gain of AUXDAC to headphone mixer path A2S 1 (mute) Mutes AUXDAC to speaker mixer path 10:8 A2SVOL 010 (0dB) Controls gain of AUXDAC to speaker mixer path A2P 1 (mute) Mutes AUXDAC to phone mixer path 6:4 A2PVOL 010 (0dB) Controls gain of AUXDAC to phone mixer path 12h AXE 0 (0FF) Enables AUXDAC Auxiliary DAC Register 14h controls the side tone paths. REG ADDR BIT LABEL DEFAULT 1 (mute) Mutes microphone to headphone mixer path 14:12 STVOL 010 (0dB) Controls gain of microphone to headphone mixer path 11:10 ALCM 11 (mute both) Selects ALC to headphone mixer path. 00=stereo, 01=right only, 10=left only, 11=mute both left and right 14h 9:7 ALCVOL 010 (0dB) Controls gain of ALC to headphone mixer path Audio Mixers, Side Tone Control Register 16h controls the analogue output pin OUT3, and also contains one control bit that affects LOUT2 and ROUT2. REG ADDR BIT LABEL DEFAULT 1 (mute) Mutes OUT3. 10:9 OUT3SRC 00 (-HPOUTL) Selects source of OUT3 signal. 00=-HPOUTL, 01=VREF, 10=HPOUTL+HPOUTR, 11=-MONOOUT SRC 0 (spkr mix) Selects source of LOUT2 and ROUT2 signals. 0=from speaker mixer, 1=from headphone mixer ZC 0 (disabled) Zero-cross enable 16h 5:0 OUT3VOL 000000 (0dB) OUT3 volume Analogue Audio Outputs Register 18h controls the audio DACs (but not AUXDAC). REG ADDR BIT LABEL DEFAULT 1 (mute) Mutes DAC to headphone mixer path D2S 1 (mute) Mutes DAC to speaker mixer path D2P 1 (mute) Mutes DAC to phone mixer path 12:8 LDACVOL 01000 (0dB) Controls left DAC input gain to all mixers 18h 4:0 RDACVOL 01000 (0dB) Controls right DAC input gain to all mixers Audio DACs Register 1Ah controls the record selector and the ADC to phone mixer path. REG ADDR BIT LABEL DEFAULT 0 (OFF) Enables 20dB gain boost for recording 13:12 R2P 11 (mute) Controls ADC to phone mixer path. 00=stereo, 01=left ADC only, 10=right ADC only, 11=mute left and right R2PBST 0 (OFF) Enables 20dB gain boost for ADC to phone mixer path 10:8 RECSL 000 (mic) Selects left ADC signal source 1Ah 2:0 RECSR 000 (mic) Selects right ADC signal source Audio ADC, Record Selector

w PD Rev 4.3 August 2006 Register 1Ch controls the recording gain. REG ADDR BIT LABEL DEFAULT 1 (mute) Mutes audio ADC input GRL 0 (standard) 13:8 RECVOLL 000000 (0dB) Controls left ADC recording volume ZC 0 (OFF) Enables zero-cross detector GRR 0 (standard) 1Ch 5:0 RECVOLR 000000 (0dB) Controls right ADC recording volume Audio ADC, Record Gain Register 20h is a “general purpose” register as defined by the AC’97 specification. Only two bits are implemented in the WM9711L. REG ADDR BIT LABEL DEFAULT 0 (OFF) Enables 3D enhancement Audio DACs, 3D Stereo Enhancement 20h LB 0 (OFF) Enables loopback (i.e. feed ADC output data directly into DAC) Intel’s AC’97 Component Specification, Revision 2.2, page 55 Register 22h controls 3D stereo enhancement for the audio DACs. REG ADDR BIT LABEL DEFAULT 0 (low) Selects lower cut-off frequency 3DUC 0 (high) Selects upper cut-off frequency 22h 3:0 3DDEPTH 0000 (0%) Controls depth of 3D effect Audio DACs, 3D Stereo Enhancement Register 24h is for power management additional to the AC’97 specification. Note that the actual state of each circuit block depends on both register 24h AND register 26h. REG ADDR BIT LABEL DEFAULT 0 * Disables Crystal Oscillator PD14 0 * Disables left audio DAC PD13 0 * Disables right audio DAC PD12 0 * Disables left audio ADC PD11 0 * Disables right audio ADC PD10 0 * Disables MICBIAS PD9 0 * Disables left headphone mixer PD8 0 * Disables right headphone mixer PD7 0 * Disables speaker mixer PD6 0 * Disables MONO_OUT buffer (pin 33) and phone mixer PD5 0 * Disables OUT3 buffer (pin 37) PD4 0 * Disables headphone buffers (HPOUTL/R) PD3 0 * Disables speaker outputs (LOUT2, ROUT2) PD2 0 * Disables Line Input PGA (left and right) PD1 0 * Disables Phone Input PGA 24h PD0 0 * Disables Mic Input PGA (left and right) Power Management * “0” corresponds to “ON”, if and only if the corresponding bit in register 26h is also 0.

w PD Rev 4.3 August 2006 Register 26h is for power management according to the AC’97 specification. Note that the actual state of many circuit blocks depends on both register 24h AND register 26h. REG ADDR BIT LABEL DEFAULT Disables HPOUTL, HPOUTR and OUT3 Buffer PR5 Disables Internal Clock PR4 Disables AC-link interface (external clock off) PR3 Disables VREF, analogue mixers and outputs PR2 Disables analogue mixers, LOUT2, ROUT2 (but not VREF) PR1 Disables Stereo DAC and AUXDAC PR0 see note Disables audio ADCs and input Mux REF inverse of PR2 Read-only bit, Indicates VREF is ready ANL inverse of PR3 Read-only bit, indicates analogue mixers are ready DAC inverse of PR1 Read-only bit, indicates audio DACs are ready 26h ADC inverse of PR0 Read-only bit, indicates audio ADCs are ready Power Management Note: PR6 to PR0 default to 1 if pin 47 is held high during reset, otherwise they default to 0. Register 28h is a read-only register that indicates to the driver which advanced AC’97 features the WM9711L supports. REG ADDR BIT LABEL DEFAULT 15:14 ID Indicates that the WM9711L is configured as the primary codec in the system. 11:10 REV Indicates that the WM9711L conforms to AC’97 Rev2.2 AMAP Indicates that the WM9711L does not support slot mapping LDAC Indicates that the WM9711L does not have an LFE DAC SDAC Indicates that the WM9711L does not have Surround DACs CDAC Indicates that the WM9711L does not have a Centre DAC VRM Indicates that the WM9711L does not have a dedicated, variable rate microphone ADC SPDIF Indicates that the WM9711L supports SPDIF output DRA Indicates that the WM9711L does not support double rate audio 28h VRA Indicates that the WM9711L supports variable rate audio Intel’s AC’97 Component Specification, Revision 2.2, page 59 Register 2Ah controls the SPDIF output and variable rate audio. REG ADDR BIT LABEL DEFAULT 1 (valid) SPDIF validity bit (read-only) 5:4 SPSA 01 (slots 6, 9) Controls SPDIF slot assignment. 00=slots 3 and 4, SEN 0 (OFF) Enables SPDIF output enable 2Ah VRA 0 (OFF) Enables variable rate audio Digital Audio (SPDIF) Output Registers 2Ch, 2Eh 32h and control the sample rates for the stereo DAC, auxiliary DAC and audio ADC, respectively. REG ADDR BIT LABEL DEFAULT Controls stereo DAC sample rate 2Eh all AUXDACSR BB80h Controls auxiliary DAC sample rate 32h all ADCSR BB80h Controls audio ADC sample rate Variable Rate Audio / Sample Rate Conversion Note: The VRA bit in register 2Ah must be set first to obtain sample rates other than 48kHz

w PD Rev 4.3 August 2006 Register 3Ah controls the SPDIF output. REG ADDR BIT LABEL DEFAULT V Validity bit; ‘0’ indicates frame valid, ‘1’ indicates frame not valid DRS Indicates that the WM9711L does not support double rate SPDIF output (read-only) 13:12 SPSR Indicates that the WM9711L only supports 48kHz sampling on the SPDIF output (read-only) L Generation level; programmed as required by user 10:4 CC 0000000 Category code; programmed as required by user PRE Pre-emphasis; ‘0’ indicates no pre-emphasis, ‘1’ indicates 50/15us pre-emphasis COPY Copyright; ‘0’ indicates copyright is not asserted, ‘1’ indicates copyright AUDIB Non-audio; ‘0’ indicates data is PCM, ‘1’ indicates non- PCM format (e.g. DD or DTS) 3Ah PRO Professional; ‘0’ indicates consumer, ‘1’ indicates professional Digital Audio (SPDIF) Output Register 4Ch to 54h control the GPIO pins and virtual GPIO signals. REG ADDR BIT LABEL DEFAULT all 1 (all inputs) except unused bits Controls GPIO configuration as inputs or as outputs (note: virtual GPIOs can only be inputs) 4Eh all 1 Controls GPIO polarity (actual polarity depends on register 4Ch AND register 4Eh) 50h all 0 (not sticky) Makes GPIO signals sticky 52h all 0 (OFF) Enables wake-up for each GPIO signal 54h = status of GPIO inputs GPIO pin status (read from inputs, write ‘0’ to clear sticky bits) Controls Comparator 1 signal (virtual GPIO) Controls Comparator 2 signal (virtual GPIO) 13-12 Unused Controls Thermal sensor signal (virtual GPIO) 10-6 Unused Controls GPIO5 (pin 48) Controls GPIO4 (pin 47) Controls GPIO3 (pin 46) Controls GPIO2 (pin 45) please refer to the register map Controls GPIO1 (pin 44) GPIO and Interrupt Control Register 56h controls the use of GPIO pins for non-GPIO functions. REG ADDR BIT LABEL DEFAULT 1 (GPIO) Selects between GPIO5 and SPDIF_OUT function for pin 48 56h GE2 1 (GPIO) Selects between GPIO2 and IRQ function for pin 45 GPIO and Interrupt Control

w PD Rev 4.3 August 2006 Register 58h controls several additional functions. REG ADDR BIT LABEL DEFAULT 15:13 COMP2DEL 000 (no delay) Selects Comparator 2 delay Battery Alarm JIEN Enables Jack Insert Detection FRC Forces Jack Insert Detection Analogue Audio Outputs, Jack Insertion and Auto-Switching SVD 0 (enabled) Disables VREF for lowest possible power consumption Power Management 3:2 DIE REV Indicates device revision. 10=Rev.C N/A WAKEEN 0 (no wake-up) Enables GPIO wake-up 58h IRQ INV 0 (not inverted) Inverts the IRQ signal (pin 45) GPIO and Interrupt Control Register 5Ch controls several additional functions. REG ADDR BIT LABEL DEFAULT Read-only bit to indicate DAC auto-muting Audio DACs, Stereo DACs C1REF 0 (AVDD/2) Selects Comparator 1 Reference Voltage 13:12 C1SRC 00 (OFF) Selects Comparator 1 Signal Source C2REF 0 (AVDD/2) Selects Comparator 1 Reference Voltage 10:9 C2SRC 00 (OFF) Selects Comparator 1 Signal Source Battery Alarm DS Selects differential microphone input pins. 0=MIC1 and MIC2, 1=LINEL and LINER Analogue Inputs, Microphone Input AMEN 0 (OFF) Enables DAC Auto-Mute 6:5 VBIAS Selects analogue bias for lowest power, depending on AVDD supply. 0X=3.3V, 10=2.5V, 11=1.8V Power Management ADCO Selects source of SPDIF data. 0=from SDATAOUT, 1= from audio ADC Digital Audio (SPDIF) Output HPF Disables ADC high-pass filter Audio ADC ENT Enables thermal sensor Analogue Audio Outputs, Thermal Sensor 5Ch 1:0 ASS Selects time slots for stereo ADC data. 00=slots 3 Audio ADC, ADC Slot Mapping Registers 60h and 62h control the ALC and Noise Gate functions. REG ADDR BIT LABEL DEFAULT 15:12 ALCL 1011 (-12dB) Controls ALC threshold 11:8 HLD 0000 (0 ms) Controls ALC hold time 7:4 DCY 0011 (192 ms) Controls ALC decay time 60h 3:0 ATK 0010 (24 ms) Controls ALC attack time 15:14 ALCSEL 00 (OFF) Controls which channel ALC operates on. 00=none, 01=right only, 10=left only, 11=both 13:11 MAXGAIN 111 (+30dB) Controls upper gain limit for ALC 10:9 ZC TIMEOUT 11 (slowest) Controls time-out for zero-cross detection ALCZC 0 (OFF) Enables zero-cross detection for ALC NGAT 0 (OFF) Enables noise gate function NGG 0 (hold gain) Selects noise gate type. 0=hold gain, 1=mute 62h 4:0 NGTH 00000 (-76.5dB) Controls noise gate threshold Audio ADC, Automatic Level Control

w PD Rev 4.3 August 2006 Register 64h controls the input signal of the auxiliary DAC. REG ADDR BIT LABEL DEFAULT Selects input for AUXDAC. 0=from AUXDACVAL (for DC signals), 1=from AC-Link slot (for AC signals) 14:12 AUXDACSLT 000 (Slot 5) Selects input slot for AUXDAC (with XSLE=1) 64h 11:0 AUXDACVAL 000000000 AUXDAC Digital Input for AUXDAC (with XSLE=0). 000h= minimum, FFFh=full-scale Auxiliary DAC Register 7Ch and 7Eh are read-only registers that indicate the identity of the device to the driver. REG ADDR BIT LABEL DEFAULT 15:8 F7:0 57h ASCII character “W” for Wolfson 7Ch 7:0 S7:0 4Dh ASCII character “M” 15:8 T7:0 4Ch ASCII character “L” 7Eh 7:0 REV7:0 12h Number 12 Intel’s AC’97 Component Specification, Revision 2.2, page 50

w PD Rev 4.3 August 2006 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 15 External Components Diagram

w PD Rev 4.3 August 2006 RECOMMENDED EXTERNAL COMPONENT VALUES COMPONENT REFERENCE SUGGESTED VALUE De-coupling for DBVDD,DCVDD,TPVDD,AVDD,SPKVDD,HPVDD C7 - C8 10uF Reservoir capacitor for DVDD, AVDD. Should the supplies use separate sources then additional capacitors will be required of each additional source. 100nF De-coupling for CAP2. C10 10uF Reservoir capacitor for CAP2 C11 100nF De-coupling for VREF C12 10uF Reservoir capacitor for VREF C13 100nF De-coupling for MICBIAS - Not required if MICBIAS output is not used C14 10uF Reservoir capacitor for MICBIAS - Not required if MICBIAS output is not used C27 and C28 22pF Required when used with a parallel resonant crystal. C15 - C20 1uF AC coupling capacitors C21 - C23 2.2uF Output AC coupling capacitors to remove VREF DC level from outputs C24 - C26 220µF Output AC coupling capacitors to remove VREF DC level from outputs. 100kΩ Pull-up resistor, ensures that all circuit blocks are OFF by default 100kΩ Pull down resistor, ensures that all circuit blocks are ON by default XT 24.576MHz AC'97 master clock frequency. A bias resistor is not required but if connected will not affect operation if the value is large (above 1MΩ) Table 36 External Components Descriptions Note: 1. For Capacitors C7, C8, C10, C12 and C14 it is recommended that very low ESR components are used. LINE OUTPUT The headphone outputs, HPOUTL and HPOUTR, can be used as stereo line outputs. The speaker outputs, LOUT2 and ROUT2, can also be used as line outputs, if ROUT2 is not inverted for BTL operation (INV = 0). Recommended external components are shown below. HPGND HPGND LINE-OUT SOCKET (LEFT) 1uF

100 Ohm

(RIGHT) 1uF Figure 16 Recommended Circuit for Line Output The DC blocking capacitors and the load resistance together determine the lower cut-off frequency, fc. Assuming a 10 kΩ load and C1, C2 = 10µF: fc = 1 / 2π (RL+R1) C1 = 1 / (2π x 10.1kΩ x 1µF) = 16 Hz Increasing the capacitance lowers fc, improving the bass response. Smaller values of C1 and C2 will diminish the bass response. The function of R1 and R2 is to protect the line outputs from damage when used improperly.

w PD Rev 4.3 August 2006 PACKAGE DRAWING e DM029.E FL: 48 PIN QFN PLASTIC PACKAGE 7 X 7 X 0.9 mm BODY, 0.50 mm LEAD PITCH INDEX AREA (D/2 X E/2) TOP VIEW C aaa 2 X SEE DETAIL 2 E2/2 b L D2/2 C aaa 2 X D E e Datum SEE DETAIL 1 C 0.08 C ccc A C (A3) SEATING PLANE DETAIL 3 DETAIL 3 DETAIL 2 Terminal tip R e/2 DETAIL 1 (A3) G T H W b Exposed lead Half etch tie bar Symbols Dimensions (mm) MIN NOM MAX NOTE A b D E e L 0.80 0.90 1.00 0.30 0.25 0.18

7.00 BSC

5.25 5.15 5.00

0.5 BSC

5.15 5.25 5.00 0.30 0.4 0.50 0.02 0.05

0.20 REF

G H 0.213 0.1 NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP. 2. ALL DIMENSIONS ARE IN MILLIMETRES 3. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-002. 4. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 5. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING. JEDEC, MO-220, VARIATION VKKD-2 Tolerances of Form and Position T W aaa bbb ccc 0.1 0.2 0.15 0.10 0.10 REF EXPOSED GROUND PADDLE R = 0.3MM EXPOSED GROUND PADDLE BOTTOM VIEW SIDE VIEW

w PD Rev 4.3 August 2006 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc

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