WM8738

WM8738_06 WOLFSON | Alldatasheet

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w WM8738

24 Bit Stereo ADC

WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ Production Data, August 2006, Rev 4.4 Copyright © 2006 Wolfson Microelectronics plc

DESCRIPTION

The WM8738 is a high performance stereo audio ADC designed for consumer applications. Stereo line-level audio inputs are provided, along with a control input pin to allow operation of the audio interface in either one of two industry standard modes. The device also has a selectable digital high pass filter to remove residual DC offsets. Stereo 24-bit multi-bit sigma delta ADCs are provided, along with oversampling digital interpolation filters. 24-bit digital audio output word lengths and sampling rates from 32kHz to 96kHz are supported. The device is available in a small 14-lead SOIC package.

FEATURES

90 dB SNR (‘A’ weighted @ 48kHz) 3.0 – 5.5V Analogue Supply Operation 3.0 – 3.6V Digital Supply Operation ADC Sampling Frequency: 32kHz – 96kHz Selectable ADC High Pass Filter Selectable Audio Data Interface Modes I2S or Left Justified 14-lead SOIC Package

APPLICATIONS

General Purpose Audio Conversion BLOCK DIAGRAM

w PD Rev 4.4 August 2006 TABLE OF CONTENTS

w PD Rev 4.4 August 2006 PIN CONFIGURATION WM8738 MCLK LIN AVDD AGND LRCLK NOHP SDATO DGND CAP FMT BCLK DVDD RIN VREF

ORDERING INFORMATION

-25 to +85oC 14-lead SOIC (Pb-free) MSL2 260°C WM8738GED/RV -25 to +85oC 14-lead SOIC (Pb-free, tape and reel) MSL2 260°C Note: Reel quantity = 3,000

w PD Rev 4.4 August 2006 PIN DESCRIPTION PIN NAME TYPE ADC audio interface data clock (5V tolerant) FMT Digital input (with pull down) Audio interface format selection (5V tolerant) ‘0’ = I2S ‘1’ = Left Justified CAP Analog Reference de-coupling pin VREF Analogue output Buffered reference decoupling pin RIN Analogue Input Right channel ADC input LIN Analogue Input Left channel ADC input AVDD Supply Analogue positive supply AGND Supply Analogue ground supply and chip substrate NOHP Digital input (with pull down) Digital highpass filter bypass; (5V tolerant) ‘0’ = Enabled ‘1’ = Bypassed LRCLK Digital Input Data left/right word clock (5V tolerant) MCLK Digital Input Master clock input (5V tolerant) DGND Supply Digital supply ground Notes 1. Digital input pins have Schmitt trigger input buffers and are 5V tolerant.

w PD Rev 4.4 August 2006 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. CONDITION MIN MAX Digital supply voltage -0.3V +4.2V Analogue supply voltage -0.3V +7.0V Voltage range digital inputs DGND -0.3V +7.0V Voltage range analogue inputs AGND -0.3V AVDD +0.3V Master Clock Frequency 37MHz Operating temperature range, TA -25°C +85°C Storage temperature prior to soldering 30°C max / 85% RH max Storage temperature after soldering -65°C +150°C Notes Analogue and digital grounds must always be within 0.3V of each other. The digital supply voltage must always be less than or equal to the analogue supply voltage. RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital supply range DVDD 3.0 3.6 V Analogue supply range AVDD 3.0 5.5 V Ground DGND,AGND V Analogue supply current AVDD = 5.0V, (DVDD at 3.3V) mA Analogue supply current AVDD = 3.3V, (DVDD at 3.3V) mA Supply Current Low Power Mode AVDD = 5.0V (DVDD at 3.3V) 180 µA Supply Current Low Power Mode AVDD = 3.3V (DVDD at 3.3V) 110 µA Digital supply current DVDD = 3.3V AVDD = 5.0V or 3.3V mA

w PD Rev 4.4 August 2006

ELECTRICAL CHARACTERISTICS

AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Logic Levels (TTL Levels) Input LOW level VIL 0.8 V Input HIGH level VIH 2.0 V Output LOW VOL IOL = 1mA 0.1 x DVDD V Output HIGH VOH IOH = 1mA 0.9 x DVDD V Pull down resistance (FMT, NOHP) RPD 100 kΩ Analogue Reference Levels Reference voltage VCAP AVDD/2 – 50mV AVDD/2 AVDD/2 + 50mV V Buffered reference voltage VREF VCAP V Potential divider output impedance RCAP kΩ Input to ADC Input Signal Level (0dB) VRIN / VLIN 1.0 Vrms SNR (Note 1) A-weighted, 0dB gain @ fs = 48KHz dB SNR (Note 1) A-weighted, 0dB gain @ fs = 96KHz dB SNR (Note 1) A-weighted, 0dB gain @ fs = 48KHz, AVDD = 3.3V dB Dynamic Range (Note 2) DNR A-weighted, -60dB full scale input dB Total Harmonic Distortion (THD) (Note 3) -1dB input, 0dB gain -87 dB ADC channel separation (Note 1KHz input dB 1kHz 100mVp-p dB Power Supply Rejection Ratio PSRR 20Hz to 20kHz 100mVp-p dB Input Resistance kΩ Input Capacitance pF Notes Ratio of output level with 1kHz full scale input, to the output level with the input open circuited, measured ‘A’ weighted over a 20Hz to 20kHz bandwidth using an Audio analyser. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. VREF and CAP de-coupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance). This data is measured, using an active filter on the device inputs.

w PD Rev 4.4 August 2006 TERMINOLOGY Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No ‘Auto-zero’ or Automute function is employed in achieving these results). Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD (dB) - THD is a ratio, of the r.m.s. values, of Distortion/Signal. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.

w PD Rev 4.4 August 2006 DEVICE DESCRIPTION INTRODUCTION The WM8738 is an ADC designed for audio recording. It’s features, performance and low power consumption make it ideal for recordable CD or DVD players, karaoke, MP3 players and mini-disc players. The on-board stereo analogue to digital converter (ADC) is of a high quality using a multi-bit high- order oversampling architecture delivering optimum performance with low power consumption. The ADC includes a selectable digital high pass filter to remove unwanted DC components from the audio signal. The device supports system clock inputs of 256, 384, 512fs or 768fs (fs is the sampling rate) The output from the ADC is available on the digital audio interface in either I2S or left justified audio data formats. The line inputs are biased internally through the operational amplifier to VCAP. ADC The WM8738 uses a multi-bit over sampled sigma-delta ADC. A single channel of the ADC is illustrated in Figure 3. LIN/RIN ANALOG INTEGRATOR MULTI BITS TO ADC DIGITAL FILTERS Figure 3 Multi-Bit Oversampling Sigma Delta ADC Schematic The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input is 1.0V rms at AVDD = 5.0 volts. Any voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with AVDD. The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. ADC DIGITAL FILTER The ADC digital filters contain a digital high pass filter, selectable via pin NOHP. NOHP = 0 Digital high pass filter enabled NOHP = 1 Digital high pass filter bypassed The high-pass filter response detailed in Digital Filter Characteristics. The operation of the high pass filter removes residual DC offsets that are present on the audio signal.

w PD Rev 4.4 August 2006 AUDIO DATA SAMPLING RATES In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s Master Clock. The external master system clock can be applied directly through the MCLK input pin. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the ADC. The master clock for WM8738 supports audio sampling rates from 256fs to 768fs, where fs is the audio sampling frequency LRCLK, typically 32kHz, 44.1kHz, 48kHz, or 96kHz. The master clock is used to operate the digital filters and the noise shaping circuits. The WM8738 has a master clock detection circuit that automatically determines the relationship between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If there is a greater than 32 clocks error the interface is disabled and maintains the output level at the last sample. The master clock must be synchronised with LRCLK, although the WM8738 is tolerant of phase variations or jitter on this clock. Table 1 shows the typical master clock frequency inputs for the WM8738. If MCLK is stopped for greater than 10us then the device will enter a low power mode where the current taken from AVDD is greatly reduced. Note that when the device enters this mode the references are powered down. Table 1 shows the common MCLK frequencies for different sample rates. Master Clock Frequency (MHz) SAMPLING RATE (LRCLK) 256fs 384fs 512fs 768fs 32kHz 8.192 12.288 16.384 24.576 44.1kHz 11.2896 16.9340 22.5792 33.8688 48kHz 12.288 18.432 24.576 36.864 96kHz 24.576 36.864 Unavailable Unavailable Table 1 Master Clock Frequency Selection

w PD Rev 4.4 August 2006 DIGITAL AUDIO INTERFACES The WM8738 has two data output formats, selectable via the FMT pin. FMT = 0 ADC audio data output is I2S FMT = 1 ADC audio data output is Left Justified Both of these modes are MSB first. The digital audio interface takes the data from the internal ADC digital filter. SDATO is the formatted digital audio data stream output from the ADC digital filters with left and right channels multiplexed together. LRCLK is an alignment clock that controls whether Left or Right channel data is present on the SDATO line. SDATO and LRCLK are synchronous with the BCLK signal with each data bit transition signified by a low to high BCLK transition. LEFT JUSTIFIED MODE In left justified mode, the MSB of the ADC data is output on SDATO and changes on the same falling edge of BCLK as LRCLK and may be sampled on the rising edge of BCLK. LRCLK is high during the left samples and low during the right samples. LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK SDATO 1/fs n n-2 n-1 LSB MSB n n-2 n-1 LSB MSB Figure 4 Left Justified Mode Timing Diagram I2S MODE In I2S mode, the MSB of the ADC data is output on SDATO and changes on the first falling edge of BCLK following an LRCLK transition and may be sampled on the rising edge of BCLK. LRCLK is low during the left samples and high during the right samples. LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK SDATO 1/fs n n-2 n-1 LSB MSB n n-2 n-1 LSB MSB

1 BCLK

Figure 5 I2S Mode Timing Diagram

w PD Rev 4.4 August 2006 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS DVDD DGND AVDD CAP C12 C11 AGND Hardware Control WM8738 DVDD FMT AVDD MCLK BCLK LRCLK SDATO Audio Serial Data I/F AGND NOHP AGND C RIN VREF C10 AGND Notes: 1. AGND and DGND should be connected as close to the WM8738 as possible. 2. C2, C3, C9 and C11 should be positioned as close to the WM8738 as possible. 3. Capacitor types should be carefully chosen. Capacitors with very low ESR are recommended for optimum performance. LIN C DVDD DVDD C C 8 R 1 R 4 R 2 R 3 Figure 9 External Components Diagram RECOMMENDED EXTERNAL COMPONENTS VALUES COMPONENT REFERENCE SUGGESTED VALUE 10µF De-coupling for DVDD and AVDD C2 and C3 0.1µF De-coupling for DVDD and AVDD C5 and C7 1µF Analogue input AC coupling caps C6 and C8 4.7nF Analogue input filtering (RC) capacitor R2 and R3 10kΩ Current limiting resistors R1 and R4 680Ω Analogue input filtering (RC) resistor 0.1µF C10 10µF Reference de-coupling capacitors for VREF pin C11 0.1µF C12 10µF Reference de-coupling capacitors for CAP pin Table 3 External Components Description

w PD Rev 4.4 August 2006 PACKAGE DIMENSIONS NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-012, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. Symbols Dimensions (mm) Dimensions (Inches) MIN MAX MIN MAX A 1.35 1.75 0.0532 0.0688 0.10 0.25 0.0040 0.0098 B 0.33 0.51 0.0130 0.0200 C 0.19 0.25 0.0075 0.0098 D 8.55 8.75 0.3367 0.3444 E 3.80 4.00 0.1497 0.1574 e

1.27 BSC

0.05 BSC

H 5.80 6.20 0.2284 0.2440 h 0.25 0.50 0.0099 0.0196 L 0.40 1.27 0.0160 0.0500 α REF: JEDEC.95, MS-012 0.10 (0.004) SEATING PLANE DM001.C E D: 14 PIN SOIC 3.9mm Wide Body H B D A C h x 45o -C- α L e

w PD Rev 4.4 August 2006 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc Westfield House

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