WM8983

WM8983 WOLFSON | Alldatasheet

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w WM8983 Mobile Multimedia CODEC with 1W Speaker Driver WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ Product Preview, August 2005, Rev 1.1 Copyright 2005 Wolfson Microelectronics plc

DESCRIPTION

The WM8983 is a low power, high quality stereo codec designed for portable multimedia applications. Highly flexible analogue mixing functions enable new application features, combining hi-fi quality audio with voice communication. The device integrates preamps for stereo differential mics, and includes drivers for speaker, headphone and differential or stereo line output. External component requirements are reduced as no separate microphone or headphone amplifiers are required. Advanced on-chip digital signal processing includes a 5-band equaliser, a mixed signal Automatic Level Control for the microphone or line input through the ADC as well as a purely digital limiter function for record or playback. A programmable high pass filter in the ADC path is provided for wind noise reduction and an IIR with programmable coefficients can be used as a notch filter to suppress fixed-frequency noise. The WM8983 digital audio interface can operate in master or slave mode, while an integrated PLL supports flexible clocking schemes. A-law and µ-law companding are fully supported. The WM8983 operates at analogue supply voltages from 2.5V to 3.3V, although the digital core can operate at voltages down to 1.71V to save power. Speaker supplies can operate up to 5V for increased speaker output power. Additional power management control enables individual sections of the chip to be powered down under software control.

FEATURES

Stereo Codec: DAC SNR 98dB, THD -84dB (‘A’ weighted @ 48kHz) ADC SNR 95dB, THD -84dB (‘A’ weighted @ 48kHz) Speaker driver (1W into 8Ω BTL with 5V supply) Headphone driver with ‘capless’ option 40mW per channel output power into 16Ω / 3.3V AVDD2 Pop and click suppression Mic Preamps: Stereo Differential or mono microphone Interfaces Programmable preamp gain Psuedo differential inputs with common mode rejection Programmable ALC / Noise Gate in ADC path Low-noise bias supplied for electret microphones Other Features: Enhanced 3-D function for improved stereo separation Highly flexible mixing functions 5-band equaliser (ADC or DAC path) ADC Programmable high pass filter (wind noise reduction) ADC Programmable IIR notch filter Aux inputs for stereo analog input signals or ‘beep’ PLL supporting various clocks between 8MHz-50MHz Sample rates supported (kHz): 8, 11.025, 16, 12, 16, 22.05, 24, 32, 44.1, 48 2.5V to 3.6V analogue supplies 1.71V to 3.6V digital supplies 2.5V to 5.5V speaker supplies 5x5mm 32-pin QFN package

APPLICATIONS

w PP Rev 1.1 August 2005 TABLE OF CONTENTS

w PP Rev 1.1 August 2005 PIN CONFIGURATION

ORDERING INFORMATION

-25°C to +85°C 32-pin QFN (5 x 5 mm) (lead free) MSL1 260oC WM8983GEFL/R -25°C to +85°C 32-pin QFN (5 x 5 mm) (lead free, tape and reel) MSL1 260oC Note: Reel quantity = 3,500

w PP Rev 1.1 August 2005 PIN DESCRIPTION PIN NAME TYPE Left MIC pre-amp positive input LIN Analogue input Left MIC pre-amp negative input L2/GPIO2 Analogue input Left channel line input/secondary mic pre-amp positive input/GPIO2 pin RIP Analogue input Right MIC pre-amp positive input RIN Analogue input Right MIC pre-amp negative input R2/GPIO3 Analogue input Right channel line input/secondary mic pre-amp positive input/GPIO3 pin LRC Digital Input / Output DAC and ADC sample rate clock BCLK Digital Input / Output Digital audio bit clock ADCDAT Digital Output ADC digital audio data output DACDAT Digital Input DAC digital audio data input MCLK Digital Input Master clock input DGND Supply Digital ground DCVDD Supply Digital core logic supply DBVDD Supply Digital buffer (I/O) supply CSB/GPIO1 Digital Input / Output 3-Wire control interface chip Select / GPIO1 pin SCLK Digital Input 3-Wire control interface clock input / 2-wire control interface clock input SDIN Digital Input / Output 3-Wire control interface data input / 2-Wire control interface data input MODE Digital Input Control interface selection AUXL Analogue input Left auxillary input AUXR Analogue input Right auxillary input OUT4 Analogue Output right line output or mono mix output OUT3 Analogue Output mono or left line output ROUT2 Analogue Output Headphone or line output right 2 AGND2 Supply Analogue ground (feeds ROUT2/LOUT2 and OUT3/OUT4) LOUT2 Analogue Output Headphone or line output left 2 AVDD2 Supply Analogue supply (feeds output amplifiers ROUT2/LOUT2 and OUT3/OUT4) VMID Reference Decoupling for ADC and DAC reference voltage AGND1 Supply Analogue ground (feeds all input amplifiers, PLL, ADC and DAC, internal bias circuits, output amplifiers LOUT1, ROUT1) ROUT1 Analogue Output Headphone or line output right 1 LOUT1 Analogue Output Headphone or line output left 1 AVDD1 Supply Analogue supply (feeds all input amplifiers, PLL, ADC and DAC, internal bias circuits, output amplifiers LOUT1, LOUT2)) MICBIAS Analogue Output Microphone bias Note: It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.

w PP Rev 1.1 August 2005 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION MIN MAX DBVDD, DCVDD, AVDD1 supply voltages -0.3V +3.63V AVDD2 supply voltage -0.3V +7V Voltage range digital inputs DGND -0.3V DVDD +0.3V Voltage range analogue inputs AGND1 -0.3V AVDD1 +0.3V Storage temperature prior to soldering 30°C max / 85% RH max Storage temperature after soldering -65°C +150°C Notes Analogue and digital grounds must always be within 0.3V of each other. All digital and analogue supplies are completely independent from each other. Analogue supply voltages should not be less than digital supply voltages. In non-boosted mode AVDD2 should be ≥ AVDD1. In boost mode, AVDD2 should be ≥ 1.5 x AVDD1. RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital supply range (Core) DCVDD 1.71 1.8 3.6 V Digital supply range (Buffer) DBVDD 1.712 3.3 3.6 V Analogue supply range AVDD1 2.5 3.3 3.6 V Speaker supply range AVDD2 2.5 3.3 5.5 V Ground DGND, AGND1, AGND2 V Notes Analogue supply voltages should not be less than digital supply voltages. DBVDD should be ≥ 1.9V when using the PLL.

w PP Rev 1.1 August 2005

ELECTRICAL CHARACTERISTICS

DCVDD=1.8V, AVDD1=AVDD2=DBVDD=AVDD2=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Microphone Preamp Inputs (LIP, LIN, RIP, RIN, L2, R2) Full-scale Input Signal Level – single ended input configuration via L/RIN. Note1 VINFSSE PGABOOST = 0dB INPPGAVOL = 0dB 1.0 Vrms dBV Full-scale Input Signal Level – pseudo differential input configuration via L/RIP and L/R2. Note1 VINFSPD PGABOOST = 0dB INPPGAVOL = 0dB 0.707 Vrms dBV Mic PGA equivalent input noise At 35.25dB gain 0 to 20kHz 150 uV Input resistance RMICIN Gain set to 35.25dB 1.6 kΩ Input resistance RMICIN Gain set to 0dB kΩ Input resistance RMICIN Gain set to -12dB kΩ Input resistance RMICIP RIP2INPPGA = 1 kΩ Input resistance RMICIP RIP2INPPGA = 0 kΩ Input Capacitance CMICIN pF MIC Programmable Gain Amplifier (PGA) Programmable Gain -12 35.25 dB Programmable Gain Step Size Guaranteed monotonic 0.75 dB Mute Attenuation 100 dB Selectable Input Gain Boost (0/+20dB) Boost disabled dB Gain Boost on PGA input Boost enabled dB Gain range from AUXL/R or L/R2 input to boost/mixer -12 dB Gain step size to boost/mixer dB Auxilliary Analogue Inputs (AUXL, AUXR) Full-scale Input Signal Level (0dB) – note this is proportional to AVDD1 VINFS AVDD1/3.3 Vrms dBV RAUXINLMIN Left Input boost and mixer enabled, at max gain 4.3 kΩ RAUXINLTYP Left Input boost and mixer enabled, at 0dB gain 8.6 kΩ RAUXINLMAX Left Input boost and mixer enabled, at min gain 39.1 kΩ RAUXINRMIN Right Input boost, mixer and beep enabled, at max gain kΩ RAUXINRTYP Right Input boost, mixer and beep enabled, at 0dB gain kΩ Input Resistance RAUXINRMAX Right Input boost, mixer and beep enabled, at min gain kΩ Input Capacitance CMICIN pF Automatic Level Control (ALC) Target Record Level -22.5 -1.5 dB Programmable gain -12 35.25

w PP Rev 1.1 August 2005 Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=AVDD2=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Gain Hold Time (Note 2,4) tHOLD MCLK = 12.288MHz (Note 2) (time doubles with each step) ms ALCMODE=0 (ALC), MCLK=12.288MHz (Note 2) (time doubles with each step) Gain Ramp-Up (Decay) Time (Note 3,4) tDCY ALCMODE=1 (limiter), MCLK=12.288MHz (Note 2) (time doubles with each step) ms ALCMODE=0 (ALC), MCLK=12.288MHz (Note 2) (time doubles with each step) Gain Ramp-Down (Attack) Time (Note 3,4) tATK ALCMODE=1 (limiter), MCLK=12.288MHz (Note 2) (time doubles with each step) ms Mute Attenuation 80dB dB Analogue to Digital Converter (ADC) Signal to Noise Ratio (Note 5,6) A-weighted, 0dB gain dB Total Harmonic Distortion (Note 7) full-scale, 0dB gain -84 dB Channel Separation (Note 8) 1kHz input signal 110 dB Digital to Analogue Converter (DAC) to L/R Mix to Line-Out (LOUT1, ROUT1 with 10kΩΩΩΩ / 50pF load) Full-scale output PGA gains set to 0dB AVDD1/3.3 Vrms Signal to Noise Ratio (Note 5,6) SNR A-weighted dB Signal to Noise Ratio (Note 5,6) SNR 22Hz to 20kHz 95.5 dB Total Harmonic Distortion (Note 7) THD RL = 10kΩ full-scale signal -84 dB Channel Separation (Note 8) 1kHz signal 110 dB Output Mixers (LMX1, RMX1) PGA gain range into mixer -15 dB PGA gain step into mixer dB Analogue Outputs (LOUT1, ROUT1, LOUT2, ROUT2) Programmable Gain range -57 dB Programmable Gain step size Monotonic dB Mute attenuation 1kHz, full scale signal dB Headphone Output (AUX to L/RMIX to LOUT1, ROUT1. LOUT2, ROUT2 with 32ΩΩΩΩ load) 0dB full scale output voltage With > 32R load AVDD1/3.3 Vrms Signal to Noise Ratio SNR A-weighted 102 dB RL = 16Ω, Po=20mW AVDD1=3.3V 0.003 -92 dB Total Harmonic Distortion THD RL = 32 Ω, Po=20mW AVDD1=3.3V 0.008 - 82 dB Headphone Output (DAC to L/RMIX to LOUT1, ROUT1 with 16ΩΩΩΩ load) Signal to Noise Ratio SNR A-weighted dB Signal to Noise Ratio SNR 22Hz to 20kHz TBD dB

w PP Rev 1.1 August 2005 Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=AVDD2=3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Speaker Output (LOUT2, ROUT2 with 8ΩΩΩΩ bridge tied load, INVROUT2=1) SPKBOOST=0 AVDD2/ 3.3 Full scale output voltage, 0dB gain. (Note 9) SPKBOOST=1 (AVDD2/ 3.3)*1.5 Vrms Output Power PO Output power is very closely correlated with THD; see below PO =200mW, RL = 8Ω, AVDD2=3.3V 0.04 -68 dB PO =320mW, RL = 8Ω, AVDD2=3.3V 1.0 -40 dB PO =500mW, RL = 8Ω, AVDD2=5V 0.02 -74 dB Total Harmonic Distortion THD PO =860mW, RL = 8Ω, AVDD2=5V 1.0 -40 dB AVDD2=3.3V, RL = 8Ω dB Signal to Noise Ratio SNR AVDD2=5V, RL = 8Ω dB RL = 8Ω BTL dB Power Supply Rejection Ratio (50Hz-22kHz) PSRR RL = 8Ω BTL AVDD2=5V (boost) dB AVDD2 = 5V Other supplies disconnected TBD SPKVDD Leakage Current AVDD2 = 5V Other supplies = 0V TBD uA OUT3/OUT4 outputs (with 10kΩΩΩΩ / 50pF load) OUT3BOOST=0/ OUT4BOOST=0 AVDD2/3.3 Vrms Full-scale output voltage, 0dB gain (Note 9) OUT3BOOST=1/ OUT4BOOST=1 1.5 x AVDD2/3.3 Vrms Signal to Noise Ratio (Note 5,6) SNR A-weighted dB Signal to Noise Ratio SNR 22Hz to 22kHz 97.5 dB Total Harmonic Distortion (Note 7) THD RL = 10 kΩ full-scale signal -84 dB Channel Separation (Note 8) 1kHz signal 100 dB RL = 10kΩ dB Power Supply Rejection Ratio (50Hz-22kHz) PSRR RL = 10kΩ, AVDD2=5V dB Microphone Bias MBVSEL=0 0.9*AVDD1 V Bias Voltage VMICBIAS MBVSEL=1 0.65*AVDD1 V Bias Current Source IMICBIAS for VMICBIAS within +/-3% mA Output Noise Voltage Vn 1kHz to 20kHz nV/√Hz Digital Input / Output Input HIGH Level VIH 0.7×DBV DD V Input LOW Level VIL 0.3×DBVDD V Output HIGH Level VOH IOL=1mA 0.9×DBV DD V Output LOW Level VOL IOH-1mA 0.1xDBVDD V Input capacitance TBD pF Input leakage TBD pA

w PP Rev 1.1 August 2005 TERMINOLOGY Note the full scale input level is proportional to AVDD1 and so will scale accordingly. Hold Time is the length of time between a signal detected being too quiet and beginning to ramp up the gain. It does not apply to ramping down the gain when the signal is too loud, which happens without a delay. Ramp-up and Ramp-Down times are defined as the time it takes for the PGA to sweep across 90% of its gain range. All hold, ramp-up and ramp-down times scale proportionally with MCLK Signal-to-noise ratio (dB) – SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) – DR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) – THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Channel Separation (dB) – Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. The maximum output voltage can be limited by the speaker power supply. If SPKBOOST is set then AVDD2 should be 1.5xAVDD to prevent clipping taking place in the output stage (when PGA gains are set to 0dB).

w PP Rev 1.1 August 2005 POWER CONSUMPTION TYPICAL SCENARIOS Estimated current consumption for typical scenarios are shown below. Power delivered to the load is not included. MODE IAVDD1 mA (3.3V) IAVDD2 mA (3.3V) IDCVDD mA (1.8V) IDBVDD mA (1.8V) TOTAL mW Off (No clocks, temperature sensor disabled) 0.010 0.010 0.001 0.002 0.071 Sleep (VREF maintained) 0.100 0.001 0.012 0.003 0.360 Mono Record from Differential MIC (8kHz, PLL enabled) 4.000 0.001 0.400 0.030 13.97 Stereo HP Playback (44.1kHz, PLL enabled) 3.700 0.950 2.100 0.100 19.31 Table 1 Power Consumption

w PP Rev 1.1 August 2005 AUDIO PATHS OVERVIEW

w PP Rev 1.1 August 2005 Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information LRC propagation delay from BCLK falling edge tDL ns ADCDAT propagation delay from BCLK falling edge tDDA ns DACDAT setup time to BCLK rising edge tDST ns DACDAT hold time from BCLK rising edge tDHT ns AUDIO INTERFACE TIMING – SLAVE MODE Figure 5 Digital Audio Data Timing – Slave Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK= 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY ns BCLK pulse width high tBCH ns BCLK pulse width low tBCL ns LRC set-up time to BCLK rising edge tLRSU ns LRC hold time from BCLK rising edge tLRH ns DACDAT hold time from BCLK rising edge tDH ns ADCDAT propagation delay from BCLK falling edge tDD ns Note: BCLK period should always be greater than or equal to MCLK period.

w PP Rev 1.1 August 2005 CONTROL INTERFACE TIMING – 3-WIRE MODE 3-wire mode is selected by connecting the MODE pin high. Figure 6 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CSB rising edge tSCS ns SCLK pulse cycle time tSCY 200 ns SCLK pulse width low tSCL ns SCLK pulse width high tSCH ns SDIN to SCLK set-up time tDSU ns SCLK to SDIN hold time tDHO ns CSB pulse width low tCSL ns CSB pulse width high tCSH ns CSB rising to SCLK rising tCSS ns Pulse width of spikes that will be suppressed tps ns

w PP Rev 1.1 August 2005 CONTROL INTERFACE TIMING – 2-WIRE MODE 2-wire mode is selected by connecting the MODE pin low. SDIN SCLK Figure 7 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK Frequency 526 kHz SCLK Low Pulse-Width 1.3 us SCLK High Pulse-Width 600 ns Hold Time (Start Condition) 600 ns Setup Time (Start Condition) 600 ns Data Setup Time 100 ns SDIN, SCLK Rise Time 300 ns SDIN, SCLK Fall Time 300 ns Setup Time (Stop Condition) 600 ns Data Hold Time 900 ns Pulse width of spikes that will be suppressed tps ns

w PP Rev 1.1 August 2005 DEVICE DESCRIPTION INTRODUCTION The WM8983 is a low power audio codec combining a high quality stereo audio DAC and ADC, with flexible line and microphone input and output processing. The chip offers great flexibility in use, and so can support many different modes of operation as follows: MICROPHONE INPUTS Two pairs of stereo microphone inputs are provided, allowing a pair of stereo microphones to be pseudo-differentially connected, with user defined gain. The provision of the common mode input pin for each stereo input allows for rejection of common mode noise on the microphone inputs (level depends on gain setting chosen). A microphone bias is output from the chip which can be used to bias both microphones. The signal routing can be configured to allow manual adjustment of mic levels, or to allow the ALC loop to control the level of mic signal that is transmitted. Total gain through the microphone paths of up to +55.25dB can be selected. PGA AND ALC OPERATION A programmable gain amplifier is provided in the input path to the ADC. This may be used manually or in conjunction with a mixed analogue/digital automatic level control (ALC) which keeps the recording volume constant. LINE INPUTS (AUXL, AUXR) AUXL and AUXR, can be used as a stereo line input or as an input for warning tones (or ‘beeps’) etc. These inputs can be summed into the record paths, along with the microphone preamp outputs, so allowing for mixing of audio with ‘backing music’ etc as required. ADC The stereo ADC uses a 24-bit high-order oversampling architecture to deliver optimum performance with low power consumption. HI-FI DAC The hi-fi DAC provides high quality audio playback suitable for all portable audio hi-fi type applications, including MP3 players, portable multimedia devices and portable disc players of all types. OUTPUT MIXERS Flexible mixing is provided on the outputs of the device. A stereo mixer is provided for the stereo headphone or line outputs, LOUT1/ROUT1, and additional summers on the OUT3/OUT4 outputs allow for an optional differential or stereo line output on these pins. Gain adjustment PGAs are provided for the LOUT1/ROUT1 and LOUT2/ROUT2 outputs, and signal switching is provided to allow for all possible signal combinations.

w PP Rev 1.1 August 2005 OUT3 and OUT4 can be configured to provide an additional stereo or mono differential lineout from the output of the DACs, the mixers or the input microphone boost stages. They can also provide a midrail reference for pseudo differential inputs to external amplifiers. AUDIO INTERFACES The WM8983 has a standard audio interface, to support the transmission of stereo data to and from the chip. This interface is a 3 wire standard audio interface which supports a number of audio data formats including: I2S DSP/PCM Mode (a burst mode in which LRC sync plus 2 data packed words are transmitted) MSB-First, left justified MSB-First, right justified The interface can operate in master or slave modes. CONTROL INTERFACES To allow full software control over all features, the WM8983 offers a choice of 2 or 3 wire control interface. It is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. Selection of the mode is via the MODE pin. In 2 wire mode, the address of the device is fixed as 0011010. CLOCKING SCHEMES WM8983 offers the normal audio DAC clocking scheme operation, where 256fs MCLK is provided to the DAC and ADC. A PLL is included which may be used to generate these clocks in the event that they are not available from the system controller. This PLL can accept a range of common input clock frequencies between 8MHz and 50MHz to generate high quality audio clocks. If this PLL is not required for generation of these clocks, it can be reconfigured to generate alternative clocks which may then be output on the GPIO pins and used elsewhere in the system. POWER CONTROL The design of the WM8983 has given much attention to power consumption without compromising performance. It operates at very low voltages, includes the ability to power off any unused parts of the circuitry under software control, and includes standby and power off modes. AUXILIARY ANALOG INPUT SUPPORT Additional stereo analog signals might be connected to the Line inputs of WM8983 (e.g. melody chip or FM radio), and the stereo signal listened to via headphones, or recorded, simultaneously if required.

w PP Rev 1.1 August 2005 INPUT SIGNAL PATH The WM8983 has a number of flexible analogue inputs. There are two input channels, Left and Right, each of which consists of an input PGA stage followed by a boost/mix stage which drives into the hi-fi ADC. Each input path has three input pins which can be configured in a variety of ways to accommodate single-ended, differential or dual differential microphones. There are two auxiliary input pins which can be fed into to the input boost/mix stage as well as driving into the output path. A bypass path exists from the output of the boost/mix stage into the output left/right mixers. MICROPHONE INPUTS The WM8983 can accommodate a variety of microphone configurations including single ended and pseudo differential inputs. The inputs to the left pseudo differential input PGA are LIP and L2. The inputs to the right pseudo differential input PGA are RIP and R2. LIN and RIN are used for a.c. coupled ground inputs. In single-ended microphone input configuration the microphone signal should be input to LIN or RIN and the non-inverting input of the input PGA clamped to VMID. Figure 11 Microphone Input PGA Circuit The input PGAs are enabled by the IPPGAENL/R register bits. REGISTER ADDRESS BIT LABEL DEFAULT Left channel input PGA enable 0 = disabled 1 = enabled Power Management INPPGAENR Right channel input PGA enable 0 = disabled 1 = enabled Table 3 Input PGA Enable Register Settings

w PP Rev 1.1 August 2005 REGISTER ADDRESS BIT LABEL DEFAULT Connect LIP pin to left channel input PGA amplifier positive terminal. 0 = LIP not connected to input PGA 1 = input PGA amplifier positive terminal connected to LIP (constant input impedance) LIN2INPPGA Connect LIN pin to left channel input PGA negative terminal. 0 = LIN not connected to input PGA 1 = LIN connected to input PGA amplifier negative terminal. L2_2INPPGA Connect L2 pin to left channel input PGA positive terminal. 0 = L2 not connected to input PGA 1 = L2 connected to input PGA amplifier positive terminal (constant input impedance). RIP2INPPGA Connect RIP pin to right channel input PGA amplifier positive terminal. 0 = RIP not connected to input PGA 1 = right channel input PGA amplifier positive terminal connected to RIP (constant input impedance) RIN2INPPGA Connect RIN pin to right channel input PGA negative terminal. 0 = RIN not connected to input PGA 1 = RIN connected to right channel input PGA amplifier negative terminal. R44 Input Control R2_2INPPGA Connect R2 pin to right channel input PGA positive terminal. 0 = R2 not connected to input PGA 1 = R2 connected to input PGA amplifier positive terminal (constant input impedance). Table 4 Input PGA Control INPUT PGA VOLUME CONTROLS The input microphone PGAs have a gain range from -12dB to +35.25dB in 0.75dB steps. The gain from the LIN/RIN input to the PGA output and from the L2/R2 amplifier to the PGA output are always common and controlled by the register bits INPPGAVOLL/R[5:0]. These register bits also affect the LIP pin when LIP2INPPGA=1, the L2 pin when L2_2INPPGA=1, the RIP pin when RIP2INPPGA=1 and the L2 pin when L2_2INPPGA=1. When the Automatic Level Control (ALC) is enabled the input PGA gains are controlled automatically and the INPPGAVOLL/R bits should not be used.

w PP Rev 1.1 August 2005 REGISTER ADDRESS BIT LABEL DEFAULT 5:0 INPPGAVOLL 010000 Left channel input PGA volume 000000 = -12dB 000001 = -11.25db 010000 = 0dB 111111 = +35.25dB INPPGAMUTEL Mute control for left channel input PGA: 0 = Input PGA not muted, normal operation 1 = Input PGA muted (and disconnected from the following input BOOST stage). INPPGAZCL Left channel input PGA zero cross enable: 0 = Update gain when gain register changes 1 = Update gain on 1st zero cross after gain register write. R45 Left channel input PGA volume control INPPGAVU Not latched INPPGA left and INPPGA right volume do not update until a 1 is written to INPPGAVU (in reg 45 or 46) (See "Volume Updates" below) 5:0 INPPGAVOLR 010000 Right channel input PGA volume 000000 = -12dB 000001 = -11.25db 010000 = 0dB 111111 = +35.25dB INPPGAMUTER Mute control for right channel input PGA: 0 = Input PGA not muted, normal operation 1 = Input PGA muted (and disconnected from the following input BOOST stage). INPPGAZCR Right channel input PGA zero cross enable: 0 = Update gain when gain register changes 1 = Update gain on 1st zero cross after gain register write. R46 Right channel input PGA volume control INPPGAVU Not latched INPPGA left and INPPGA right volume do not update until a 1 is written to INPPGAVU (in reg 45 or 46) (See "Volume Updates" below) R32 ALC control 8:7 ALCSEL ALC function select: 00 = ALC off 01 = ALC right only 10 = ALC left only 11 = ALC both on Table 5 Input PGA Volume Control

w PP Rev 1.1 August 2005 AUXILLIARY INPUTS There are two auxiliary inputs, AUXL and AUXR which can be used for a variety of purposes such as stereo line inputs or as a ‘beep’ input signal to be mixed with the outputs. As signal inputs, AUXL/R inputs can be used as a line input to the input BOOST stage which has adjustable gain of -12dB to +6dB in 3dB steps, with an additional "off" state (i.e. not connected to ADC input). See the INPUT BOOST section for further details. The AUXL/R inputs can also be mixed into the output channel mixers, with a gain of -15dB to +6dB plus off. INPUT BOOST Each of the stereo input PGA stages is followed by an input BOOST circuit. The input BOOST circuit has 3 selectable inputs: the input microphone PGA output, the AUX amplifier output and the L2/R2 input pin (can be used as a line input, bypassing the input PGA). These three inputs can be mixed together and have individual gain boost/adjust as shown in Figure 16. Figure 16 Input Boost Stage The input PGA paths can have a +20dB boost (PGABOOSTL/R=1) , a 0dB pass through (PGABOOSTL/R=0) or be completely isolated from the input boost circuit (INPPGAMUTEL/R=1). REGISTER ADDRESS BIT LABEL DEFAULT Boost enable for left channel input PGA: 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. R48 Right Input BOOST control PGABOOSTR Boost enable for right channel input PGA: 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. Table 6 Input BOOST Stage Control The Auxilliary amplifier path to the BOOST stages is controlled by the AUXL2BOOSTVOL[2:0] and AUXR2BOOSTVOL[2:0] register bits. When AUXL2BOOSTVOL/AUXR2BOOSTVOL=000 this path is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB. The L2/R2 path to the BOOST stage is controlled by the LIP2BOOSTVOL[2:0] and the RIP2BOOSTVOL[2:0] register bits. When L2_2BOOSTVOL/R2_2BOOSTVOL=000 the L2/R2 input pin is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB.

w PP Rev 1.1 August 2005 REGISTER ADDRESS BIT LABEL DEFAULT 8:6 OUT4_2ADCVOL 000 Controls the OUT4 to ADC input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage 111=+6dB gain through boost stage R42 OUT4 to ADC OUT4_2LNR OUT4 to L or R ADC input 0 = Right ADC input 1 = Left ADC input 2:0 AUXL2BOOSTVOL 000 Controls the auxiliary amplifier to the left channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage 111=+6dB gain through boost stage R47 Left channel Input BOOST control 6:4 L2_2BOOSTVOL 000 Controls the L2 pin to the left channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage 111=+6dB gain through boost stage R48 Right channel Input BOOST control 2:0 AUXR2BOOSTVOL 000 Controls the auxiliary amplifier to the right channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage 111=+6dB gain through boost stage 6:4 R2_2BOOSTVOL 000 Controls the R2 pin to the right channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage 111=+6dB gain through boost stage Table 7 Input BOOST Stage Control The BOOST stage is enabled under control of the BOOSTEN register bit.

w PP Rev 1.1 August 2005 REGISTER ADDRESS BIT LABEL DEFAULT Left channel Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON Power management BOOSTENR Right channel Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON Table 8 Input BOOST Enable Control MICROPHONE BIASING CIRCUIT The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. Refer to the Applications Information section for recommended external components. The MICBIAS voltage can be altered via the MBVSEL register bit. When MBVSEL=0, MICBIAS=0.9*AVDD1 and when MBVSEL=1, MICBIAS=0.65*AVDD1. The output can be enabled or disabled using the MICBEN control bit. REGISTER ADDRESS BIT LABEL DEFAULT 0 = OFF (high impedance output) 1 = ON Table 9 Microphone Bias Enable Control REGISTER ADDRESS BIT LABEL DEFAULT Microphone Bias Voltage Control 0 = 0.9 * AVDD1 1 = 0.65 * AVDD1 Table 10 Microphone Bias Voltage Control The internal MICBIAS circuitry is shown in Figure 17. Note that the maximum source current capability for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit the MICBIAS current to 3mA. Figure 17 Microphone Bias Schematic AGND1 MBVSEL=0 MICBIAS = 1.8 x VMID = 0.9 X AVDD1 VMID internal resistor internal resistor MICBEN MBVSEL=1 MICBIAS = 1.3 x VMID = 0.65 X AVDD1 MICBIAS

w PP Rev 1.1 August 2005 ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8983 uses stereo multi-bit, oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD1. With a 3.3V supply voltage, the full scale level is 1.0Vrms. Any voltage greater than full scale may overload the ADC and cause distortion. ADC DIGITAL FILTERS The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital filter path for each ADC channel is illustrated in Figure 18. Figure 18 ADC Digital Filter Path The ADCs are enabled by the ADCENL/R register bit. REGISTER ADDRESS BIT LABEL DEFAULT Enable ADC left channel: 0 = ADC disabled 1 = ADC enabled Power management 2 ADCENR Enable ADC right channel: 0 = ADC disabled 1 = ADC enabled Table 11 ADC Enable Control The polarity of the output signal can also be changed under software control using the ADCLPOL/ADCRPOL register bit. The oversampling rate of the ADC can be adjusted using the ADCOSR register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power operation and when ADCOSR=1 the oversample rate is 128x which gives best performance. REGISTER ADDRESS BIT LABEL DEFAULT ADC left channel polarity adjust: 0 = normal 1 = inverted ADCRPOL ADC right channel polarity adjust: 0 = normal 1 = inverted R14 ADC Control ADCOSR ADC oversample rate select: 0 = 64x (lower power) 1 = 128x (best performance) Table 12 ADC Control

w PP Rev 1.1 August 2005 SELECTABLE HIGH PASS FILTER A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown in Table 14. REGISTER ADDRESS BIT LABEL DEFAULT 0 = disabled 1 = enabled HPFAPP Select audio mode or application mode 0 = Audio mode (1st order, fc = ~3.7Hz) 1 = Application mode (2nd order, fc = HPFCUT) R14 ADC Control 6:4 HPFCUT 000 Application mode cut-off frequency See Table 14 for details. Table 13 ADC Enable Control SR=101/100 SR=011/010 SR=001/000 fs (kHz) HPFCUT [2:0] 11.025 22.05 44.1 000 113 122 113 122 113 122 001 102 141 153 102 141 153 102 141 153 010 131 180 156 131 180 156 131 180 156 011 163 225 245 163 225 245 163 225 245 100 204 281 306 204 281 306 204 281 306 101 261 360 392 261 360 392 261 360 392 110 327 450 490 327 450 490 327 450 490 111 408 563 612 408 563 612 408 563 612 Table 14 High Pass Filter Cut-off Frequencies (HPFAPP=1) Note that the High Pass filter values (when HPFAPP=1) are calculated on the assumption that the SR register bits are set correctly for the actual sample rate as shown in Table 14.

w PP Rev 1.1 August 2005 PROGRAMMABLE IIR NOTCH FILTER A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits NFA0[13:0] and NFA1[13:0]. Because these coefficient values require four register writes to setup there is an NFU (Notch Filter Update) flag which should be set only when all four registers are setup. REGISTER ADDRESS BIT LABEL DEFAULT 6:0 NFA0[13:7] Notch Filter a0 coefficient, bits [13:7] NFEN Notch filter enable: 0 = Disabled 1 = Enabled R27 Notch Filter 1 NFU Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. 6:0 NFA0[6:0] Notch Filter a0 coefficient, bits [6:0] R28 Notch Filter 2 NFU Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. 6:0 NFA1[13:7] Notch Filter a1 coefficient, bits [13:7] R29 Notch Filter 3 NFU Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. 0-6 NFA1[6:0] Notch Filter a1 coefficient, bits [6:0] R30 Notch Filter 4 NFU Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Table 15 Notch Filter Function The coefficients are calculated as follows: tan( tan( b b w w a cos( w a a Where: s c f f w π s b b f f w fc = centre frequency in Hz, fb = -3dB bandwidth in Hz, fs = sample frequency in Hz The actual register values can be determined from the coefficients as follows: NFA0 = -a0 x 213 NFA1 = -a1 x 212 DIGITAL ADC VOLUME CONTROL The output of the ADCs can be digitally attenuated over a range from –127dB to 0dB in 0.5dB steps. The gain for a given eight-bit code X is given by: 0.5 × (G-255) dB for 1 ≤ G ≤ 255; MUTE for G = 0

w PP Rev 1.1 August 2005 REGISTER ADDRESS BIT LABEL DEFAULT 7:0 ADCLVOL [7:0] 11111111 ( 0dB ) Left ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB R15 Left channel ADC Digital Volume ADCVU Not latched ADC left and ADC right volume do not update until a 1 is written to ADCVU (in reg 15 or 16) 7:0 ADCRVOL [7:0] 11111111 ( 0dB ) Right ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB R16 Right channel ADC Digital Volume ADCVU Not latched ADC left and ADC right volume do not update until a 1 is written to ADCVU (in reg 15 or 16) Table 16 ADC Digital Volume Control

w PP Rev 1.1 August 2005 INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) The WM8983 has an automatic PGA gain control circuit, which can function as an input peak limiter or as an automatic level control (ALC). In input peak limiter mode (ALCMODE bit = 1), a digital peak detector detects when the input signal goes above a predefined level and will ramp the PGA gain down to prevent the signal becoming too large for the input range of the ADC. When the signal returns to a level below the threshold, the PGA gain is slowly returned to its starting level. The peak limiter cannot increase the PGA gain above its static level. Figure 19 Input Peak Limiter Operation In ALC mode (ALCMODE bit = 0) the circuit aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary.

w PP Rev 1.1 August 2005 Figure 20 ALC Operation The ALC/Limiter function is enabled by setting the register bit ALCSEL. When enabled, the recording volume can be programmed between –6dB and –28.5dB (relative to ADC full scale) using the ALCLVL register bits. An upper limit for the PGA gain can be imposed by setting the ALCMAX control bits and a lower limit for the PGA gain can be imposed by setting the ALCMIN control bits. ALCHLD, ALCDCY and ALCATK control the hold, decay and attack times, respectively: Hold time is the time delay between the peak level detected being below target and the PGA gain active in limiter mode (ALCMODE = 1). The hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is above target. Decay (Gain Ramp-Up) Time is the time that it takes for the PGA gain to ramp up and is given as a time per gain step, time per 6dB change and time to ramp up over 90% of it’s range. The decay time can be programmed in power-of-two (2n) steps, from 3.3ms/6dB, 6.6ms/6dB, 13.1ms/6dB, etc. to 3.36s/6dB. Attack (Gain Ramp-Down) Time is the time that it takes for the PGA gain to ramp down and is given as a time per gain step, time per 6dB change and time to ramp down over 90% of it’s range. The attack time can be programmed in power-of-two (2n) steps, from 832us/6dB, 1.66ms/6dB, 3.328us/6dB, etc. to 852ms/6dB. NB, In peak limiter mode the gain control circuit runs approximately 4x faster to allow reduction of fast peaks. Attack and Decay times for peak limiter mode are given below. The hold, decay and attack times given in Table 17 are constant across sample rates so long as the SR bits are set correctly. E.g. when sampling at 48kHz the sample rates stated in Table 17 will only be correct if the SR bits are set to 000 (48kHz). If the actual sample rate was only 44.1kHz then the hold, decay and attack times would be scaled down by 44.1/48. Note: Zero cross function can affect these time constants, and is not recommended for use during ALC operation.

w PP Rev 1.1 August 2005 REGISTER ADDRESS BIT LABEL DEFAULT 8:7 ALCSEL ALC function select 00 = ALC disabled 01 = Right channel ALC enabled 10 = Left channel ALC enabled 11 = Both channels ALC enabled 5:3 ALCMAXGAIN [2:0] 111 (+35.25dB) Set Maximum Gain of PGA 111 = +35.25dB 110 = +29.25dB 101 = +23.25dB 100 = +17.25dB 011 = +11.25dB 010 = +5.25dB 001 = -0.75dB 000 = -6.75dB R32 ALC Control 2:0 ALCMINGAIN [2:0] 000 (-12dB) Set minimum gain of PGA 000 = -12dB 001 = -6dB 010 = 0dB 011 = +6dB 100 = +12dB 101 = +18dB 110 = +24dB 111 = +30dB 7:4 ALCHLD [3:0] 0000 (0ms) ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms … (time doubles with every step) 1111 = 43.691s 3:0 ALCLVL [3:0] 1011 (-12dB) ALC target – sets signal level at ADC input 1111 = -1.5dBFS 1110 = -1.5dBFS 1101 = -3dBFS 1100 = -4.5dBFS 0001 = -21dBFS 0000 = -22.5dBFS R33 ALC Control ALCZC 0 (zero cross off) ALC uses zero cross detection circuit. (not recommended for use with ALC)

w PP Rev 1.1 August 2005 ALCMODE Determines the ALC mode of operation: 0 = ALC mode 1 = Limiter mode. Decay (gain ramp-up) time (ALCMODE ==0) Per step Per 6dB 90% of range 0000 410us 3.3ms 24ms 0001 820us 6.6ms 48ms 0010 1.64ms 13.1ms 192ms … (time doubles with every step) 0011 (13ms/6dB) 1010 or higher 420ms 3.36s 24.576s Decay (gain ramp-up) time (ALCMODE ==1) Per step Per 6dB 90% of range 0000 90.8us 726.4us 5.26ms 0001 181.6us 1.453 ms 10.53 ms 0010 363.2us 2.905 ms 21.06 ms … (time doubles with every step) 7:4 ALCDCY [3:0] 0011 (2.9ms/6dB) 1010 93ms 744ms 5.39s ALC attack (gain ramp-down) time (ALCMODE == 0) Per step Per 6dB 90% of range 0000 104us 832us 6ms 0001 208us 1.664 ms 12ms 0010 416us 3.328 ms 24.1ms … (time doubles with every step) 0010 (832us/6dB) 1010 or higher 106ms 852ms 6.18s ALC attack (gain ramp-down) time (ALCMODE == 1) Per step Per 6dB 90% of range 0000 22.7us 182.4us 1.31ms 0001 45.4us 363.2us 2.62ms 0010 90.8us 726.4us 5.26ms … (time doubles with every step) R34 ALC Control 3:0 ALCATK [3:0] 0010 (182us/6dB) 1010 23.2ms 186ms 1.348s Table 17 ALC Control Registers When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update must be made by writing to the INPPGAVOLL/R register bits.

w PP Rev 1.1 August 2005 MINIMUM AND MAXIMUM GAIN The ALCMINGAIN and ALCMAXGAIN register sets the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled. PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ALCATK = 0000), until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled. Note: If ALCATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed to prevent clipping when long attack times are used. NOISE GATE When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise pumping”, i.e. loud hissing noise during silence periods. The WM8983 has a noise gate function that prevents noise pumping by comparing the signal level at the input pins against a noise gate threshold, NGTH. The noise gate cuts in when: Signal level at ADC [dBFS] < NGTH [dBFS] + PGA gain [dB] + Mic Boost gain [dB] This is equivalent to: Signal level at input pin [dBFS] < NGTH [dBFS] The PGA gain is then held constant (preventing it from ramping up as it normally would when the signal is quiet). The table below summarises the noise gate control register. The NGTH control bits set the noise gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps. Levels at the extremes of the range may cause inappropriate operation, so care should be taken with set–up of the function. The noise gate only operates in conjunction with the ALC and cannot be used in limiter mode. REGISTER ADDRESS BIT LABEL DEFAULT 2:0 NGTH 000 Noise gate threshold: 000 = -39dB 001 = -45dB 010 = -51db … (6dB steps) 111 = -81dB R35 ALC Noise Gate Control NGATEN Noise gate function enable 1 = enable 0 = disable Table 18 ALC Noise Gate Control

w PP Rev 1.1 August 2005 OUTPUT SIGNAL PATH The WM8983 output signal paths consist of digital application filters, up-sampling filters, stereo Hi-Fi DACs, analogue mixers, stereo headphone and stereo line/mono/midrail output drivers. The digital filters and DAC are enabled by register bits DACENL And DACENR. The mixers and output drivers can be separately enabled by individual control bits (see Analogue Outputs). Thus it is possible to utilise the analogue mixing and amplification provided by the WM8983, irrespective of whether the DACs are running or not. The WM8983 DACs receive digital input data on the DACDAT pin. The digital filter block processes the data to provide the following functions: Digital volume control Graphic equaliser A digital peak limiter. Sigma-Delta Modulation High performance sigma-delta audio DAC converts the digital data into an analogue signal. Figure 21 DAC Digital Filter Path The analogue outputs from the DACs can then be mixed with the aux analogue inputs and the ADC analogue inputs. The mix is fed to the output drivers for headphone (LOUT1/ROUT1, LOUT2/ROUT2) or line (OUT3/OUT4). OUT3 and OUT4 have additional mixers which allow them to output different signals to the headphone and line outputs. DIGITAL PLAYBACK (DAC) PATH Digital data is passed to the WM8983 via the flexible audio interface and is then passed through a variety of advanced digital filters as shown in Figure 21 to the hi-fi DACs. The DACs are enabled by the DACENL/R register bits. REGISTER ADDRESS BIT LABEL DEFAULT 0 = DAC disabled 1 = DAC enabled Power Management 3 DACENR Right channel DAC enable 0 = DAC disabled 1 = DAC enabled Table 19 DAC Enable Control The WM8983 also has a Soft Mute function, which when enabled, gradually attenuates the volume of the digital signal to zero. When disabled, the gain will ramp back up to the digital gain setting. This function is enabled by default. To play back an audio signal, it must first be disabled by setting the SOFTMUTE bit to zero.

w PP Rev 1.1 August 2005 REGISTER ADDRESS BIT LABEL DEFAULT Left DAC output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) DACRPOL Right DAC output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) AMUTE Automute enable 0 = Amute disabled 1 = Amute enabled DACOSR DAC oversampling rate: 0 = 64x (lowest power) 1 = 128x (best performance) R10 DAC Control SOFTMUTE Softmute enable: 0 = Enabled 1 = Disabled Table 20 DAC Control Register The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters the multi-bit, sigma-delta DACs, which convert it to a high quality analogue audio signal. The multi-bit DAC architecture reduces high frequency noise and sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and low distortion. The DAC output phase defaults to non-inverted. Setting DACLPOL will invert the DAC output phase on the left channel and DACRPOL inverts the phase on the right channel. AUTO-MUTE The DAC has an auto-mute function which applies an analogue mute when 1024 consecutive zeros are detected. The mute is released as soon as a non-zero sample is detected. Auto-mute can be disabled using the AMUTE control bit. DIGITAL HI-FI DAC VOLUME (GAIN) CONTROL The signal volume from each Hi-Fi DAC can be controlled digitally. The gain range is –127dB to 0dB in 0.5dB steps. The level of attenuation for an eight-bit code X is given by: 0.5 × (X-255) dB for 1 ≤ X ≤ 255; MUTE for X = 0

w PP Rev 1.1 August 2005 REGISTER ADDRESS BIT LABEL DEFAULT 7:0 DACLVOL [7:0] 11111111 ( 0dB ) Left DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB R11 Left DAC Digital Volume DACVU Not latched DAC left and DAC right volume do not update until a 1 is written to DACVU (in reg 11 or 12) 7:0 DACRVOL [7:0] 11111111 ( 0dB ) Right DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB R12 Right DAC Digital Volume DACVU Not latched DAC left and DAC right volume do not update until a 1 is written to DACVU (in reg 11 or 12) Table 21 DAC Digital Volume Control Note: An additional gain of up to 12dB can be added using the gain block embedded in the digital peak limiter circuit (see DAC OUTPUT LIMITER section). 5-BAND EQUALISER A 5-band graphic equaliser function which can be used to change the output frequency levels to suit the environment. This can be applied to the ADC or DAC path and is described in the 5-BAND EQUALISER section for further details on this feature. 3-D ENHANCEMENT The WM8983 has an advanced digital 3-D enhancement feature which can be used to vary the perceived stereo separation of the left and right channels. Like the 5-band equaliser this feature can be applied to either the ADC record path or the DAC plaback path but not both simultaneously. Refer to the 3-D STEREO ENHANCEMENT section for further details on this feature. DAC DIGITAL OUTPUT LIMITER The WM8983 has a digital output limiter function. The operation of this is shown in Figure 22. In this diagram the upper graph shows the envelope of the input/output signals and the lower graph shows the gain characteristic.

w PP Rev 1.1 August 2005 Figure 22 DAC Digital Limiter Operation The limiter has a programmable upper threshold which is close to 0dB. Referring to Figure 22, in normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the limiter. Signals above the upper threshold are attenuated at a specific attack rate (set by the LIMATK register bits) until the signal falls below the threshold. The limiter also has a lower threshold 1dB below the upper threshold. When the signal falls below the lower threshold the signal is amplified at a specific decay rate (controlled by LIMDCY register bits) until a gain of 0dB is reached. Both threshold levels are controlled by the LIMLVL register bits. The upper threshold is 0.5dB above the value programmed by LIMLVL and the lower threshold is 0.5dB below the LIMLVL value. VOLUME BOOST The limiter has programmable upper gain which boosts signals below the threshold to compress the dynamic range of the signal and increase its perceived loudness. This operates as an ALC function with limited boost capability. The volume boost is from 0dB to +12dB in 1dB steps, controlled by the LIMBOOST register bits. The output limiter volume boost can also be used as a stand alone digital gain boost when the limiter is disabled.

w PP Rev 1.1 August 2005 REGISTER ADDRESS BIT LABEL DEFAULT 3:0 LIMATK 0010 Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note that these are proportionally related to sample rate. 0000 = 94us 0001 = 188s 0010 = 375us 0011 = 750us 0100 = 1.5ms 0101 = 3ms 0110 = 6ms 0111 = 12ms 1000 = 24ms 1001 = 48ms 1010 = 96ms 1011 to 1111 = 192ms 7:4 LIMDCY 0011 Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these are proportionally related to sample rate: 0000 = 750us 0001 = 1.5ms 0010 = 3ms 0011 = 6ms 0100 = 12ms 0101 = 24ms 0110 = 48ms 0111 = 96ms 1000 = 192ms 1001 = 384ms 1010 = 768ms 1011 to 1111 = 1.536s R24 DAC digital limiter control LIMEN Enable the DAC digital limiter: 0 = disabled 1 = enabled 3:0 LIMBOOST 0000 Limiter volume boost (can be used as a stand alone volume boost when LIMEN=0): 0000 = 0dB 0001 = +1dB 0010 = +2dB 0011 = +3dB 0100 = +4dB 0101 = +5dB 0110 = +6dB 0111 = +7dB 1000 = +8dB 1001 = +9dB 1010 = +10dB 1011 = +11dB 1100 = +12dB 1101 to 1111 = reserved R25 DAC digital limiter control 6:4 LIMLVL 000 Programmable signal threshold level (determines level at which the limiter starts to operate) 000 = -1dB 001 = -2dB 010 = -3dB 011 = -4dB 100 = -5dB 101 to 111 = -6dB Table 22 DAC Digital Limiter Control

w PP Rev 1.1 August 2005 5-BAND GRAPHIC EQUALISER A 5-band graphic equaliser is provided, which can be applied to the ADC or DAC path, together with 3D enhancement, under control of the EQ3DMODE register bit. The ADCs and DACs should be disabled before changing the AQ3DMODE bit. REGISTER ADDRESS BIT LABEL DEFAULT 0 = Equaliser and 3D Enhancement applied to ADC path 1 = Equaliser and 3D Enhancement applied to DAC path Table 23 EQ and 3D Enhancement DAC or ADC Path Select The equaliser consists of low and high frequency shelving filters (Band 1 and 5) and three peak filters for the centre bands. Each has adjustable cut-off or centre frequency, and selectable boost (+/- 12dB in 1dB steps). The peak filters have selectable bandwidth. REGISTER ADDRESS BIT LABEL DEFAULT 4:0 EQ1G 01100 (0dB) Band 1 Gain Control. See Table 29 for details. R18 EQ Band 1 Control 6:5 EQ1C Band 1 Cut-off Frequency: 00 = 80Hz 01 = 105Hz 10 = 135Hz 11 = 175Hz Table 24 EQ Band 1 Control REGISTER ADDRESS BIT LABEL DEFAULT 4:0 EQ2G 01100 (0dB) Band 2 Gain Control. See Table 29 for details. 6:5 EQ2C Band 2 Centre Frequency: 00 = 230Hz 01 = 300Hz 10 = 385Hz 11 = 500Hz R19 EQ Band 2 Control EQ2BW Band 2 Bandwidth Control 0 = narrow bandwidth 1 = wide bandwidth Table 25 EQ Band 2 Control REGISTER ADDRESS BIT LABEL DEFAULT 4:0 EQ3G 01100 (0dB) Band 3 Gain Control. See Table 29 for details. 6:5 EQ3C Band 3 Centre Frequency: 00 = 650Hz 01 = 850Hz 10 = 1.1kHz 11 = 1.4kHz R20 EQ Band 3 Control EQ3BW Band 3 Bandwidth Control 0 = narrow bandwidth 1 = wide bandwidth Table 26 EQ Band 3 Control

w PP Rev 1.1 August 2005 REGISTER ADDRESS BIT LABEL DEFAULT 4:0 EQ4G 01100 (0dB) Band 4 Gain Control. See Table 29 for details 6:5 EQ4C Band 4 Centre Frequency: 00 = 1.8kHz 01 = 2.4kHz 10 = 3.2kHz 11 = 4.1kHz R21 EQ Band 4 Control EQ4BW Band 4 Bandwidth Control 0 = narrow bandwidth 1 = wide bandwidth Table 27 EQ Band 4 Control REGISTER ADDRESS BIT LABEL DEFAULT 4:0 EQ5G 01100 (0dB) Band 5 Gain Control. See Table 29 for details. R22 EQ Band 5 Gain Control 6:5 EQ5C Band 5 Cut-off Frequency: 00 = 5.3kHz 01 = 6.9kHz 10 = 9kHz 11 = 11.7kHz Table 28 EQ Band 5 Control GAIN REGISTER GAIN 00000 +12dB 00001 +11dB 00010 +10dB 00011 +9dB 00100 +8dB 00101 +7dB 00110 +6dB 00111 +5dB 01000 +4dB 01001 +3dB 01010 +2dB 01011 +1dB 01100 0dB 01101 -1dB 11000 -12dB 11001 to 11111 Reserved Table 29 Gain Register Table See also Figure 51 to Figure 68 for equaliser and high pass filter responses.

w PP Rev 1.1 August 2005 3D STEREO ENHANCEMENT The WM8983 has a digital 3D enhancement option to increase the perceived separation between the left and right channels. Selection of 3D for record or playback is controlled by register bit EQ3DMODE. Switching this bit from record to playback or from playback to record may only be done when ADC and DAC are disabled. The WM8983 control interface will only allow EQ3DMODE to be changed when ADC and DAC are disabled (ie ADCENL = 0, ADCENR = 0, DACENL = 0 and DACENR = 0). The DEPTH3D setting controls the degree of stereo expansion. When 3D enhancement is used, it may be necessary to attenuate the signal by 6dB to avoid limiting. REGISTER ADDRESS BIT LABEL DEFAULT R41 (29h) 3D Control 3:0 DEPTH3D[3:0] 0000 Stereo depth 0000: 0% (minimum 3D effect) 0001: 6.67% 0010: 13.33 0011: 20.00 0100: 26.67 0101: 33.33 0110: 40.0 0111: 46.67 1000: 53.33 1001: 60.00 1010: 66.67 1011: 73.33 1100: 80.00 1101: 86.67 1110: 93.3% 1111: 100% (maximum 3D effect) Table 30 3D Stereo Enhancement Function ANALOGUE OUTPUTS The WM8983 has three sets of stereo analogue outputs. These are: LOUT1 and ROUT1 which are normally used to drive a headphone load. LOUT2 and ROUT2 – which can be used as speaker, headphone or line drivers. OUT3 and OUT4 – can be configured as a stereo line out (OUT3 is left output and OUT4 is right output). OUT4 can also be used to provide a mono mix of left and right channels. The outputs LOUT2, ROUT2 OUT3 and OUT4 are powered from AVDD2 and are capable of driving a 1V rms signal (AVDD1/3.3) in non-boost mode and AVDD1*1.5/3.3 in boost mode. LOUT1 and ROUT1 are supplied from AVDD1 and can drive out a 1V rms signal (AVDD1/3.3). LOUT1, ROUT1, LOUT2 and ROUT2 have individual analogue volume PGAs with -57dB to +6dB gain ranges. There are four output mixers in the output signal path, the left and right channel mixers which control the signals to headphone (and optionally the line outputs) and also dedicated OUT3 and OUT4 mixers.

w PP Rev 1.1 August 2005 LEFT AND RIGHT OUTPUT CHANNEL MIXERS The left and right output channel mixers are shown in Figure 23. These mixers allow the AUX inputs, the ADC bypass and the DAC left and right channels to be combined as desired. This allows a mono mix of the DAC channels to be performed as well as mixing in external line-in from the AUX or speech from the input bypass path. The AUX and bypass inputs have individual volume control from -15dB to +6dB and the DAC volume can be adjusted in the digital domain if required. The output of these mixers is connected to the headphone outputs (LOUT1, ROUT1, LOUT2 and ROUT2) and can optionally be connected to the OUT3 and OUT4 mixers. Figure 23 Left/Right Output Channel Mixers

w PP Rev 1.1 August 2005 REGISTER ADDRESS BIT LABEL DEFAULT Left bypass path (from the Left channel input PGA stage) to right output mixer 0 = not selected 1 = selected R43 Output mixer control BYPR2LMIX Right bypass path (from the right channel input PGA stage) to Left output mixer 0 = not selected 1 = selected DACR2LMIX Right DAC output to left output mixer 0 = not selected 1 = selected R49 Output mixer control DACL2RMIX Left DAC output to right output mixer 0 = not selected 1 = selected DACL2LMIX Left DAC output to left output mixer 0 = not selected 1 = selected BYPL2LMIX Left bypass path (from the left channel input PGA stage) to left output mixer 0 = not selected 1 = selected 4:2 BYPLMIXVOL 000 Left bypass volume contol to output channel mixer: 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB AUXL2LMIX Left Auxilliary input to left channel output mixer: 0 = not selected 1 = selected R50 Left channel output mixer control 8:6 AUXLMIXVOL 000 Aux left channel input to left mixer volume control: 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB

w PP Rev 1.1 August 2005 DACR2RMIX Right DAC output to right output mixer 0 = not selected 1 = selected BYPR2RMIX Right bypass path (from the right channel input PGA stage) to right output mixer 0 = not selected 1 = selected 4:2 BYPRMIXVOL 000 Right bypass volume control to output channel mixer: 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB AUXR2RMIX Right Auxiliary input to right channel output mixer: 0 = not selected 1 = selected R51 Right channel output mixer control 8:6 AUXRMIXVOL 000 Aux right channel input to right mixer volume control: 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB LMIXEN Left output channel mixer enable: 0 = disabled 1 = enabled Power management RMIXEN Right output channel mixer enable: 0 = disabled 1 = enabled Table 31 Left and Right Output Mixer Control

w PP Rev 1.1 August 2005 HEADPHONE OUTPUTS (LOUT1 AND ROUT1) The headphone outputs LOUT1 and ROUT1 can drive a 16Ω or 32Ω headphone load, either through DC blocking capacitors, or DC-coupled to a buffered midrail reference as shown in Figure 24. OUT3, OUT4, LOUT2 or ROUT2 could be used as this buffered reference if one of these outputs is not being used, saving decoupling capacitors, at the expense of increased power consumption. For fully independent left and right channels, two separate midrail references can be used, eliminating crosstalk caused by headphone ground impedances, at the expense of increased power consumption. Headphone Output using DC Blocking Capacitors: Lowest power consumption (Two outputs enabled); Large and expensive capacitors; Bass response may be reduced for smaller capacitors; Impedance in common ground may introduce crosstalk. DC Coupled Headphone Output: Higher power consumption (Three outputs enabled); Improved PSRR if AVDD2 connected to AVDD1; Impedance in common ground may introduce crosstalk; Improved bass response (DC connection). DC Coupled with Fully Independent Left / Right Drive: Highest power consumption (Four outputs enabled); Improved PSRR if AVDD2 connected to AVDD1; Independent L/R pseudo-ground eliminates crosstalk; Improved bass response (DC connection); Non-standard headphone connection may not be suitable for some applications. Figure 24 Recommended Headphone Output Configurations Each headphone output has an analogue volume control PGA with a gain range of -57dB to +6dB. When DC blocking capacitors are used, their capacitance and the load resistance together determine the lower cut-off frequency of the output signal, fc. Increasing the capacitance lowers fc, improving the bass response. Smaller capacitance values will diminish the bass response. Assuming a 16Ω load and C1, C2 = 220µF: fc = 1 / 2π RLC1 = 1 / (2π x 16Ω x 220µF) = 45 Hz In the DC coupled configuration, the headphone “ground” is connected to the VMID pin. The OUT3/4 pins can be configured as a DC output driver by setting the OUT3MUTE and OUT4MUTE register bit. The DC voltage on VMID in this configuration is equal to the DC offset on the LOUT1 and ROUT1 pins therefore no DC blocking capacitors are required. This saves space and material cost in portable applications. Note that LOUT2, ROUT2, OUT3 and OUT4 have an optional output boost of 1.5x. When these are configured in this output boost mode (SPKBOOST/OUT3BOOST/OUT4BOOST=1) then the VMID value of these outputs will be equal to 1.5xAVDD/2 and will not match the VMID of the headphone drivers. Do not use the DC coupled output mode in this configuration. It is recommended to connect the DC coupled outputs only to headphones, and not to the line input of another device. Although the built-in short circuit protection will prevent any damage to the headphone outputs, such a connection may be noisy, and may not function properly if the other device is grounded.

w PP Rev 1.1 August 2005 REGISTER ADDRESS BIT LABEL DEFAULT Headphone volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately LOUT1MUTE Left headphone output mute: 0 = Normal operation 1 = Mute 5:0 LOUT1VOL 111001 Left headphone output volume: 000000 = -57dB 000001 = -56dB ... 111001 = 0dB ... 111111 = +6dB R52 LOUT1 Volume control HPVU Not latched LOUT1 and ROUT1 volumes do not update until a 1 is written to OUT1VU (in reg 52 or 53) ROUT1ZC Headphone volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately ROUT1MUTE Right headphone output mute: 0 = Normal operation 1 = Mute 5:0 ROUT1VOL 111001 Right headphone output volume: 000000 = -57dB 000001 = -56dB 111001 = 0dB ... 111111 = +6dB R53 ROUT1 Volume control HPVU Not latched LOUT1 and ROUT1 volumes do not update until a 1 is written to OUT1VU (in reg 52 or 53) Table 32 OUT1 Volume Control SPEAKER OUTPUTS (LOUT2 AND ROUT2) The outputs LOUT2 and ROUT2 are designed to drive an 8Ω BTL speaker but can optionally drive two headphone loads of 16Ω/32Ω or a line output (see Headphone Output and Line Output sections, respectively). Each output has an individual volume control PGA, an output boost/level shift bit, a mute and an enable as shown in Figure 25. LOUT2 and ROUT2 output the left and right channel mixer outputs respectively. The ROUT2 signal path also has an optional invert. The amplifier used for this invert can be used to mix in the AUXR signal with an adjustable gain range of -15dB -> +6dB. This allows a ‘beep’ signal to be applied only to the speaker output without affecting the HP or line outputs.

w PP Rev 1.1 August 2005 Figure 25 Speaker Outputs LOUT2 and ROUT2

w PP Rev 1.1 August 2005 REGISTER ADDRESS BIT LABEL DEFAULT LOUT2 volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately LOUT2MUTE Left output mute: 0 = Normal operation 1 = Mute 5:0 LOUT2VOL 111001 Left output volume: 000000 = -57dB 000001 = -56dB ... 111001 = 0dB ... 111111 = +6dB R54 LOUT2 Volume control SPKVU Not latched LOUT2 and ROUT2 volumes do not update until a 1 is written to OUT2VU (in reg 54 or 55) ROUT2ZC ROUT2 volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately ROUT2MUTE Right output mute: 0 = Normal operation 1 = Mute 5:0 ROUT2VOL 111001 Right output volume: 000000 = -57dB 000001 = -56dB ... 111001 = 0dB ... 111111 = +6dB R55 ROUT2 Volume control SPKVU Not latched LOUT2 and ROUT2 volumes do not update until a 1 is written to OUT2VU (in reg 54 or 55) Table 33 OUT2 Volume Control The signal output on LOUT2/ROUT2 comes from the Left/Right Mixer circuits and can be any combination of the DAC output, the Bypass path (output of the input boost stage) and the AUX input. The LOUT2/ROUT2 volume is controlled by the LOUT2VOL/ ROUT2VOL register bits. Gains over 0dB may cause clipping if the signal is large. The LOUT2MUTE/ ROUT2MUTE register bits cause the speaker outputs to be muted (the output DC level is driven out). The output pins remain at the same DC level (DCOP), so that no click noise is produced when muting or un-muting The speaker output stages also have a selectable gain boost of 1.5x (3.52dB). When this boost is enabled the output DC level is also level shifted (from AVDD1/2 to 1.5xAVDD1/2) to prevent the signal from clipping. A dedicated amplifier BUFDCOP, as shown in Figure 29, is used to perform the DC level shift operation. This buffer must be enabled using the BUFDCOPEN register bit for this operating mode. It should also be noted that if AVDD2 is not equal to or greater than 1.5xAVDD1 this boost mode may result in signals clipping. Table 35 summarises the effect of the SPKBOOST control bits.

w PP Rev 1.1 August 2005 REGISTER ADDRESS BIT LABEL DEFAULT 0 = speaker gain = -1; DC = AVDD1 / 2 1 = speaker gain = +1.5; DC = 1.5 x AVDD1 / 2 Power management BUFDCOPEN Dedicated buffer for DC level shifting output stages when in 1.5x gain boost configuration. 0 = Buffer disabled 1 = Buffer enabled (required for 1.5x gain boost) Table 34 Speaker Boost Stage Control SPKBOOST OUTPUT STAGE GAIN OUTPUT DC LEVEL OUTPUT STAGE CONFIGURATION 1x (0dB) AVDD1/2 Inverting 1.5x (3.52dB) 1.5xAVDD1/2 Non-inverting Table 35 Output Boost Stage Details REGISTER ADDRESS BIT LABEL DEFAULT Mute input to INVROUT2 mixer INVROUT2 Invert ROUT2 output 3:1 BEEPVOL 000 AUXR input to ROUT2 inverter gain 000 = -15dB 001 = -12dB 010 = -9dB 011 = -6dB 100 = -3dB 101 = 0dB 110 = +3dB 111 = +6dB R43 Beep control BEEPEN 0 = mute AUXR beep input 1 = enable AUXR beep input Table 36 AUXR – ROUT2 BEEP Mixer Function ZERO CROSS TIMEOUT A zero-cross timeout function is provided so that if zero cross is enabled on the input or output PGAs the gain will automatically update after a timeout period if a zero cross has not occurred. This is enabled by setting SLOWCLKEN. The timeout period is dependent on the clock input to the digital and is equal to 221 * SYSCLK period. REGISTER ADDRESS BIT LABEL DEFAULT Slow clock enable. Used for both the jack insert detect debounce circuit and the zero cross timeout. 0 = slow clock disabled 1 = slow clock enabled Table 37 Timeout Clock Enable Control

w PP Rev 1.1 August 2005 OUT3/OUT4 MIXERS AND OUTPUT STAGES The OUT3/OUT4 pins provide an additional stereo line output, a mono output, or a pseudo ground connection for headphones. There is a dedicated analogue mixer for OUT3 and one for OUT4 as shown in Figure 30. The OUT3 and OUT4 output stages are powered from AVDD2 and AGND2. These individually- controllable outputs also incorporate an optional 1.5x boost and level shifting stage. Figure 30 OUT3 and OUT4 Mixers OUT3 can provide a midrail reference, a left line output, or a mono mix line output OUT4 can provide a midrail reference, a right line output, or a mono mix line output. A 6dB attenuation function is provided for OUT4, to prevent clipping during mixing of left and right signals. This function is enabled by the OUT4ATTN register bit.

w PP Rev 1.1 August 2005 REGISTER ADDRESS BIT LABEL DEFAULT 0 = Output stage outputs OUT3 mixer 1 = Output stage muted – drives out VMID. Can be used as VMID reference in this mode. OUT4_2OUT3 OUT4 mixer output to OUT3 0 = disabled 1 = enabled BYPL2OUT3 Left ADC input to OUT3 0 = disabled 1 = enabled LMIX2OUT3 Left DAC mixer to OUT3 0 = disabled 1= enabled R56 OUT3 mixer control LDAC2OUT3 Left DAC output to OUT3 0 = disabled 1 = enabled OUT3_2OUT4 OUT3 mixer output to OUT4 0 = disabled 1= enabled OUT4MUTE 0 = Output stage outputs OUT4 mixer 1 = Output stage muted – drives out VMID. Can be used as VMID reference in this mode. OUT4ATTN 0 = OUT4 normal output 1 = OUT4 attenuated by 6dB LMIX2OUT4 Left DAC mixer to OUT4 0 = disabled 1 = enabled LDAC2OUT4 Left DAC to OUT4 0 = disabled 1 = enabled BYPR2OUT4 Right ADC input to OUT4 0 = disabled 1 = enabled RMIX2OUT4 Right DAC mixer to OUT4 0 = disabled 1 = enabled R57 OUT4 mixer control RDAC2OUT4 Right DAC output to OUT4 0 = disabled 1 = enabled Table 38 OUT3/OUT4 Mixer Registers The OUT3 and OUT4 output stages each have a selectable gain boost of 1.5x (3.52dB). When this boost is enabled the output DC level is also level shifted (from AVDD1/2 to 1.5xAVDD1/2) to prevent the signal from clipping. A dedicated amplifier BUFDCOP, as shown in Figure 31, is used to perform the DC level shift operation. This buffer must be enabled using the BUFDCOPEN register bit for this operating mode. It should also be noted that if AVDD2 is not equal to or greater than 1.5xAVDD1 this boost mode may result in signals clipping. Table 35 summarises the effect of the OUT3BOOST and OUT4BOOST control bits.

w PP Rev 1.1 August 2005 Figure 32 Outputs OUT3 and OUT4 REGISTER ADDRESS BIT LABEL DEFAULT 0 = OUT3 output gain = -1; DC = AVDD1 / 2 1 = OUT3 output gain = +1.5 DC = 1.5 x AVDD1 / 2 R49 Output control OUT4BOOST 0 = OUT4 output gain = -1; DC = AVDD1 / 2 1 = OUT4 output gain = +1.5 DC = 1.5 x AVDD1 / 2 Power management BUFDCOPEN Dedicated buffer for DC level shifting output stages when in 1.5x gain boost configuration. 0=Buffer disabled 1=Buffer enabled (required for 1.5x gain boost) Table 39 OUT3 and OUT4 Boost Stages Control OUT3BOOST/ OUT4BOOST OUTPUT STAGE GAIN OUTPUT DC LEVEL OUTPUT STAGE CONFIGURATION AVDD1/2 Inverting 1.5x 1.5xAVDD1/2 Non-inverting Table 40 OUT3 and OUT4 Output Boost Stage Details

w PP Rev 1.1 August 2005 Table 41 shows the polarities of the outputs in various configurations. Unless otherwise stated, polarity is shown with respect to left DAC output in non-inverting mode. Note that only registers relating to the mixer paths are shown here (Mixer enables, volume settings, output enables etc are not shown). CONFIGURATION DACLPOL DACRPOL INVROUT2 SPKBOOST OUT3BOOST OUT4BOOST MIXER PATH REGISTERS DIFFERENT FROM DEFAULT OUT4 PHASE / MAG OUT3 PHASE / MAG LOUT1 PHASE / MAG ROUT1 PHASE / MAG LOUT2 PHASE / MAG ROUT2 PHASE / MAG Default: Stereo DAC playback to LOUT1/ROUT1, LOUT2/ROUT2 and OUT4/OUT3 180° 180° DACs inverted 180° 180° 180° 180° Stereo DAC playback to LOUT1/ROUT1 and LOUT2/ROUT2 and OUT4/OUT3 (Speaker boost enabled) 1.5 1.5 Stereo DAC playback to LOUT1/ROUT1 and LOUT2/ROUT2 and OUT4/OUT3 (OUT3 and OUT4 boost enabled) 180° 1.5 180° 1.5 180° 180° Stereo playback to OUT3/OUT4 (DACs input to OUT3/OUT4 mixers via left/right mixers) LDAC2OUT3=0 RDAC2OUT4=0 LMIX2OUT3=1 RMIX2OUT4=1 180° 180° 180° 180° Differential output of right bypass path via OUT3/OUT4 (Phase shown relative to right bypass) BYPR2OUT4=1 OUT4_2OUT3=1 180° X X X X Differential output of mono mix of DACs via LOUT2/ROUT2 (e.g. BTL speaker drive) 180° High power speaker drive 1.5 180° 1.5 Table 41 Relative Output Phases Note that differential output should not be set up by combining outputs in boost mode with outputs which are not in boost mode as this would cause a DC offset current on the outputs.

w PP Rev 1.1 August 2005 ENABLING THE OUTPUTS Each analogue output of the WM8983 can be independently enabled or disabled. The analogue mixer associated with each output has a separate enable bit. All outputs are disabled by default. To save power, unused parts of the WM8983 should remain disabled. Outputs can be enabled at any time, but it is not recommended to do so when BUFIO is disabled (BUFIOEN=0), as this may cause pop noise (see “Power Management” and “Applications Information” sections). REGISTER ADDRESS BIT LABEL DEFAULT Unused input/output bias buffer enable OUT3MIXEN OUT3 mixer enable OUT4MIXEN OUT4 mixer enable Power Management BUFDCOPEN Output stage 1.5xAVDD/2 driver enable ROUT1EN ROUT1 output enable LOUT1EN LOUT1 output enable Power Management SLEEP 0 = Normal device operation 1 = Supply current reduced in device standby mode LMIXEN Left mixer enable RMIXEN Right mixer enable ROUT2EN ROUT2 output enable LOUT2EN LOUT2 output enable OUT3EN OUT3 enable Power Management OUT4EN OUT4 enable DELEN 2nd enable bit for L/ROUT1 R42 Output ctrl1 OUT1DEL 2 stage enable for L/ROUT1 Note: All “Enable” bits are 1 = ON, 0 = OFF Table 42 Output Stages Power Management Control OUT1DEL and OUT2DEL enable lower pop noise power-up option. See start–up sequences. (in 2 stage enable method, normal enable bit is set, followed shortly later by the delayed enable DELEN) THERMAL SHUTDOWN To protect the WM8983 from overheating a thermal shutdown circuit is included. If the device temperature reaches approximately 1250C and the thermal shutdown circuit is enabled (TSDEN=1) the L/ROUT2 amplifiers will be disabled. The thermal shutdown may also be configured to generate an interrupt. See the GPIO and Interrupt Controller section for details. REGISTER ADDRESS BIT LABEL DEFAULT 0 : thermal shutdown disabled 1 : thermal shutdown enabled Table 43 Thermal Shutdown

w PP Rev 1.1 August 2005 L/ROUT2EN/ OUT3/4EN OUT3BOOST/ OUT4BOOST/ SPKBOOST VROI OUTPUT CONFIGURATION 1kΩ tie-off to AVDD1/2 30kΩ tie-off to AVDD1/2 1kΩ tie-off to 1.5xAVDD1/2 30kΩ tie-off to 1.5xAVDD1/2 X Output enabled (DC level=AVDD1/2) X Output enabled (DC level=1.5xAVDD1/2) Table 45 Unused Output Pin Bias Options DIGITAL AUDIO INTERFACES The audio interface has four pins: ADCDAT: ADC data output DACDAT: DAC data input LRC: Data Left/Right alignment clock BCLK: Bit clock, for synchronisation The clock signals BCLK, and LRC can be outputs when the WM8983 operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). Five different audio data formats are supported: Left justified Right justified I2S DSP mode early DSP mode late All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for timing information. MASTER AND SLAVE MODE OPERATION The WM8983 audio interface may be configured as either master or slave. As a master interface device the WM8983 generates BCLK and LRC and thus controls sequencing of the data transfer on ADCDAT and DACDAT. To set the device to master mode register bit MS should be set high. In slave mode (MS=0), the WM8983 responds with data to clocks it receives over the digital audio interfaces. AUDIO DATA FORMATS In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRC transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRC transition. Figure 35 Left Justified Audio Interface (assuming n-bit word length)

w PP Rev 1.1 August 2005 REGISTER ADDRESS BIT LABEL DEFAULT Selects between stereo and mono device operation: 0 = Stereo device operation 1 = Mono device operation. Data appears in ‘left’ phase of LRC. ADCLRSWAP Controls whether ADC data appears in ‘right’ or ‘left’ phases of LRC clock: 0=ADC left data appear in ‘left’ phase of LRC and right data in 'right' phase 1=ADC left data appear in ‘right’ phase of LRC and right data in 'left' phase DACLRSWAP Controls whether DAC data appears in ‘right’ or ‘left’ phases of LRC clock: 0=DAC left data appear in ‘left’ phase of LRC and right data in 'right' phase 1=DAC left data appear in ‘right’ phase of LRC and right data in 'left' phase 4:3 FMT Audio interface Data Format Select: 00=Right Justified 01=Left Justified 10=I2S format 11= DSP/PCM mode 6:5 WL Word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits (see note) LRP LRC clock polarity 0=normal 1=inverted Audio Interface Control BCP BCLK polarity 0=normal 1=inverted LOOPBACK Digital loopback function 0=No loopback 1=Loopback enabled, ADC data output is fed directly into DAC data input. Table 46 Audio Interface Control Note: Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected the device will operate in 24-bit mode. AUDIO INTERFACE CONTROL The register bits controlling audio format, word length and master / slave mode are summarised below. Register bit MS selects audio interface operation in master or slave mode. In Master mode BCLK and LRC are outputs. The frequencies of BCLK and LRC in master mode are controlled using MCLKDIV; these clocks are divided down versions of PLL output clock (SYSCLK). The MCLKDIV default setting provides a SYSCLK/256 division rate for the LRC output clock. It is possible to divide down the BCLK rate using BCLKDIV; care must be taken in choosing the correct BCLKDIV rate to maintain sufficient BCLK pulses per LRC period for the chosen data word length. The BCLKDIV default setting provides a BCLK = SYSCLK clock.

w PP Rev 1.1 August 2005 REGISTER ADDRESS BIT LABEL DEFAULT Sets the chip to be master over LRC and BCLK 0=BCLK and LRC clock are inputs (Slave mode) 1=BCLK and LRC clock are outputs generated by the WM8983 (Master mode) 4:2 BCLKDIV 000 Configures the BCLK and LRC output frequency, for use when the chip is in Master mode. 000=divide by 1 (BCLK=SYSCLK) 001=divide by 2 (BCLK=SYSCLK/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved 7:5 MCLKDIV 010 Sets the division for either the MCLK or PLL clock output (selected by CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 (LRC=SYSCLK/256) 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 Clock Generation Control CLKSEL Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output Table 47 Clock Control SAMPLE RATE (KHZ) SYSCLK (MHZ) (256FS CLOCK) MCLKDIV R6 [BIT 7:5] SR R7 [BIT3:1] 12.288 111 = divide by 12 010 11.025 11.2896 110 = divide by 8 100 12.288 110 = divide by 8 100 12.288 101 = divide by 6 011 22.05 11.2896 100 = divide by 4 010 12.288 100 = divide by 4 010 12.288 011 = divide by 3 001 44.1 11.2896 010 = divide by 2 000 12.288 010 = divide by 2 000 Table 48 Register Settings and Required SYSCLK for Common Sample Rates

w PP Rev 1.1 August 2005 LOOPBACK Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data from the ADC audio interface is fed directly into the DAC data input. COMPANDING The WM8983 supports A-law and µ-law companding on both transmit (ADC) and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively. REGISTER ADDRESS BIT LABEL DEFAULT 2:1 ADC_COMP ADC companding 00 = off 01 = reserved 10 = µ-law 11 = A-law 4:3 DAC_COMP DAC companding 00 = off 01 = reserved 10 = µ-law 11 = A-law Companding Control WL8 0 = off 1 = device operates in 8-bit mode. Table 49 Companding Control Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: µ-law (where µ=255 for the U.S. and Japan): F(x) = ln( 1 + µ|x|) / ln( 1 + µ) -1 x 1 law (where A=87.6 for Europe): F(x) = A|x| / ( 1 + lnA) } for x 1/A F(x) = ( 1 + lnA|x|) / (1 + lnA) } for 1/A x 1 The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted for µ-law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSB’s of data. Companding converts 13 bits (µ-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The input data range is separated into 8 levels, allowing low amplitude signals better precision than that of high amplitude signals. This is to exploit the operation of the human auditory system, where louder sounds do not require as much resolution as quieter sounds. The companded signal is an 8- bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits). Setting the WL8 register bit allows the device to operate with 8-bit data. In this mode it is possible to use 8 BCLK’s per LRC frame. When using DSP mode B, this allows 8-bit data words to be output consecutively every 8 BCLK’s and can be used with 8-bit data words using the A-law and u-law companding functions. BIT8 BIT[7:4] BIT[3:0] SIGN EXPONENT MANTISSA Table 50 8-bit Companded Word Composition

w PP Rev 1.1 August 2005 AUDIO SAMPLE RATES The WM8983 filter characteristics for the ADCs and the DACs are set using the SR register bits; these bits do not change the rate of the audio interface output clocks in Master mode. The cut-offs for the digital filters and the ALC attack/decay times stated are determined using these values and assume a 256fs master clock rate. If a sample rate is required which is not explicitly supported by the SR register settings, then the closest SR value to that sample rate should be chosen, the filter characteristics and the ALC attack, decay and hold times will scale appropriately. REGISTER ADDRESS BIT LABEL DEFAULT 3:1 SR 000 Approximate sample rate (configures the coefficients for the internal digital filters): 000 = 48kHz 001 = 32kHz 010 = 24kHz 011 = 16kHz 100 = 12kHz 101 = 8kHz 110-111 = reserved Table 51 Sample Rate Control MASTER CLOCK AND PHASE LOCKED LOOP (PLL) The WM8983 has an on-chip phase-locked loop (PLL) circuit that can be used to: Generate master clocks for the WM8983 audio functions from another external clock, e.g. in telecoms applications. Generate and output (on pin CSB/GPIO1) a clock for another part of the system that is derived from an existing audio master clock. Figure 44 shows the PLL and internal clocking on the WM8983. The PLL can be enabled or disabled by the PLLEN register bit. REGISTER ADDRESS BIT LABEL DEFAULT 0 = PLL off 1 = PLL on Table 52 PLLEN Control Bit

w PP Rev 1.1 August 2005 Figure 44 PLL and Clock Select Circuit The PLL frequency ratio R = f2/f1 (see Figure 44) can be set using the register bits PLLK and PLLN. R should be chosen to ensure 5 < PLLN < 13: PLLN = int R PLLK = int (224 (R-PLLN)) To calculate R: There is a fixed divide by 4 in the PLL, f/4, and a selectable divide by N after the PLL, MCLKDIV. f2 = SYSCLK x 4 x MCLKDIV R = f2 / (MCLK / PRESCALE) = R PLLN = int R k = int ( 224 x (R – intR)) – convert k to hex for PLLK EXAMPLE: MCLK=26MHz, required clock = 12.288MHz. R should be chosen to ensure 5 < PLLN < 13. MCLKDIV = 2 sets the required division rate; SYSCLK/256. f2 = 4 x 2 x 12.288MHz = 98.304MHz. PLLN = int R = 7 k = int ( 224 x (7.561846 – 7)) = 9426214dec Convert k to hex: PLLK = 8FD526h Convert PLLK to R36, R37, R38 and R39 hex values: R36 = 7h; R37 = 23h; R38 = 1EAh; R39 = 126h

w PP Rev 1.1 August 2005 REGISTER ADDRESS BIT LABEL DEFAULT Divide MCLK by 2 before input to PLL R36 PLL N value 3:0 PLLN 1000 Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. R37 PLL K value 5:0 PLLK [23:18] 0Ch R38 PLL K Value 8:0 PLLK [17:9] 093h R39 PLL K Value 8:0 PLLK [8:0] 0E9h Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Table 53 PLL Frequency Ratio Control The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings are shown in Table 54. MCLK (MHz) (F1) DESIRED OUTPUT (MHz) (MHz) PRESCALE DIVIDE MCLKDIV R PLLN R36 (Hex) K (Hex) PLLK [23:18] R37 (Hex) PLLK [17:9] R38 (Hex) PLLK [8:0] R39 (Hex) 11.29 90.3168 7.5264 86C226 161 12.288 98.304 8.192 3126E8 C 11.29 90.3168 6.947446 F28BD4 145 1D4 12.288 98.304 7.561846 8FD525 1EA 126 14.4 11.29 90.3168 6.272 45A1CA 1CA 14.4 12.288 98.304 6.826667 D3A06E 1D0 19.2 11.29 90.3168 9.408 6872AF 19.2 12.288 98.304 10.24 A 3D70A3 F 19.68 11.29 90.3168 9.178537 2DB492 B DA 19.68 12.288 98.304 9.990243 FD809F 19.8 11.29 90.3168 9.122909 1F76F7 1BB 19.8 12.288 98.304 9.929697 EE009E 100 11.29 90.3168 7.5264 86C226 161 12.288 98.304 8.192 3126E8 C 11.29 90.3168 6.947446 F28BD4 145 1D4 12.288 98.304 7.561846 8FD525 1EA 126 11.29 90.3168 6.690133 BOAC93 12.288 98.304 7.281778 482296 Table 54 PLL Frequency Examples for Common MCLK Rates

w PP Rev 1.1 August 2005 GENERAL PURPOSE INPUT/OUTPUT The WM8983 has three dual purpose input/output pins. CSB/GPIO1: CSB / GPIO1 pin L2/GPIO2: Left channel line input / headphone detection input R2/GPIO3: Right channel line input / headphone detection input The GPIO2 and GPIO3 functions are provided for use as jack detection inputs. The GPIO1 and GPIO2 functions are provided for use as jack detection inputs or general purpose outputs. The default configuration for the CSB/GPIO1 is to be an input. When setup as an input, the CSB/GPIO1 pin can either be used as CSB or for jack detection, depending on how the MODE pin is set. Table 55 illustrates the functionality of the GPIO1 pin when used as a general purpose output. REGISTER ADDRESS BIT LABEL DEFAULT 2:0 GPIO1SEL 000 CSB/GPIO1 pin function select: 000= input (CSB/jack detection: depending on MODE setting) 001 = reserved 010 = Temp ok 011 = Amute active 100 = PLL clk output 101 = PLL lock 110 = logic 0 111 = logic 1 GPIO1POL GPIO1 Polarity invert 0 = Non inverted 1 = Inverted GPIO Control 5:4 OPCLKDIV PLL Output clock division ratio 00 = divide by 1 01 = divide by 2 10 = divide by 3 11 = divide by 4 Table 55 CSB/GPIO Control Note: If MODE is set to 3 wire mode, CSB/GPIO1 is used as CSB input irrespective of the GPIO1SEL[2:0] bits. For further details of the jack detect operation see the OUTPUT SWITCHING section. OUTPUT SWITCHING (JACK DETECT) When the device is operated using a 2-wire interface the CSB/GPIO1 pin can be used as a switch control input to automatically disable one set of outputs and enable another. The L2/GPIO2 and R2/GPIO3 pins can also be used for this purpose. The GPIO pins have an internal de-bounce circuit when in this mode in order to prevent the output enables from toggling multiple times due to input glitches. This de-bounce circuit is clocked from a slow clock with period 221 x MCLK. Note that the GPIOPOL bit is not relevant for jack detection, it is the signal detected at the pin which is used. The switching on/off of the outputs is fully configurable by the user. Each output, OUT1, OUT2, OUT3 and OUT4 has 2 associated enables. OUT1_EN_0, OUT2_EN_0, OUT3_EN_0 and OUT4_EN_0 are the output enable signals which are used if the selected jack detection pin is at logic 0 (after de-bounce). OUT1_EN_1, OUT2_EN_1, OUT3_EN_1 and OUT4_EN_1 are the output enable signals which are used if the selected jack detection pin is at logic 1 (after de-bounce).

w PP Rev 1.1 August 2005 Similar to the output enables, VMID can be output to OUT3. This VMID output can be configured to be on/off depending on the jack detection input polarity of VMID_EN_0 and VMID_EN_1. The jack detection enables operate as follows: All OUT_EN signals have an AND function performed with their normal enable signals (in Table 42). When an output is normally enabled at per Table 42, the selected jack detection enable (controlled by selected jack detection pin polarity) is set 0, it will turn the output off. If the normal enable signal is already OFF (0), the jack detection signal will have no effect due to the AND function. During jack detection if the user desires an output to be un-changed whether the jack is in or not, both the JD_EN settings i.e. JD_EN0 and JD_EN1, should be set to 0000. The VMID_EN signal has an OR function performed with the normal VMID driver enable. If the VMID_EN signal is to have no effect to normal functionality when jack detection is enabled, it should set to 0 for all JD_EN0 or JD_EN1 settings. If jack detection is not enabled (JD_EN=0), the output enables default to all 1’s, allowing the outputs to be controlled as normal via the normal output enables found in Table 42. Similarly the VMID_EN signal defaults to 0 allowing the VMID driver to be controlled via the normal enable bit. REGISTER ADDRESS BIT LABEL DEFAULT 5:4 JD_SEL Pin selected as jack detection input 00 = GPIO1 01 = GPIO2 10 = GPIO3 11 = Reserved JD_EN Jack Detection Enable 0 = disabled 1 = enabled GPIO control 8:7 JD_VMID [7] VMID_EN_0 [8] VMID_EN_1 3:0 JD_EN0 0000 Output enables when selected jack detection input is logic 0. 0000 = OUT1_EN_0 0001 = OUT2_EN_0 0010 = OUT3_EN_0 0011 = OUT4_EN_0 0100-1111 = Reserved R13 7:4 JD_EN1 0000 Output enables when selected jack detection input is logic 1 0000-0011 = Reserved 0100 = OUT1_EN_1 0101 = OUT2_EN_1 0110 = OUT3_EN_1 0111 = OUT4_EN_1 1000-1111 = Reserved Table 56 Jack Detect Register Control Bits

w PP Rev 1.1 August 2005 In 2-wire mode the WM8983 has a fixed device address, 0011010. RESETTING THE CHIP The WM8983 can be reset by performing a write of any value to the software reset register (address 0h). This will cause all register values to be reset to their default values. In addition to this there is a Power-On Reset (POR) circuit which ensures that the registers are initially set to default when the device is powered up. POWER SUPPLIES The WM8983 requires four separate power supplies: AVDD1 and AGND1: Analogue supply, powers all internal analogue functions and output drivers LOUT1 and ROUT1. AVDD1 must be between 2.5V and 3.6V and has the most significant impact on overall power consumption (except for power consumed in the headphones). Higher AVDD1 will improve audio quality. AVDD2 and AGND2: Output driver supplies, power LOUT2, ROUT2, OUT3 and OUT4. AVDD2 must be between 2.5V and 5.5V. AVDD2 can be tied to AVDD1, but it requires separate layout and decoupling capacitors to curb harmonic distortion. DCVDD: Digital core supply, powers all digital functions except the audio and control interfaces. DCVDD must be between 1.71V and 3.6V, and has no effect on audio quality. The return path for DCVDD is DGND, which is shared with DBVDD. DBVDD must be between 1.71V and 3.6V. DBVDD return path is through DGND. It is possible to use the same supply voltage for all four supplies. However, digital and analogue supplies should be routed and decoupled separately on the PCB to keep digital switching noise out of the analogue signal paths. POWER MANAGEMENT SAVING POWER BY REDUCING OVERSAMPLING RATE The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode. Under the control of ADCOSR128 and DACOSR128 the oversampling rate may be doubled. 64x oversampling results in a slight decrease in noise performance compared to 128x but lowers the power consumption of the device. REGISTER ADDRESS BIT LABEL DEFAULT DAC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) R14 ADC control ADCOSR128 ADC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) Table 58 ADC and DAC Oversampling Rate Selection VMID The analogue cicruitry will not operate unless VMID is enabled. The impedance of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the startup time of the VMID circuit. REGISTER ADDRESS BIT LABEL DEFAULT 1:0 VMIDSEL Reference string impedance to VMID pin (Determines startup time): 00 = off (250kΩ VMID to AGND1) 01 = 100kΩ total, 25kΩ impedance 10 = 500kΩ total, 125kΩ impedance 11 = 10kΩ total, 2.5kΩ impedance Table 59 VMID Impedance Control

w PP Rev 1.1 August 2005 BIASEN The analogue amplifiers will not operate unless BIASEN is enabled. REGISTER ADDRESS BIT LABEL DEFAULT Analogue amplifier bias control 0 = disabled 1 = enabled Table 60 Analogue Bias Control BIAS CONTROL Control of the analog bias values is possible using register 61 and 62 REGISTER ADDRESS BIT LABEL DEFAULT 0 = normal 1 = 0.5x HALF_ IPGA Input bias control 0 = normal 1 = 0.5x 4,3 BUFBIAS ADC input buffer bias 00 = 1.5x 01 = 1.0x 10 = 1.0x 11 = 0.5x 2,1 ADCBIAS ADC input buffer bias 00 = 1.5x 01 = 1.0x 10 = 1.0x 11 = 0.5x R61 Bias control HALFOP BIAS Output bias 0 = normal 1 = 0.5x R62 HALF DACI DAC bias 0 = normal 1 = 0.5x Table 61 Analogue Bias Control Note that these bits must be used with care and may cause degradation in analog performance. For example, if both BIASCUT and HALFDACI are used at same time, the playback THD will be poor.

w PP Rev 1.1 August 2005 REGISTER MAP ADDR B[15:9] DEF’T VAL D E C H E X REGISTER NAME (HEX) Software Reset Software reset Power manage’t BUFDC OPEN OUT4 MIXEN OUT3 MIXEN PLLEN MICBEN BIASEN BUFIO EN VMIDSEL 000 Power manage’t ROUT1 EN LOUT1 EN SLEEP BOOST ENR BOOST ENL INPGA ENR INPPGA ENL ADC ENR ADC ENL 000 Power manage’t OUT4EN OUT3EN LOUT2 EN ROUT2 EN RMIXEN LMIXEN DAC ENR DAC ENL 000 Audio Interface BCP LRP WL FMT DLR SWAP ALR SWAP MONO 050 Companding ctrl WL8 DAC_COMP ADC_COMP LOOP BACK 000 Clock Gen ctrl CLKSEL MCLKDIV BCLKDIV MS 140 Additional ctrl SR SLOWC LK EN 000 GPIO Stuff OPCLKDIV GPIO1P OL GPIO1SEL[2:0] 000 Jack detect control JD_VMID JD_VMI JD_EN JD_SEL 000 DAC Control SOFT MUTE DAC OSR128 AMUTE DACR POL DACL POL 000 Left DAC digital Vol DACVU DACLVOL 0FF Right DAC dig’l Vol DACVU DACRVOL 0FF Jack Detect Control JD_EN1 JD_EN0 000 ADC Control HPFEN HPFAPP HPFCUT ADC OSR128 ADCR POL ADC LPOL 100 Left ADC Digital Vol ADCVU ADCLVOL 0FF Right ADC Digital Vol ADCVU ADCRVOL 0FF EQ1 – low shelf EQ3D MODE EQ1C EQ1G 12C EQ2 – peak 1 EQ2BW EQ2C EQ2G 02C EQ3 – peak 2 EQ3BW EQ3C EQ3G 02C EQ4 – peak 3 EQ4BW EQ4C EQ4G 02C EQ5 – high shelf EQ5C EQ5G 02C DAC Limiter 1 LIMEN LIMDCY LIMATK 032 DAC Limiter 2 LIMLVL LIMBOOST 000 Notch Filter 1 NFU NFEN NFA0[13:7] 000 Notch Filter 2 NFU NFA0[6:0] 000 Notch Filter 3 NFU NFA1[13:7] 000 Notch Filter 4 NFU NFA1[6:0] 000 ALC control 1 ALCSEL ALCMAX ALCMIN 038 ALC control 2 ALCZC ALCHLD ALCLVL 00B ALC control 3 ALC MODE ALCDCY ALCATK 032

w PP Rev 1.1 August 2005 ADDR B[15:9] DEF’T VAL D E C H E X REGISTER NAME (HEX) Noise Gate NGEN NGTH 000 PLL N PLLPRE SCALE PLLN[3:0] 008 PLL K 1 PLLK[23:18] 00C PLL K 2 PLLK[17:9] 093 PLL K 3 PLLK[8:0] 0E9 3D control DEPTH3D 000 OUT4 to ADC OUT4_2ADCVOL OUT4_2 LNR POB CTRL DELEN OUT1 DEL Beep control BYPL2 RMIX BYPR2 LMIX 000 Input ctrl MICBV SEL R2_2 INPPGA RIN2 INPPGA RIP2 INPPGA L2_2 INPPGA LIN2 INPPGA LIP2 INPPGA 003 Left INP PGA gain ctrl INPGAVU INPPGA ZCL INPPGA MUTEL INPPGAVOLL 010 Right INP PGA gain ctrl INPGAVU INPPGA ZCR INPPGA MUTER INPPGAVOLR 010 Left ADC Boost ctrl PGA BOOSTL L2_2BOOSTVOL AUXL2BOOSTVOL 100 Right ADC Boost ctrl PGA BOOSTR R2_2BOOSTVOL AUXR2BOOSTVOL 100 Output ctrl DACL2 RMIX DACR2 LMIX OUT4 BOOST OUT3 BOOST SPK BOOST TSDEN VROI 002 Left mixer ctrl AUXLMIXVOL AUXL2 LMIX BYPLMIXVOL BYPL2 LMIX DACL2 LMIX 001 Right mixer ctrl AUXRMIXVOL AUXR2 RMIX BYPRMIXVOL BYPR2 RMIX DACR2 RMIX 001 LOUT1 (HP) volume ctrl OUT1VU LOUT1 ZC LOUT1 MUTE LOUT1VOL 039 ROUT1 (HP) volume ctrl OUT1VU ROUT1 ZC ROUT1 MUTE ROUT1VOL 039 LOUT2 (SPK) volume ctrl OUT2VU LOUT2 ZC LOUT2 MUTE LOUT2VOL 039 ROUT2 (SPK) volume ctrl OUT2VU ROUT2 ZC ROUT2 MUTE ROUT2VOL 039 OUT3 mixer ctrl OUT3 MUTE OUT4_ 2OUT3 BYPL2 OUT3 LMIX2 OUT3 LDAC2 OUT3 001 OUT4 (MONO) mixer ctrl OUT3_2 OUT4 OUT4 MUTE OUT4 ATTN LMIX2 OUT4 LDAC2 OUT4 BYPR2 OUT4 RMIX2 OUT4 RDAC2 OUT4 001 Bias Control BIASCUT HALF I_IPGA BUFBIAS[1:0] ADCBIAS[1:0] HALF OPBIAS 000 Table 62 WM8983 Register Map

w PP Rev 1.1 August 2005 DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC Filter +/- 0.025dB 0.454fs Passband -6dB 0.5fs Passband Ripple +/- 0.025 dB Stopband 0.546fs Stopband Attenuation f > 0.546fs -60 dB Group Delay 21/fs ADC High Pass Filter -3dB 3.7 -0.5dB 10.4 High Pass Filter Corner Frequency -0.1dB 21.6 Hz DAC Filter +/- 0.035dB 0.454fs Passband -6dB 0.5fs Passband Ripple +/-0.035 dB Stopband 0.546fs Stopband Attenuation f > 0.546fs -80 dB Group Delay 29/fs Table 63 Digital Filter Characteristics TERMINOLOGY Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band) Pass-band Ripple – any variation of the frequency response in the pass-band region

w PP Rev 1.1 August 2005 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 69 External Component Diagram

w PP Rev 1.1 August 2005 PACKAGE DIAGRAM DM030.E FL: 32 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.9 mm BODY, 0.50 mm LEAD PITCH NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. DIMENSION L1 REPRESENTS TERMINAL PULL BACK FROM PACKAGE SIDE WALL. MAXIMUM OF 0.1mm IS ACCEPTABLE. WHERE TERMINAL PULL BACK EXISTS, ONLY UPPER HALF OF LEAD IS VISIBLE ON PACKAGE SIDE WALL DUE TO HALF ETCHING OF LEADFRAME. 2. FALLS WITHIN JEDEC, MO-220 WITH THE EXCEPTION OF D2, E2: D2,E2: LARGER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION 3. ALL DIMENSIONS ARE IN MILLIMETRES 4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 5. SHAPE AND SIZE OF CORNER TIE BAR MAY VARY WITH PACKAGE TERMINAL COUNT. CORNER TIE BAR IS CONNECTED TO EXPOSED PAD INTERNALLY. 6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING. SEE DETAIL B E2/2 b B A e CORNER TIE BAR B L D2/2 SEE DETAIL A INDEX AREA (D/2 X E/2) TOP VIEW D C aaa 2 X C aaa 2 X E DETAIL B TERMINAL TIP R DATUM e e/2 DETAIL A B C bbb M A 32x b L 32x K R 0.566 mm 0.43 mm CORNER TIE BAR Symbols Dimensions (mm) MIN NOM MAX NOTE A b D E e L R 0.85 0.90 1.00 0.05 0.02

0.2 REF

0.30 0.23 0.18 5.00 3.4 3.3 3.2

0.5 BSC

0.35 0.4 0.45 0.1 b(min)/2 K 0.20 aaa bbb ccc REF: 0.15 0.10 0.10 JEDEC, MO-220, VARIATION VHHD-2 Tolerances of Form and Position 4.90 5.10 5.00 4.90 5.10 3.4 3.3 3.2 EXPOSED GROUND PADDLE EXPOSED GROUND PADDLE BOTTOM VIEW C 0.08 C ccc A C (A3) SEATING PLANE SIDE VIEW

w PP Rev 1.1 August 2005 IMPORTANT NOTICE Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s approval, license, warranty or endorsement thereof. Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. ADDRESS: Wolfson Microelectronics plc Westfield House

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