WM8971LGEFL

WM8971L WOLFSON | Alldatasheet

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w WM8971L Stereo CODEC for Portable Audio Applications WOLFSON MICROELECTRONICS plc www.wolfsonmicro.com Advanced Information, March 2004, Rev 3.0 Copyright 2004 Wolfson Microelectronics plc

DESCRIPTION

The WM8971L is a low power, high quality stereo codec designed for portable digital audio applications. The device integrates complete interfaces to stereo or mono microphones and a stereo headphone. External component requirements are drastically reduced as no separate microphone or headphone amplifiers are required. Advanced on-chip digital signal processing performs graphic equaliser, and automatic level control for the microphone or line input. The WM8971L can operate as a master or a slave, with various master clock frequencies including 12 or 24MHz for USB devices, or standard 256fs rates like 12.288MHz and 24.576MHz. Different audio sample rates such as 96kHz, 48kHz, 44.1kHz are generated directly from the master clock without the need for an external PLL. The WM8971L operates at supply voltages down to 1.8V, although the digital core can operate at voltages down to 1.42V to save power, and the maximum for all supplies is 3.6 Volts. Different sections of the chip can also be powered down under software control. The WM8971L is supplied in a very small and thin 5x5mm QFN package, ideal for use in hand-held and portable systems.

FEATURES

DAC SNR 98dB (‘A’ weighted), THD –84dB at 48kHz, 3.3V ADC SNR 95dB (‘A’ weighted), THD -82dB at 48kHz, 3.3V Complete Stereo / Mono Microphone Interface Programmable ALC / Noise Gate On-chip 400mW BTL Speaker Driver (mono) On-chip Headphone Driver >40mW output power on 16Ω / 3.3V THD –80dB at 20mW, SNR 90dB with 16Ω load No DC blocking capacitors required (capless mode) Separately mixed mono output Digital Graphic Equaliser Low Power 7mW stereo playback (1.8V / 1.5V supplies) 14mW record and playback (1.8V / 1.5V supplies) Low Supply Voltages Analogue 1.8V to 3.6V Digital core: 1.42V to 3.6V Digital I/O: 1.8V to 3.6V 256fs / 384fs or USB master clock rates: 12MHz, 24MHz Audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48, 88.2, 96kHz generated internally from master clock 5x5x0.9mm QFN package

APPLICATIONS

Minidisc Player / Recorders Portable Digital Music Systems BLOCK DIAGRAM CSB SDIN SCLK MODE VREF AVDD AGND VMID ADCDAT ADCLRC BCLK MCLK DACDAT DACLRC HPDETECT

w AI Rev 3.0 March 2004 TABLE OF CONTENTS

w AI Rev 3.0 March 2004

w AI Rev 3.0 March 2004 PIN CONFIGURATION

ORDERING INFORMATION

-25°C to +85°C 32-pin QFN (5x5x0.9mm) MSL1 260°C WM8971LEFL/R -25°C to +85°C 32-pin QFN (5x5x0.9mm) (tape and reel) MSL1 260°C WM8971LGEFL -25°C to +85°C 32-pin QFN (5x5x0.9mm) (lead free) MSL1 260°C WM8971LGEFL/R -25°C to +85°C 32-pin QFN (5x5x0.9mm) (lead free, tape and reel) MSL1 260°C Note: Reel quantity = 3500

w AI Rev 3.0 March 2004 PIN DESCRIPTION PIN NO NAME TYPE Digital Buffer (I/O) Supply DGND Supply Digital Ground (return path for both DCVDD and DBVDD) BCLK Digital Input / Output Audio Interface Bit Clock DACDAT Digital Input DAC Digital Audio Data DACLRC Digital Input / Output Audio Interface Left / Right Clock/Clock Out ADCDAT Digital Output ADC Digital Audio Data ADCLRC Digital Input / Output Audio Interface Left / Right Clock MONOOUT Analogue Output Mono Output NC No Connect No Connect ROUT1 Analogue Output Right Output 1 (Line or Headphone) LOUT1 Analogue Output Left Output 1 (Line or Headphone) HPGND Supply Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2) ROUT2 Analogue Output Right Output 1 (Line or Headphone or Speaker) LOUT2 Analogue Output Left Output 1 (Line or Headphone or Speaker) HPVDD Supply Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2, MONOUT) AVDD Supply Analogue Supply AGND Supply Analogue Ground (return path for both AVDD and MVDD) VREF Analogue Output Reference Voltage Decoupling Capacitor VMID Analogue Output Midrail Voltage Decoupling Capacitor MICBIAS Analogue Output Microphone Bias HPDETECT Analogue Input Headphone Plug-in Detection NC No Connect No Connect MIC Analogue Input Single Ended Microphone Input NC No Connect No Connect RINPUT1 Analogue Input Right Channel Input 1 LINPUT1 Analogue Input Left Channel Input 1 MODE Digital Input Control Interface Selection CSB Digital Input Chip Select / Device Address Selection SDIN Digital Input/Output Control Interface Data Input / 2-wire Acknowledge output SCLK Digital Input Control Interface Clock Input

w AI Rev 3.0 March 2004 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION MIN MAX Supply voltages -0.3V +3.63V Voltage range digital inputs DGND -0.3V DBVDD +0.3V Voltage range analogue inputs AGND -0.3V AVDD +0.3V Operating temperature range, TA -25°C +85°C Storage temperature after soldering -65°C +150°C Notes Analogue and digital grounds must always be within 0.3V of each other. All digital and analogue supplies are completely independent from each other. DCVDD must be less than or equal to AVDD and DBVDD. RECOMMENDED OPERATION CONDITIONS PARAMETER SYMBOL MIN TYP MAX UNIT Digital supply range (Core) DCVDD 1.42 2.0 3.6 V Digital supply range (Buffer) DBVDD 1.8 2.0 3.6 V Analogue supplies range AVDD, HPVDD 1.8 2.0 3.6 V Ground DGND,AGND, HPGND V

w AI Rev 3.0 March 2004

ELECTRICAL CHARACTERISTICS

DCVDD = 1.5V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue Inputs (LINPUT1, RINPUT1, MIC) to ADC AVDD = 3.3V 1.0 Full Scale Input Signal Level (for ADC 0dB Input at 0dB Gain) VINFS AVDD = 1.8V 0.545 V rms L/RINPUT1 to ADC, PGA gain = 0dB L/RINPUT1 to ADC, PGA gain = +30dB 8.2 L/RINPUT1 to mixer 8.7 Input Resistance L/RINPUT1 unused kΩ Input Capacitance pF AVDD = 3.3V Signal to Noise Ratio (A-weighted) SNR AVDD = 1.8V dB Dynamic Range -60dBFs dB -1dBFs input, AVDD = 3.3V -82 0.008 -77 0.014 Total Harmonic Distortion THD -1dBFs input, AVDD = 1.8V -74 0.02 dB ADC Channel Separation 1kHz signal dB Channel Matching 1kHz signal 0.2 dB Analogue Outputs (LOUT1/2, ROUT1/2, MONOOUT) 0dB Full scale output voltage AVDD/3.3 Vrms 1kHz, full scale signal Mute attenuation MONOOUT pin dB Channel Separation analogue in to analogue out dB DAC to Line-Out (L/ROUT2 with 10kΩΩΩΩ / 50pF load) AVDD=3.3V Signal to Noise Ratio (A-weighted) SNR AVDD=1.8V dB AVDD=3.3V -84 Total Harmonic Distortion THD AVDD=1.8V -80 dB Channel Separation 1kHz signal 100 dB

w AI Rev 3.0 March 2004 Test Conditions DCVDD = 1.5V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Headphone Output (LOUT1/ROUT1, using capacitors) Output Power per channel PO Output power is very closely correlated with THD; see below. HPVDD=1.8V, RL=32Ω PO=5mW 0.016 -76 HPVDD=1.8V, RL=16Ω PO=5mW 0.022 -73 HPVDD=3.3V, RL=32Ω, PO=20mW 0.013 -78 Total Harmonic Distortion THD HPVDD=3.3V, RL=16Ω, PO=20mW 0.018 -75 dB HPVDD = 3.3V Signal to Noise Ratio (A-weighted) SNR HPVDD = 1.8V dB Speaker Output (LOUT2/ROUT2 with 8ΩΩΩΩ bridge tied load, ROUT2INV=1) Output Power at 1% THD PO THD = 1% 400 mW (rms) Abs. Max Power Output POmax 500 mW (rms) Total Harmonic Distortion THD Po=180mW, RL=8Ω, HPVDD=3.3V -60 0.1 dB Signal to Noise Ratio (A-weighted) SNR HPVDD=3.3V, RL=8Ω dB Analogue Reference Levels Midrail Reference Voltage VMID –3% AVDD/2 +3% V Buffered Reference Voltage VREF –3% AVDD/2 +3% V Microphone Bias Bias Voltage VMICBIAS 3mA load current –5% 0.9×AVDD + 5% V Bias Current Source IMICBIAS mA Output Noise Voltage Vn 1K to 20kHz nV/√Hz Digital Input / Output Input HIGH Level VIH 0.7×DBVDD V Input LOW Level VIL 0.3×DBVDD V Output HIGH Level VOH IOL=1mA 0.9×DBVDD V Output LOW Level VOL IOH-1mA 0.1×DBVDD V HPDETECT (pin 23) Input HIGH Level VIH 0.7×AVDD V Input LOW Level VIL 0.3×AVDD V

w AI Rev 3.0 March 2004 OUTPUT PGA’S LINEARITY Output PGA Gains -70.000 -60.000 -50.000 -40.000 -30.000 -20.000 -10.000 0.000 10.000 100 110 120 130 XXXVOL Register Setting (binary) Measured Gain [dB] LOUT1 ROUT1 LOUT2 ROUT2 MONOOUT Output PGA Gain Step Size 0.000 0.250 0.500 0.750 1.000 1.250 1.500 1.750 2.000 100 110 120 130 XXXVOL Register Setting (binary) Step Size [dB] LOUT1 ROUT1 LOUT2 ROUT2 MONOOUT

w AI Rev 3.0 March 2004 HEADPHONE OUTPUT THD VERSUS POWER Headphone Power vs THD+N (32Ohm load) -100 -80 -60 -40 -20 Power (mW) THD+N (dB) AVDD=1.8V AVDD=1.8V, capless AVDD=3.3V AVDD=3.3V, capless Headphone Power vs THD+N (16Ohm load) -100 -80 -60 -40 -20 Power (mW) THD+N (dB) AVDD=1.8V AVDD=1.8V, capless AVDD=3.3V AVDD=3.3V, capless

w AI Rev 3.0 March 2004 SPEAKER OUTPUT THD VERSUS POWER Speaker Power vs THD+N (8Ohm BTL load) -70 -60 -50 -40 -30 -20 -10 100 200 300 400 500 Power (mW) THD+N (dB) AVDD=1.8V AVDD=2.5V AVDD=3.3V Speaker Power vs THD+N (8 Ohm BTL load) 100 200 300 400 500 Power (mW) THD+N (%) AVDD=1.8V AVDD=2.5V AVDD=3.3V

w AI Rev 3.0 March 2004 POWER CONSUMPTION The power consumption of the WM8971L depends on the following factors. Supply voltages: Reducing the supply voltages also reduces supply currents, and therefore results in significant power savings, especially in the digital sections of the WM8971L. Operating mode: Significant power savings can be achieved by always disabling parts of the WM8971L that are not used (e.g. mic pre-amps, unused outputs, DAC, ADC, etc.) Control Register R23 Other settings Tot. Power Bit VMIDSEL VREF AINL AINR ADCL ADCR MICB DACL DACR LOUT1 ROUT1 LOUT2 ROUT2 MONO ADCOSR DACOSR VSEL V I (mA) V I (mA) V I (mA) V I (mA) mW OFF 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Clocks stopped 0.0950 0.0570 0.0233 Standby 10 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Interface Stopped 1.4421 (500 KOhm VMID string) 0.7750 0.3771 Playback to Line-out 01 1 0 0 0 0 0 1 1 0 0 1 1 0 0 32.7624 17.4600 7.0536 Playback to Line-out 01 1 0 0 0 0 0 1 1 1 1 0 0 0 0 31.0662 (64x oversampling mode) 16.6175 6.7647 Playback to 16 Ohm Headphone 01 1 0 0 0 0 0 1 1 1 1 0 0 0 0 35.1417 18.8875 7.5465 Playback to 8 Ohm BTL Speaker 01 1 0 0 0 0 0 1 1 0 0 1 1 0 0 R24, ROUT2INV=1 33.3696 18.1175 7.2663 Headphone Amp 01 1 0 0 0 0 0 0 0 1 1 0 0 0 0 Clocks Stopped 9.3126 (line-in to 16 Ohm headphone) 4.9850 2.4360 Speaker Amp 01 1 0 0 0 0 0 0 0 0 0 1 1 0 0 Clocks Stopped 7.7121 (line-in to 8 Ohm speaker) R24, ROUT2INV=1 4.2425 2.1156 Phone Call 01 1 0 0 0 0 1 0 0 0 0 1 1 1 0 Clocks Stopped 9.9330 (mono line-in to headphone, 5.4900 mic to MONOOUT) 2.7492 Record from Line-in 01 1 1 1 1 1 0 0 0 0 0 0 0 0 0 51.3579 30.5550 15.7575 Record from Line-in 01 1 1 1 1 1 0 0 0 0 0 0 0 0 1 37.3593 (64x oversampling mode) 20.5925 9.5295 Record from mono microphone 01 1 1 0 1 0 1 0 0 0 0 0 0 0 0 38.9796 R23, DATSEL=01 21.9675 10.2333 Stereo Record & Playback 01 1 1 1 1 1 1 1 1 0 0 1 1 0 0 77.2563 44.7800 19.8597 Stereo Record & Playback 01 1 1 1 1 1 1 1 1 0 0 1 1 0 1 59.5782 (64x oversampling mode) 33.2325 13.9962 DBVDD HPVDD R24 R25 (19h) R26 (1Ah) AVDD DCVDD Table 1 Supply Current Consumption Notes: All figures are at TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 12.288 MHz (256fs), with zero signal (quiescent) The power dissipated in the headphone or speaker is not included in the above table.

w AI Rev 3.0 March 2004 Test Conditions DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Bit Clock Timing Information BCLK rise time (10pF load) tBCLKR ns BCLK fall time (10pF load) tBCLKF ns BCLK duty cycle (normal mode, BCLK = MCLK/n) tBCLKDS 50:50 BCLK duty cycle (USB mode, BCLK = MCLK) tBCLKDS TMCLKDS Audio Data Input Timing Information ADCLRC/DACLRC propagation delay from BCLK falling edge tDL ns ADCDAT propagation delay from BCLK falling edge tDDA ns DACDAT setup time to BCLK rising edge tDST ns DACDAT hold time from BCLK rising edge tDHT ns AUDIO INTERFACE TIMING – SLAVE MODE BCLK DACLRC/ ADCLRC tBCH tBCL tBCY DACDAT ADCDAT tLRSU tDS tLRH tDH tDD Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY ns BCLK pulse width high tBCH ns BCLK pulse width low tBCL ns ADCLRC/DACLRC set-up time to BCLK rising edge tLRSU ns ADCLRC/DACLRC hold time from BCLK rising edge tLRH ns DACDAT hold time from BCLK rising edge tDH ns ADCDAT propagation delay from BCLK falling edge tDD ns Note: BCLK period should always be greater than or equal to MCLK period.

w AI Rev 3.0 March 2004 CONTROL INTERFACE TIMING – 3-WIRE MODE CSB SCLK SDIN tCSL tDHO tDSU tCSH tSCY tSCH tSCL tSCS LSB tCSS Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CSB rising edge tSCS ns SCLK pulse cycle time tSCY 200 ns SCLK pulse width low tSCL ns SCLK pulse width high tSCH ns SDIN to SCLK set-up time tDSU ns SCLK to SDIN hold time tDHO ns CSB pulse width low tCSL ns CSB pulse width high tCSH ns CSB rising to SCLK rising tCSS ns Pulse width of spikes that will be suppressed tPS ns

w AI Rev 3.0 March 2004 CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK Frequency 400 kHz SCLK Low Pulse-Width 600 ns SCLK High Pulse-Width 1.3 us Hold Time (Start Condition) 600 ns Setup Time (Start Condition) 600 ns Data Setup Time 100 ns SDIN, SCLK Rise Time 300 ns SDIN, SCLK Fall Time 300 ns Setup Time (Stop Condition) 600 ns Data Hold Time 900 ns Pulse width of spikes that will be suppressed tps ns

w AI Rev 3.0 March 2004 DEVICE DESCRIPTION INTRODUCTION The WM8971L is a low power audio codec offering a combination of high quality audio, advanced features, low power and small size. These characteristics make it ideal for portable digital audio applications such as Digital Still Cameras, MP3 and minidisk player / recorders. The device includes a stereo analogue input which can be switched internally. This input can be used as either a line level input, as a microphone input or be selected as a mono differential input. A mono input is also included which can be configured as a microphone or line input. When recording a programmable gain amplifier with automatic level control (ALC) keeps the recording volume constant. The on-chip stereo ADC and DAC are of a high quality using a multi-bit, low-order oversampling architecture to deliver optimum performance with low power consumption. The DAC output signal first enters an analogue mixer where an analogue input and/or the post-ALC signal can be added to it. This mix is available on line and headphone outputs. The WM8971L has a configurable digital audio interface where ADC data can be read and digital audio playback data fed to the DAC. It supports a number of audio data formats including I2S, DSP Mode (a burst mode in which frame sync plus 2 data packed words are transmitted), MSB-First, left justified and MSB-First, right justified, and can operate in master or slave modes. The WM8971L uses a unique clocking scheme that can generate many commonly used audio sample rates from either a 12.00MHz USB clock or an industry standard 256/384 fs clock. This feature eliminates the common requirement for an external phase-locked loop (PLL) in applications where the master clock is not an integer multiple of the sample rate. Sample rates of 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 88.2kHz and 96kHz can be generated. The digital filters used for recording and playback are optimised for each sampling rate used. To allow full software control over all its features, the WM8971L offers a choice of 2 or 3 wire MPU control interface. It is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. The design of the WM8971L has given much attention to power consumption without compromising performance. It operates at very low voltages, and includes the ability to power off parts of the circuitry under software control, including standby and power off modes. INPUT SIGNAL PATH The input signal path for each channel consists of a switch to select between three analogue inputs, followed by a PGA (programmable gain amplifier) and an optional microphone gain boost. A differential input of (LINPUT1 – RINPUT1) may also be selected. The gain of the PGA can be controlled either by the user or by the on-chip ALC function (see Automatic Level Control). The signal then enters an ADC where it is digitised. Alternatively, the two channels can also be mixed in the analogue domain and digitised in one ADC while the other ADC is switched off. The mono-mix signal appears on both digital output channels. SIGNAL INPUTS The WM8971L has three high impedance, low capacitance AC coupled analogue inputs, LINPUT1, RINPUT1, and MIC. The LINSEL and RINSEL control bits select between them. These inputs can be configured as microphone or line inputs by enabling or disabling the microphone gain boost. A differential input, LINPUT1-RINPUT1 may also be selected using L/RINSEL. The signal inputs are biased internally to the reference voltage VREF. Whenever the line inputs are muted or the device placed into standby mode, the inputs are kept biased to VREF using special anti-thump circuitry. This reduces any audible clicks that may otherwise be heard when changing inputs.

w AI Rev 3.0 March 2004 REGISTER ADDRESS BIT LABEL DEFAULT 7:6 LINSEL Left Channel Input Select 00 = LINPUT1 11 = Differential R32 (20h) ADC Signal Path Control (Left) 5:4 LMICBOOST Left Channel Microphone Gain Boost 00 = Boost off (bypassed) 01 = 13dB boost 10 = 20dB boost 11 = 29dB boost 7:6 RINSEL Right Channel Input Select 00 = RINPUT1 01 = MIC 11 = Differential R33 (21h) ADC Signal Path Control (Right) 5:4 RMICBOOST Right Channel Microphone Gain Boost 00 = Boost off (bypassed) 01 = 13dB boost 10 = 20dB boost 11 = 29dB boost Table 2 Input Software Control MONO MIXING The stereo ADC can operate as a stereo or mono device, or the two channels can be mixed to mono, either in the analogue domain (i.e. before the ADC) or in the digital domain (after the ADC). MONOMIX selects the mode of operation. The user also has the flexibility to select the data output from the audio interface using DATSEL. The default is for left and right channel ADC data to be output, but the interface may also be configured so that e.g. left channel ADC data is output as both left and right data for when an analogue mono mix is selected. REGISTER ADDRESS BIT LABEL DEFAULT R31 (1Fh) ADC input Mode 7:6 MONOMIX [1:0] 00: Stereo 01: Analogue Mono Mix (using left ADC) 10: Analogue Mono Mix (using right ADC) 11: Digital Mono Mix Table 3 Mono Mixing REGISTER ADDRESS BIT LABEL DEFAULT R23 (17h) Additional Control (1) 3:2 DATSEL [1:0] 00: left data=left ADC; right data =right ADC 01: left data =left ADC; right data = left ADC 10: left data = right ADC; right data =right ADC 11: left data = right ADC; right data = left ADC Table 4 ADC Data Output Configuration

w AI Rev 3.0 March 2004 The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. Refer to the Applications Information section for recommended external components. The output can be enabled or disables using the MICB control bit (see also the “Power Management” section). REGISTER ADDRESS BIT LABEL DEFAULT R25 (19h) Power Management (1) MICB Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON Table 5 Microphone Bias Control The internal MICBIAS circuitry is shown below. Note that the is a maximum source current capability for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit the MICBIAS current to 3mA. AGND MICBIAS = 1.8 x VMID = 0.9 X AVDD VMID internal resistor internal resistor MICB Figure 6 Microphone Bias Schematic PGA CONTROL The PGA matches the input signal level to the ADC input range. The PGA gain is logarithmically adjustable from +30dB to –17.25dB in 0.75dB steps. Each PGA can be controlled either by the user or by the ALC function (see Automatic Level Control). When ALC is enabled for one or both channels, then writing to the corresponding PGA control register has no effect. The gain is independently adjustable on both Right and Left Line Inputs. However, by setting the LIVU or RIVU bits whilst programming the PGA gain, both channels are simultaneously updated. This reduces the required number of software writes required. Setting the LZCEN and RZCEN bits enables a zero-cross detector which ensures that PGA gain changes only occur when the signal is at zero, eliminating any zipper noise. If zero cross is enabled a timeout is also available to update the gain if a zero cross does not occur. This function may be enabled by setting TOEN in register R23 (17h).

w AI Rev 3.0 March 2004 The inputs can also be muted in the analogue domain under software control. The software control registers are shown in Table 6 REGISTER ADDRESS BIT LABEL DEFAULT 0 = Store LINVOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = LINVOL, right = intermediate latch) LINMUTE Left Channel Input Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: LIVU must be set to un-mute. LZCEN Left Channel Zero Cross Detector 1 = Change gain on zero cross only 0 = Change gain immediately R0 (00h) Left Channel PGA 5:0 LINVOL [5:0] 010111 ( 0dB ) Left Channel Input Volume Control 111111 = +30dB 111110 = +29.25dB . . 0.75dB steps down to 000000 = -17.25dB RIVU Right Volume Update 0 = Store RINVOL in intermediate latch (no gain change) 1 = Update left and right channel gains (right = RINVOL, left = intermediate latch) RINMUTE Right Channel Input Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: RIVU must be set to un-mute. RZCEN Right Channel Zero Cross Detector 1 = Change gain on zero cross only 0 = Change gain immediately R1 (01h) Right Channel PGA 5:0 RINVOL [5:0] 010111 ( 0dB ) Right Channel Input Volume Control 111111 = +30dB 111110 = +29.25dB . . 0.75dB steps down to 000000 = -17.25dB R23 (17h) Additional Control (1) TOEN Timeout Enable 0 : Timeout Disabled 1 : Timeout Enabled Table 6 Input PGA Software Control

w AI Rev 3.0 March 2004 ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8971L uses a multi-bit, oversampled sigma-delta ADC for each channel. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is ADC DIGITAL FILTER The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital filter path is illustrated in Figure 7. FROM ADC DIGITAL HPF DIGITAL FILTER TO DIGITAL AUDIO INTERFACE DIGITAL DECIMATOR ADCHPD Figure 7 ADC Digital Filter The ADC digital filters contain a digital high pass filter, selectable via software control. The high-pass filter response is detailed in the Digital Filter Characteristics section. When the high-pass filter is enabled the dc offset is continuously calculated and subtracted from the input signal. By setting HPOR, the last calculated dc offset value is stored when the high-pass filter is disabled and will continue to be subtracted from the input signal. If the DC offset is changed, the stored and subtracted value will not change unless the high-pass filter is enabled. This feature can be used for calibration purposes. The output data format can be programmed by the user to accommodate stereo or monophonic recording on both inputs. The polarity of the output signal can also be changed under software control. The software control is shown in Table 7. REGISTER ADDRESS BIT LABEL DEFAULT 6:5 ADCPOL [1:0] 00 = Polarity not inverted 01 = L polarity invert 10 = R polarity invert 11 = L and R polarity invert HPOR Store dc offset when High Pass Filter disabled 1 = store offset 0 = clear offset R5 (05h) ADC and DAC Control ADCHPD ADC High Pass Filter Enable (Digital) 1 = Disable High Pass Filter 0 = Enable High Pass Filter Table 7 ADC Signal Path Control

w AI Rev 3.0 March 2004 DIGITAL ADC VOLUME CONTROL The output of the ADCs can be digitally amplified or attenuated over a range from –97dB to +30dB in 0.5dB steps. The volume of each channel can be controlled separately. The gain for a given eight-bit code X is given by: 0.5 × (X-195) dB for 1 ≤ X ≤ 255; MUTE for X = 0 The LAVU and RAVU control bits control the loading of digital volume control data. When LAVU or RAVU are set to 0, the LADCVOL or RADCVOL control data will be loaded into the respective control register, but will not actually change the digital gain setting. Both left and right gain settings are updated when either LAVU or RAVU are set to 1. This makes it possible to update the gain of both channels simultaneously. REGISTER ADDRESS BIT LABEL DEFAULT 7:0 LADCVOL [7:0] 11000011 ( 0dB ) Left ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -97dB 0000 0010 = -96.5dB ... 0.5dB steps up to 1111 1111 = +30dB R21 (15h) Left ADC Digital Volume LAVU Left ADC Volume Update 0 = Store LADCVOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = LADCVOL, right = intermediate latch) 7:0 RADCVOL [7:0] 11000011 ( 0dB ) Right ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -97dB 0000 0010 = -96.5dB ... 0.5dB steps up to 1111 1111 = +30dB R22 (16h) Right ADC Digital Volume RAVU Right ADC Volume Update 0 = Store RADCVOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = intermediate latch, right = RADCVOL) Table 8 ADC Digital Volume Control

w AI Rev 3.0 March 2004 AUTOMATIC LEVEL CONTROL (ALC) The WM8971L has an automatic level control that aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary. Note that when the ALC function is enabled, the settings of registers 0 and 1 (LINVOL, LIVU, LIZC, RINVOL, RIVU and RIZC, but not LINMUTE and RINMUTE) are ignored. hold time decay time attack time input signal signal after ALC PGA gain ALC target level Figure 8 ALC Operation The ALC function is enabled using the ALCSEL control bits. When enabled, the recording volume can be programmed between –6dB and –28.5dB (relative to ADC full scale) using the ALCL register bits. An upper limit for the PGA gain can be imposed by setting the MAXGAIN control bits. HLD, DCY and ATK control the hold, decay and attack times, respectively: Hold time is the time delay between the peak level detected being below target and the PGA gain applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is above target. Decay (Gain Ramp-Up) Time is the time that it takes for the PGA gain to ramp up across 90% of its range (e.g. from –15B up to 27.75dB). The time it takes for the recording level to return to its target value therefore depends on both the decay time and on the gain adjustment required. If the gain adjustment is small, it will be shorter than the decay time. The decay time can be programmed in power-of-two (2n) steps, from 24ms, 48ms, 96ms, etc. to 24.58s. Attack (Gain Ramp-Down) Time is the time that it takes for the PGA gain to ramp down across 90% of its range (e.g. from 27.75dB down to -15B gain). The time it takes for the recording level to return to its target value therefore depends on both the attack time and on the gain adjustment required. If the gain adjustment is small, it will be shorter than the attack time. The attack time can be programmed in power-of-two (2n) steps, from 6ms, 12ms, 24ms, etc. to 6.14s. When operating in stereo, the peak detector takes the maximum of left and right channel peak values, and any new gain setting is applied to both left and right PGAs, so that the stereo image is preserved. However, the ALC function can also be enabled on one channel only. In this case, only one PGA is controlled by the ALC mechanism, while the other channel runs independently with its PGA gain set through the control register. When one ADC channel is unused, the peak detector disregards that channel. The ALC function can also operate when the two ADC outputs are mixed to mono in the digital domain, but not if they are mixed to mono in the analogue domain, before entering the ADCs.

w AI Rev 3.0 March 2004 REGISTER ADDRESS BIT LABEL DEFAULT 8:7 ALCSEL [1:0] (OFF) ALC function select 00 = ALC off (PGA gain set by register) 01 = Right channel only 10 = Left channel only 11 = Stereo (PGA registers unused) Note: ensure that LINVOL and RINVOL settings (reg. 0 and 1) are the same before entering this mode. 6:4 MAXGAIN [2:0] 111 (+30dB) Set Maximum Gain of PGA 111 : +30dB 110 : +24dB ….(-6dB steps) 001 : -6dB 000 : -12dB R17 (11h) ALC Control 1 3:0 ALCL [3:0] 1011 (-12dB) ALC target – sets signal level at ADC input 0000 = -28.5dB FS 0001 = -27.0dB FS … (1.5dB steps) 1110 = -7.5dB FS 1111 = -6dB FS ALCZC 0 (zero cross off) ALC uses zero cross detection circuit. R18 (12h) ALC Control 2 3:0 HLD [3:0] 0000 (0ms) ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms … (time doubles with every step) 1111 = 43.691s 7:4 DCY [3:0] 0011 (192ms) ALC decay (gain ramp-up) time 0000 = 24ms 0001 = 48ms 0010 = 96ms … (time doubles with every step) 1010 or higher = 24.58s R19 (13h) ALC Control 3 3:0 ATK [3:0] 0010 (24ms) ALC attack (gain ramp-down) time 0000 = 6ms 0001 = 12ms 0010 = 24ms … (time doubles with every step) 1010 or higher = 6.14s Table 9 ALC Control PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled. Note: If ATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed to prevent clipping when long attack times are used.

w AI Rev 3.0 March 2004 NOISE GATE When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise pumping”, i.e. loud hissing noise during silence periods. The WM8971L has a noise gate function that prevents noise pumping by comparing the signal level at the LINPUT1/2/3 and/or RINPUT1/2/3 pins against a noise gate threshold, NGTH. The noise gate cuts in when: Signal level at ADC [dB] < NGTH [dB] + PGA gain [dB] + Mic Boost gain [dB] This is equivalent to: Signal level at input pin [dB] < NGTH [dB] The ADC output can then either be muted or digitally attenuated by 18dB. Alternatively, the PGA gain can be held constant (preventing it from ramping up as it normally would when the signal is quiet). The table below summarises the noise gate control register. The NGTH control bits set the noise gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 1.5dB steps. Levels at the extremes of the range may cause inappropriate operation, so care should be taken with set–up of the function. Note that the noise gate only works in conjunction with the ALC function, and always operates on the same channel(s) as the ALC (left, right, both, or none). REGISTER ADDRESS BIT LABEL DEFAULT 7:3 NGTH [4:0] 00000 Noise gate threshold 00000 -76.5dBfs 00001 -75dBfs … 1.5 dB steps 11110 -31.5dBfs 11111 -30dBfs 2:1 NGG [1:0] Noise gate type X0 = PGA gain held constant 01 = mute ADC output 10 = reserved (do not use this setting) 11 = reserved (do not use this setting) R20 (14h) Noise Gate Control NGAT Noise gate function enable 1 = enable 0 = disable Table 10 Noise Gate Control REGISTER ADDRESS BIT LABEL DEFAULT 0 = disabled (0dB) 1 = -6dB enabled R5 (05h) ADC and DAC control DACDIV2 DAC 6dB attenuate enable 0 = disabled (0dB) 1 = -6dB enabled Table 11 ADC and DAC 6dB Attenuation Select

w AI Rev 3.0 March 2004 OUTPUT SIGNAL PATH The WM8971L output signal paths consist of digital filters, DACs, analogue mixers and output drivers. The digital filters and DACs are enabled when the WM8971L is in ‘playback only’ or ‘record and playback’ mode. The mixers and output drivers can be separately enabled by individual control bits (see Analogue Outputs). Thus it is possible to utilise the analogue mixing and amplification provided by the WM8971L, irrespective of whether the DACs are running or not. The WM8971L receives digital input data on the DACDAT pin. The digital filter block processes the data to provide the following functions: Digital volume control Graphic equaliser and Dynamic Bass Boost Sigma-Delta Modulation Two high performance sigma-delta audio DACs convert the digital data into two analogue signals (left and right). These can then be mixed with analogue signals from the LINPUT1/2/3 and RINPUT1/2/3 pins, and the mix is fed to the output drivers, LOUT1/ROUT1, LOUT2/ROUT2 and MONOOUT. LOUT1/ROUT1: can drive a 16Ω or 32Ω stereo headphone or stereo line output. LOUT2/ROUT2: can drive a 16Ω or 32Ω stereo headphone or stereo line output, or an 8Ω mono speaker. MONOOUT: can drive a mono line output or other load down to 10kΩ DIGITAL DAC VOLUME CONTROL The signal volume from each DAC can be controlled digitally, in the same way as the ADC volume (see Digital ADC Volume Control). The gain and attenuation range is –127dB to 0dB in 0.5dB steps. The level of attenuation for an eight-bit code X is given by: 0.5 × (X-255) dB for 1 ≤ X ≤ 255; MUTE for X = 0 The LDVU and RDVU control bits control the loading of digital volume control data. When LDVU or RDVU are set to 0, the LDACVOL or RDACVOL control data is loaded into an intermediate register, but the actual gain does not change. Both left and right gain settings are updated simultaneously when either LDVU or RDVU are set to 1. REGISTER ADDRESS BIT LABEL DEFAULT 0 = Store LDACVOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = LDACVOL, right = intermediate latch) R10 (0Ah) Left Channel Digital Volume 7:0 LDACVOL [7:0] 11111111 ( 0dB ) Left DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB RDVU Right DAC Volume Update 0 = Store RDACVOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = intermediate latch, right = RDACVOL) R11 (0Bh) Right Channel Digital Volume 7:0 RDACVOL [7:0] 11111111 ( 0dB ) Right DAC Digital Volume Control similar to LDACVOL Table 12 Digital Volume Control

w AI Rev 3.0 March 2004 GRAPHIC EQUALISER The WM8971L has a digital graphic equaliser and adaptive bass boost function. This function operates on digital audio data before it is passed to the audio DACs. Bass enhancement can take two different forms: Linear bass control: bass signals are amplified or attenuated by a user programmable gain. This is independent of signal volume, and very high bass gains on loud signals may lead to signal clipping. Adaptive bass boost: The bass volume is amplified by a variable gain. When the bass volume is low, it is boosted more than when the bass volume is high. This method is recommended because it prevents clipping, and usually sounds more pleasant to the human ear. Treble control applies a user programmable gain, without any adaptive boost function. Bass and treble control are completely independent with separately programmable gains and filter characteristics. REGISTER ADDRESS BIT LABEL DEFAULT 0 = Linear bass control 1 = Adaptive bass boost BC Bass Filter Characteristic 0 = Low Cutoff (130Hz at 48kHz sampling) 1 = High Cutoff (200Hz at 48kHz sampling) Bass Intensity Code BB=0 BB=1 0000 +9dB 15 (max) 0001 +9dB 0010 +7.5dB 0011 +6dB 0100 +4.5dB 0101 +3dB 0110 +1.5dB 0111 0dB 1000 -1.5dB 1001 -3dB 1010 -4.5dB 1011 -6dB 1100 -6dB 1101 -6dB 1110 -6dB R12 (0Ch) Bass Control 3:0 BASS [3:0] 1111 (Disabled) 1111 Bypass (OFF) TC Treble Filter Characteristic 0 = High Cutoff (8kHz at 48kHz sampling) 1 = Low Cutoff (4kHz at 48kHz sampling) R13 (0Dh) Treble Control 3:0 TRBL [3:0] 1111 (Disabled) Treble Intensity 0000 or 0001 = +9dB 0010 = +7.5dB … (1.5dB steps) 1011 to 1110 = -6dB 1111 = Disable Table 13 Graphic Equaliser

w AI Rev 3.0 March 2004 DIGITAL TO ANALOGUE CONVERTER (DAC) After passing through the graphic equaliser filters, digital ‘de-emphasis’ can be applied to the audio data if necessary (e.g. when the data comes from a CD with pre-emphasis used in the recording). De-emphasis filtering is available for sample rates of 48kHz, 44.1kHz and 32kHz. The WM8971L also has a Soft Mute function, which gradually attenuates the volume of the digital signal to zero. When removed, the gain will ramp back up to the digital gain setting. This function is enabled by default. To play back an audio signal, it must first be disabled by setting the DACMU bit to zero. REGISTER ADDRESS BIT LABEL DEFAULT 2:1 DEEMP [1:0] De-emphasis Control 11 = 48kHz sample rate 10 = 44.1kHz sample rate 01 = 32kHz sample rate 00 = No De-emphasis R5 (05h) ADC and DAC Control DACMU Digital Soft Mute 1 = mute 0 = no mute (signal active) Table 14 DAC Control The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters two multi-bit, sigma-delta DACs, which convert them to high quality analogue audio signals. The multi-bit DAC architecture reduces high frequency noise and sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and low distortion. In normal operation, the left and right channel digital audio data is converted to analogue in two separate DACs. However, it is also possible to disable one channel, so that the same signal (left or right) appears on both analogue output channels. Additionally, there is a mono-mix mode where the two audio channels are mixed together digitally and then converted to analogue using only one DAC, while the other DAC is switched off. The mono-mix signal can be selected to appear on both analogue output channels. The DAC output defaults to non-inverted. Setting DACINV will invert the DAC output phase on both left and right channels. REGISTER ADDRESS BIT LABEL DEFAULT 5:4 DMONOMIX [1:0] DAC mono mix 00: stereo 01: mono ((L+R)/2) into DACL, ‘0’ into DACR 10: mono ((L+R)/2) into DACR, ‘0’ into DACL 11: mono ((L+R)/2) into DACL and DACR R23 (17h) Additional Control (1) DACINV DAC phase invert 0 : non-inverted 1 : inverted Table 15 DAC Mono Mix and Phase Invert Select

w AI Rev 3.0 March 2004 OUTPUT MIXERS The WM8971L provides the option to mix the DAC output signal with analogue line-in signals from the LINPUT1, RINPUT1, MIC pins or a mono differential input (LINPUT1 – RINPUT1). The level of the mixed-in signals can be controlled with PGAs (Programmable Gain Amplifiers). REGISTER ADDRESS BIT LABEL DEFAULT R34 (22h) Left Mixer (1) 2:0 LMIXSEL 000 Left Input Selection for Output Mix 000 = LINPUT1 011 = Left ADC Input (after PGA / MICBOOST) 100 = Differential input R36 (24h) Right Mixer (1) 2:0 RMIXSEL 000 Right Input Selection for Output Mix 000 = RINPUT1 001 = MIC 010 = Reserved (do not use) 011 = Right ADC Input (after PGA / MICBOOST) 100 = Differential input Table 16 Output Mixer Signal Selection REGISTER ADDRESS BIT LABEL DEFAULT 0 = Disable (Mute) 1 = Enable Path LI2LO LMIXSEL Signal to Left Mixer 0 = Disable (Mute) 1 = Enable Path R34 (22h) Left Mixer Control (1) 6:4 LI2LOVOL [2:0] 101 (-9dB) LMIXSEL Signal to Left Mixer Volume 000 = +6dB … (3dB steps) 111 = -15dB RD2LO Right DAC to Left Mixer 0 = Disable (Mute) 1 = Enable Path RI2LO RMIXSEL Signal to Left Mixer 0 = Disable (Mute) 1 = Enable Path R35 (23h) Left Mixer Control (2) 6:4 RI2LOVOL [2:0] 101 (-9dB) RMIXSEL Signal to Left Mixer Volume 000 = +6dB … (3dB steps) 111 = -15dB Table 17 Left Output Mixer Control

w AI Rev 3.0 March 2004 REGISTER ADDRESS BIT LABEL DEFAULT 0 = Disable (Mute) 1 = Enable Path LI2RO LMIXSEL Signal to Right Mixer 0 = Disable (Mute) 1 = Enable Path R36 (24h) Right Mixer Control (1) 6:4 LI2ROVOL [2:0] 101 (-9dB) LMIXSEL Signal to Right Mixer Volume 000 = +6dB … (3dB steps) 111 = -15dB RD2RO Right DAC to Right Mixer 0 = Disable (Mute) 1 = Enable Path RI2RO RMIXSEL Signal to Right Mixer 0 = Disable (Mute) 1 = Enable Path R37 (25h) Right Mixer Control (2) 6:4 RI2ROVOL [2:0] 101 (-9dB) RMIXSEL Signal to Right Mixer Volume 000 = +6dB … (3dB steps) 111 = -15dB Table 18 Right Output Mixer Control REGISTER ADDRESS BIT LABEL DEFAULT 0 = Disable (Mute) 1 = Enable Path LI2MO LMIXSEL Signal to Mono Mixer 0 = Disable (Mute) 1 = Enable Path R38 (26h) Mono Mixer Control (1) 6:4 LI2MOVOL [2:0] 101 (-9dB) LMIXSEL Signal to Mono Mixer Volume 000 = +6dB … (3dB steps) 111 = -15dB RD2MO Right DAC to Mono Mixer 0 = Disable (Mute) 1 = Enable Path RI2MO RMIXSEL Signal to Mono Mixer 0 = Disable (Mute) 1 = Enable Path R39 (27h) Mono Mixer Control (2) 6:4 RI2MOVOL [2:0] 101 (-9dB) RMIXSEL Signal to Mono Mixer Volume 000 = +6dB … (3dB steps) 111 = -15dB Table 19 Mono Output Mixer Control

w AI Rev 3.0 March 2004 ANALOGUE OUTPUTS LOUT1/ROUT1 OUTPUTS The LOUT1 and ROUT1 pins can drive a 16Ω or 32Ω headphone or a line output (see Headphone Output and Line Output sections, respectively). The signal volume on LOUT1 and ROUT1 can be independently adjusted under software control by writing to LOUT1VOL and ROUT1VOL, respectively. Note that gains over 0dB may cause clipping if the signal is large. Any gain setting below 0101111 (minimum) mutes the output driver. The corresponding output pin remains at the same DC level (the reference voltage on the VREF pin), so that no click noise is produced when muting or un-muting. A zero cross detect on the analogue output may also be enabled when changing the gain setting to minimize audible clicks and zipper noise as the gain updates. If zero cross is enabled a timeout is also available to update the gain if a zero cross does not occur. This function may be enabled by setting TOEN in register R23 (17h). REGISTER ADDRESS BIT LABEL DEFAULT 0 = Store LOUT1VOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = LOUT1VOL, right = intermediate latch) LO1ZC Left zero cross enable 1 = Change gain on zero cross only 0 = Change gain immediately R2 (02h) LOUT1 Volume 6:0 LOUT1VOL [6:0] 1111001 (0dB) LOUT1 Volume 1111111 = +6dB … (80 steps) 0110000 = -67dB 0101111 to 0000000 = Analogue MUTE RO1VU Right Volume Update 0 = Store ROUT1VOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = intermediate latch, right = ROUT1VOL) RO1ZC Right zero cross enable 1 = Change gain on zero cross only 0 = Change gain immediately R3 (03h) ROUT1 Volume 6:0 ROUT1VOL [6:0] 1111001 ROUT1 Volume Similar to LOUT1VOL Table 20 LOUT1/ROUT1 Volume Control

w AI Rev 3.0 March 2004 LOUT2/ROUT2 OUTPUTS The LOUT2 and ROUT2 output pins are essentially similar to LOUT1 and ROUT1, but they are independently controlled and can also drive an 8Ω mono speaker (see Speaker Output section). For speaker drive, the ROUT2 signal must be inverted (ROUT2INV = 1), so that the left and right channel are mixed to mono in the speaker [L–(-R) = L+R]. REGISTER ADDRESS BIT LABEL DEFAULT 6:0 LOUT2VOL [6:0] 1111001 (0dB) Similar to LOUT1VOL LO2ZC Left zero cross enable 1 = Change gain on zero cross only 0 = Change gain immediately R40 (28h) LOUT2 Volume LO2VU Same as LO1VU 6:0 ROUT2VOL [6:0] 1111001 (0dB) Similar ROUT1VOL RO2ZC Right zero cross enable 1 = Change gain on zero cross only 0 = Change gain immediately R41 (29h) ROUT2 Volume RO2VU Same as RO1VU R24 (18h) Additional Control (2) ROUT2INV ROUT2 Invert 0 = No Inversion (0° phase shift) 1 = Signal inverted (180° phase shift) Table 21 LOUT2/ROUT2 Volume Control MONO OUTPUT The MONOOUT pin can drive a mono line output. The signal volume on MONOOUT can be adjusted under software control by writing to MONOOUTVOL. REGISTER ADDRESS BIT LABEL DEFAULT 6:0 MONOOUT VOL [6:0] 1111001 (0dB) MONOOUT Volume 1111111 = +6dB … (80 steps) 0110000 = -67dB 0101111 to 0000000 = Analogue MUTE R42 (2Ah) MONOOUT Volume MOZC MONOOUT zero cross enable 1 = Change gain on zero cross only 0 = Change gain immediately Table 22 MONOOUT Volume Control

w AI Rev 3.0 March 2004 ENABLING THE OUTPUTS Each analogue output of the WM8971L can be separately enabled or disabled. The analogue mixer associated with each output is powered on or off along with the output pin. All outputs are disabled by default. To save power, unused outputs should remain disabled. Outputs can be enabled at any time, except when VREF is disabled (VR=0), as this may cause pop noise (see “Power Management” and “Applications Information” sections) REGISTER ADDRESS BIT LABEL DEFAULT R26 (1Ah) Power Management (2) MONO MONOOUT Enable Note: All “Enable” bits are 1 = ON, 0 = OFF Table 23 Analogue Output Control Whenever an analogue output is disabled, it remains connected to VREF (pin 20) through a resistor. This helps to prevent pop noise when the output is re-enabled. The resistance between VREF and each output can be controlled using the VROI bit in register 27. The default is low (1.5kΩ), so that any capacitors on the outputs can charge up quickly at start-up. If a high impedance is desired for disabled outputs, VROI can then be set to 1, increasing the resistance to about 40kΩ. REGISTER ADDRESS BIT LABEL DEFAULT R27 (1Bh) Additional (1) VROI VREF to analogue output resistance 0: 1.5 kΩ 1: 40 kΩ Table 24 Disabled Outputs to VREF Resistance HEADPHONE SWITCH The HPDETECT pin can be used as a headphone switch control input to automatically disable the speaker output and enable the headphone output e.g. when a headphone is plugged into a jack socket. In this mode, enabled by setting HPSWEN, HPDETECT switches between headphone and speaker outputs (e.g. when the pin is connected to a mechanical switch in the headphone socket to detect plug-in). The HPSWPOL bit reverses the pin’s polarity. Note that the LOUT1, ROUT1, LOUT2 and ROUT2 bits in register 26 must also be set for headphone and speaker output (see Table 25 and Table 26). HPSWEN HPSWPOL HPDETECT (PIN23) L/ROUT1 (REG. 26) L/ROUT2 (REG. 26) HEADPHONE ENABLED SPEAKER ENABLED X X no no X X no yes X X yes no X X yes yes X no no X no yes X no no X yes no X no no X yes no X no no X no yes Table 25 Headphone Switch Operation

w AI Rev 3.0 March 2004 AUDIO DATA FORMATS In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition. LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC BCLK DACDAT/ ADCDAT 1/fs n n-2 n-1 LSB MSB n n-2 n-1 LSB MSB Input Word Length (WL) Note: Input word length is defined by the WL register. Timing is shown with LRP = 1 Figure 16 Left Justified Audio Interface (assuming n-bit word length) In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition. LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC BCLK DACDAT/ ADCDAT 1/fs n n-2 n-1 LSB MSB n n-2 n-1 LSB MSB Input Word Length (WL) Note: Input word length is defined by the WL register. Timing is shown with LRP = 1 Figure 17 Right Justified Audio Interface (assuming n-bit word length) In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next. LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC BCLK DACDAT/ ADCDAT 1/fs n n-2 n-1 LSB MSB n n-2 n-1 LSB MSB

1 BCLK

Input Word Length (WL) Note: Input word length is defined by the WL register. Timing is shown with LRP = 1 Figure 18 I2S Justified Audio Interface (assuming n-bit word length)

w AI Rev 3.0 March 2004 In DSP mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRCLK. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC BCLK DACDAT/ ADCDAT n n-2 n-1 LSB MSB n n-2 n-1 Input Word Length (WL) 1/fs Figure 19 DSP Mode Audio Interface (mode A, LRP=0) LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC BCLK DACDAT/ ADCDAT n n-2 n-1 LSB MSB n n-2 n-1 Input Word Length (WL) 1/fs Figure 20 DSP Mode Audio Interface (mode B, LRP=1)

w AI Rev 3.0 March 2004 AUDIO INTERFACE CONTROL The register bits controlling audio format, word length and master / slave mode are summarised in Table 28. MS selects audio interface operation in master or slave mode. In Master mode BCLK, rate control bits SR[4:0] and USB. In Slave mode BCLK, ADCLRC and DACLRC are inputs. BCLK invert bit (for master and slave modes) 0 = BCLK not inverted 1 = BCLK inverted MS Master / Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode LRSWAP Left/Right channel swap 1 = swap left and right DAC data in audio interface 0 = output left and right data as normal right, left and i2s modes – LRCLK polarity 1 = invert LRCLK polarity 0 = normal LRCLK polarity LRP DSP Mode – mode A/B select 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) 3:2 WL[1:0] Audio Data Word Length 11 = 32 bits (see Note) 10 = 24 bits 01 = 20 bits 00 = 16 bits R7 (07h) Digital Audio Interface Format 1:0 FORMAT[1:0] Audio Data Format Select 11 = DSP Mode 10 = I2S Format 01 = Left justified 00 = Right justified Table 28 Audio Data Format Control Note: Right Justified mode does not support 32-bit data. AUDIO INTERFACE OUTPUT TRISTATE Register bit TRI, register 24(18h) bit[3] can be used to tristate the ADCDAT pin and switch ADCLRC, DACLRC and BCLK to inputs. In Slave mode (MASTER=0) ADCLRC, DACLRC and BCLK are by default configured as inputs and only ADCDAT will be tri-stated, (see Table 29). REGISTER ADDRESS BIT LABEL DEFAULT R24(18h) Additional Control (2) TRI Tristates ADCDAT and switches ADCLRC, DACLRC and BCLK to inputs. 0 = ADCDAT is an output, ADCLRC, DACLRC and BCLK are inputs (slave mode) or outputs (master mode) 1 = ADCDATE is tristated, ADCLRC, DACLRC and BCLK are inputs Table 29 Tri-stating the Audio Interface

w AI Rev 3.0 March 2004 MASTER MODE ADCLRC AND DACLRC ENABLE In Master mode, by default ADCLRC is disabled when the ADC is disabled and DACLRC is disabled when the DAC is disabled. Register bit LRCM, register 24(18h) bit[2] changes the control so that the ADCLRC and DACLRC are disabled only when ADC and DAC are disabled. This enables the user to use e.g. ADCLRC for both ADC and DAC LRCLK and disable the ADC when DAC only operation is required, (see Table 30). REGISTER ADDRESS BIT LABEL DEFAULT R24(18h) Additional Control (2) LRCM Selects disable mode for ADCLRC and DACLRC 0 = ADCLRC disabled when ADC (Left and Right) disabled, DACLRC disabled when DAC (Left and Right) disabled. 1 = ADCLRC and DACLRC disabled only when ADC (Left and Right) and DAC (Left and Right) are disabled. Table 30 ADCLRC/DACLRC Enable CLOCK OUTPUT By default ADCLRC (pin 9) is the ADC word clock input/output. Under the control of ADCLRM[1:0], register 27(1Bh) bits [8:7] the ADCLRC pin may be configured as a clock output. If ADCLRM is 01, 10 or 11 then ADCLRC pin is always an output even in slave mode or when TRI = ‘1’, (see Table 31). REGISTER ADDRESS BIT LABEL DEFAULT R27(18h) Additional Control (3) [8:7] ADCLRM [1:0] Configures ADCLRC pin 00 = ADCLRC is ADC word clock input (slave mode) or ADCLRC output (master mode) 01 = ADCLRC pin is MCLK output 10 = ADCLRC pin is MCLK / 5.5 output 11 = ADCLRC pin is MCLK / 6 output Table 31 ADCLRC Clock Output CLOCKING AND SAMPLE RATES The WM8971L supports a wide range of master clock frequencies on the MCLK pin, and can generate many commonly used audio sample rates directly from the master clock. The ADC and DAC do not need to run at the same sample rate; several different combinations are possible. There are two clocking modes: ‘Normal’ mode supports master clocks of 128fs, 192fs, 256fs, 384fs, and their multiples (Note: fs refers to the ADC or DAC sample rate, whichever is faster) USB mode supports 12MHz or 24MHz master clocks. This mode is intended for use in systems with a USB interface, and eliminates the need for an external PLL to generate another clock frequency for the audio codec. REGISTER ADDRESS BIT LABEL DEFAULT 1 = MCLK is divided by 2 0 = MCLK is not divided 5:1 SR [4:0] 00000 Sample Rate Control R8 (08h) Clocking and Sample Rate Control USB Clocking Mode Select 1 = USB Mode 0 = ‘Normal’ Mode Table 32 Clocking and Sample Rate Control The clocking of the WM8971L is controlled using the CLKDIV2, USB, and SR control bits. Setting the CLKDIV2 bit divides MCLK by two internally. The USB bit selects between ‘Normal’ and USB mode. Each value of SR[4:0] selects one combination of MCLK division ratios and hence one combination of sample rates (see next page). Since all sample rates are generated by dividing MCLK, their

w AI Rev 3.0 March 2004 accuracy depends on the accuracy of MCLK. If MCLK changes, the sample rates change proportionately. target value by a very small amount. This is not audible, as the maximum deviation is only 0.27% (8.0214kHz instead of 8kHz in USB mode). By comparison, a half-tone step corresponds to a 5.9% change in pitch. MCLK CLKDIV2=0 MCLK CLKDIV2=1 ADC SAMPLE RATE (ADCLRC) DAC SAMPLE RATE (DACLRC) USB SR [4:0] FILTER TYPE BCLK (MS=1) ‘Normal’ Clock Mode (‘*’ indicates backward compatibility with WM8731) 8 kHz (MCLK/1536) 8 kHz (MCLK/1536) 00110 * MCLK/4 8 kHz (MCLK/1536) 48 kHz (MCLK/256) 00100 * MCLK/4 12 kHz (MCLK/1024) 12 kHz (MCLK/1024) 01000 MCLK/4 16 kHz (MCLK/768) 16 kHz (MCLK/768) 01010 MCLK/4 24 kHz (MCLK/512) 24 kHz (MCLK/512) 11100 MCLK/4 32 kHz (MCLK/384) 32 kHz (MCLK/384) 01100 * MCLK/4 48 kHz (MCLK/256) 8 kHz (MCLK/1536) 00010 * MCLK/4 48 kHz (MCLK/256) 48 kHz (MCLK/256) 00000 * MCLK/4

12.288 MHz

24.576 MHz

96 kHz (MCLK/128) 96 kHz (MCLK/128) 01110 * MCLK/2 8.0182 kHz (MCLK/1408) 8.0182 kHz (MCLK/1408) 10110 * MCLK/4 8.0182 kHz (MCLK/1408) 44.1 kHz (MCLK/256) 10100 * MCLK/4 11.025 kHz (MCLK/1024) 11.025 kHz (MCLK/1024) 11000 MCLK/4 22.05 kHz (MCLK/512) 22.05 kHz (MCLK/512) 11010 MCLK/4 44.1 kHz (MCLK/256) 8.0182 kHz (MCLK/1408) 10010 * MCLK/4 44.1 kHz (MCLK/256) 44.1 kHz (MCLK/256) 10000 * MCLK/4 11.2896MHz 22.5792MHz 88.2 kHz (MCLK/128) 88.2 kHz (MCLK/128) 11110 * MCLK/2 8 kHz (MCLK/2304) 8 kHz (MCLK/2304) 00111 * MCLK/6 8 kHz (MCLK/2304) 48 kHz (MCLK/384) 00101 * MCLK/6 12 kHz (MCLK/1536) 12 kHz (MCLK/1536) 01001 MCLK/6 16kHz (MCLK/1152) 16 kHz (MCLK/1152) 01011 MCLK/6 24kHz (MCLK/768) 24 kHz (MCLK/768) 11101 MCLK/6 32 kHz (MCLK/576) 32 kHz (MCLK/576) 01101 * MCLK/6 48 kHz (MCLK/384) 48 kHz (MCLK/384) 00001 * MCLK/6 48 kHz (MCLK/384) 8 kHz (MCLK/2304) 00011 * MCLK/6 18.432MHz 36.864MHz 96 kHz (MCLK/192) 96 kHz (MCLK/192) 01111 * MCLK/3 8.0182 kHz (MCLK/2112) 8.0182 kHz (MCLK/2112) 10111 * MCLK/6 8.0182 kHz (MCLK/2112) 44.1 kHz (MCLK/384) 10101 * MCLK/6 11.025 kHz (MCLK/1536) 11.025 kHz (MCLK/1536) 11001 MCLK/6 22.05 kHz (MCLK/768) 22.05 kHz (MCLK/768) 11011 MCLK/6 44.1 kHz (MCLK/384) 8.0182 kHz (MCLK/2112) 10011 * MCLK/6 44.1 kHz (MCLK/384) 44.1 kHz (MCLK/384) 10001 * MCLK/6 16.9344MHz 33.8688MHz 88.2 kHz (MCLK/192) 88.2 kHz (MCLK/192) 11111 * MCLK/3 USB Mode (‘*’ indicates backward compatibility with WM8731) 8 kHz (MCLK/1500) 8 kHz (MCLK/1500) 00110 * MCLK 8 kHz (MCLK/1500) 48 kHz (MCLK/250) 00100 * MCLK 8.0214 kHz (MCLK/1496) 8.0214kHz (MCLK/1496) 10111 * MCLK 8.0214 kHz (MCLK/1496) 44.118 kHz (MCLK/272) 10101 * MCLK 11.0259 kHz (MCLK/1088) 11.0259kHz (MCLK/1088) 11001 MCLK 12 kHz (MCLK/1000) 12 kHz (MCLK/1000) 01000 MCLK 16kHz (MCLK/750) 16kHz (MCLK/750) 01010 MCLK 22.0588kHz (MCLK/544) 22.0588kHz (MCLK/544) 11011 MCLK 24kHz (MCLK/500) 24kHz (MCLK/500) 11100 MCLK 32 kHz (MCLK/375) 32 kHz (MCLK/375) 01100 * MCLK 44.118 kHz (MCLK/272) 8.0214kHz (MCLK/1496) 10011 * MCLK 44.118 kHz (MCLK/272) 44.118 kHz (MCLK/272) 10001 * MCLK 48 kHz (MCLK/250) 8 kHz (MCLK/1500) 00010 * MCLK 48 kHz (MCLK/250) 48 kHz (MCLK/250) 00000 * MCLK 88.235kHz (MCLK/136) 88.235kHz (MCLK/136) 11111 * MCLK 12.000MHz 24.000MHz 96 kHz (MCLK/125) 96 kHz (MCLK/125) 01110 * MCLK Table 33 Master Clock and Sample Rates

w AI Rev 3.0 March 2004 The WM8971L has two possible device addresses, which can be selected using the CSB pin. CSB STATE DEVICE ADDRESS Low 0011010 (0 x 34h) High 0011011 (0 x 36h) Table 35 2-Wire MPU Interface Address Selection POWER SUPPLIES The WM8971L can use up to four separate power supplies: AVDD / AGND: Analogue supply, powers all analogue functions except the headphone drivers. AVDD can range from 1.8V to 3.6V and has the most significant impact on overall power consumption (except for power consumed in the headphone). A large AVDD slightly improves audio quality. HPVDD / HPGND: Headphone supply, powers analogue outputs L/ROUT1, L/ROUT2 and MONOOUT. HPVDD is normally tied to AVDD, but requires separate layout and decoupling capacitors to curb harmonic distortion. If HPVDD is lower than AVDD, the output signal may be clipped. DCVDD: Digital core supply, powers all digital functions except the audio and control interfaces. DCVDD can range from 1.42V to 3.6V, and has no effect on audio quality. The return path for DCVDD is DGND, which is shared with DBVDD. DBVDD: Digital buffer supply, powers the audio and control interface buffers. This makes it possible to run the digital core at very low voltages, saving power, while interfacing to other digital devices using a higher voltage. DBVDD draws much less power than DCVDD, and has no effect on audio quality. DBVDD can range from 1.8V to 3.6V. The return path for DBVDD is DGND, which is shared with DCVDD. It is possible to use the same supply voltage on all four. However, digital and analogue supplies should be routed and decoupled separately to keep digital switching noise out of the analogue signal paths.

w AI Rev 3.0 March 2004 POWER MANAGEMENT The WM8971L has two control registers that allow users to select which functions are active. For minimum power consumption, unused functions should be disabled. To avoid any pop or click noise, it is important to enable or disable functions in the correct order (see Applications Information). VMIDSEL is the enable for the Vmid reference, which defaults to disabled and can be enabled as a 50kOhm potential divider or, for low power maintenance of Vref when all other blocks are disabled, as a 500kOhm potential divider. REGISTER ADDRESS BIT LABEL DEFAULT 8:7 VMIDSEL Vmid divider enable and select 00 – Vmid disabled (for OFF mode) 01 – 50kOhm divider enabled (for playback/record) 10 – 500kOhm divider enabled (for low-power standby) 11 – 5kOhm divider enabled (for fast start-up) VREF VREF (necessary for all other functions) AINL Analogue in PGA Left AINR Analogue in PGA Right ADCL ADC Left ADCR ADC Right R25 (19h) Power Management (1) MICB MICBIAS DACL DAC Left DACR DAC Right LOUT1 LOUT1 Output Buffer* ROUT1 ROUT1 Output Buffer* LOUT2 LOUT2 Output Buffer* ROUT2 ROUT2 Output Buffer* R26 (1Ah) Power Management (2) MONO MONOOUT Output Buffer and Mono Mixer Note: All control bits are 0=OFF, 1=ON * The left mixer is enabled when LOUT1=1 or LOUT2=1. The right mixer is enabled when ROUT1=1 or ROUT2=1. Table 36 Power Management STOPPING THE MASTER CLOCK In order to minimise power consumed in the digital core of the WM8971L, the master clock should be stopped in Standby and OFF modes. If this is cannot be done externally at the clock source, the DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core. In Standby mode with all supplies at 3.3V, setting DIGENB saves approximately 0.27mA on DCVDD and 0.2mA on DBVDD. However, since setting DIGENB has no effect on the power consumption of other system components external to the WM8971L, it is preferable to disable the master clock at its source wherever possible. REGISTER ADDRESS BIT LABEL DEFAULT R25 (19h) Additional Control (1) DIGENB Master clock disable 0: master clock enabled 1: master clock disabled Table 37 ADC and DAC Oversampling Rate Selection NOTE: Before DIGENB can be set, the control bits ADCL, ADCR, DACL and DACR must be set to zero and a waiting time of 1ms must be observed. Any failure to follow this procedure may prevent DACs and ADCs from re-starting correctly.

w AI Rev 3.0 March 2004 SAVING POWER BY REDUCING OVERSAMPLING RATE The default mode of operation of the ADC and DAC digital filters is in 128x oversampling mode. Under the control of ADCOSR and DACOSR the oversampling rate may be halved. This will result in a slight decrease in noise performance but will also reduce the power consumption of the device. REGISTER ADDRESS BIT LABEL DEFAULT ADC oversample rate select 1 = 64x (lowest power) 0 = 128x (best SNR) R24 (18h) Additional Control (2) DACOSR DAC oversample rate select 1 = 64x (lowest power) 0 = 128x (best SNR) Table 38 ADC and DAC Oversampling Rate Selection SAVING POWER AT LOW SUPPLY VOLTAGES The analogue supplies to the WM8971L can run from 1.8V to 3.6V. By default, all analogue circuitry on the device is optimized to run at 3.3V. This set-up is also good for all other supply voltages down to 1.8V. However, at lower voltages, it is possible to save power by reducing the internal bias currents used in the analogue circuitry. This is controlled as shown below. REGISTER ADDRESS BIT LABEL DEFAULT R23 (17h) Additional Control(1) 7:6 VSEL [1:0] Analogue Bias optimization 00: Lowest bias current, optimized for AVDD=1.8V 01: Low bias current, optimized for AVDD=2.5V 1X: Default bias current, optimized for AVDD=3.3V

w AI Rev 3.0 March 2004 REGISTER MAP REGISTER ADDRESS (Bit 15 – 9) remarks Bit[8] Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0] default page ref R0 (00h) 0000000 Left Input volume LIVU LINMUTE LIZC LINVOL 010010111 R1 (01h) 0000001 Right Input volume RIVU RINMUTE RIZC RINVOL 010010111 R2 (02h) 0000010 LOUT1 volume LO1VU LO1ZC LOUT1VOL[6:0] 001111001 R3 (03h) 0000011 ROUT1 volume RO1VU RO1ZC ROUT1VOL[6:0] 001111001 R4 (04h) 0000100 Reserved 000000000 R5 (05h) 0000101 ADC and DAC Control ADCDIV2 DACDIV2 ADCPOL[1:0] HPOR DACMU DEEMPH[1:0] ADCHPD 000001000 20,25,28 R6 (06h) 0000110 Reserved 000000000 R7 (07h) 0000111 Audio Interface BCLKINV MS LRSWAP LRP WL[1:0] FORMAT[1:0] 000001010 R8 (08h) 0001000 Sample rate CLKDIV2 SR[4:0] USB 000000000 R9 (09h) 0001001 Reserved 000000000 R10 (0Ah) 0001010 Left DAC volume LDVU LDACVOL[7:0] 011111111 R11 (0Bh) 0001011 Right DAC volume RDVU RDACVOL[7:0] 011111111 R12 (0Ch) 0001100 Bass control BB BC BASS[3:0] 000001111 R13 (0Dh) 0001101 Treble control TC TRBL[3:0] 000001111 R15 (0Fh) 0001111 Reset writing to this register resets all registers to their default state not reset R16 (10h) 0010000 Reserved 000000000 R17 (11h) 0010001 ALC1 ALCSEL[1:0] MAXGAIN[2:0] ALCL[3:0] 001111011 R18 (12h) 0010010 ALC2 ALCZC HLD[3:0] 000000000 R19 (13h) 0010011 ALC3 DCY[3:0] ATK[3:0] 000110010 R20 (14h) 0010100 Noise Gate NGTH[4:0] NGG[1:0] NGAT 000000000 R21 (15h) 0010101 Left ADC volume LAVU LADCVOL[7:0] 011000011 R22 (16h) 0010110 Right ADC volume RAVU RADCVOL[7:0] 011000011 R23 (17h) 0010111 Additional control(1) TSDEN VSEL[1:0] DMONOMIX[1:0] DATSEL[1:0] DACINV TOEN 011000000 18,20,28,35 R24 (18h) 0011000 Additional control(2) HPSWEN HPSWPOL ROUT2INV TRI LRCM ADCOSR DACOSR 000000000 32, 34,46 R25 (19h) 0011001 Pwr Mgmt (1) VMIDSEL[1:0] VREF AINL AINR ADCL ADCR MICB DIGENB 000000000 R26 (1Ah) 0011010 Pwr Mgmt (2) DACL DACR LOUT1 ROUT1 LOUT2 ROUT2 MONO 000000000 R27 (1Bh) 0011011 Additional Control (3) ADCLRM[1:0] VROI 000000000 R31 (1Fh) 0011111 ADC input mode DS MONOMIX[1:0] 000000000 R32 (20h) 0100000 ADCL signal path LINSEL[1:0] LMICBOOST[1:0] 000000000 R33 (21h) 0100001 ADCR signal path RINSEL[1:0] RMICBOOST[1:0] 000000000 R34 (22h) 0100010 Left out Mix (1) LD2LO LI2LO LI2LOVOL[2:0] LMIXSEL[2:0] 001010000 R35 (23h) 0100011 Left out Mix (2) RD2LO RI2LO RI2LOVOL[2:0] 001010000 R36 (24h) 0100100 Right out Mix (1) LD2RO LI2RO LI2ROVOL[2:0] RMIXSEL[2:0] 001010000 R37 (25h) 0100101 Right out Mix (2) RD2RO RI2RO RI2ROVOL[2:0] 001010000 R38 (26h) 0100110 Mono out Mix (1) LD2MO LI2MO LI2MOVOL[2:0] 001010000 R39 (27h) 0100111 Mono out Mix (2) RD2MO RI2MO RI2MOVOL[2:0] 001010000 R40 (28h) 0101000 LOUT2 volume LO2VU LO2ZC LOUT2VOL[6:0] 001111001 R41 (29h) 0101001 ROUT2 volume RO2VU RO2ZC ROUT2VOL[6:0] 001111001 R42 (2Ah) 0101010 MONOOUT volume MOZC MOUTVOL[6:0] 001111001 Note: All unused register bits must be set to ‘0’ when writing to WM8971L.

w AI Rev 3.0 March 2004 DIGITAL FILTER CHARACTERISTICS The ADC and DAC employ different digital filters. There are 4 types of digital filter, called Type 0, 1, 2 and 3. The performance of Types 0 and 1 is listed in the table below, the responses of all filters is shown in the proceeding pages. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC Filter Type 0 (USB Mode, 250fs operation) +/- 0.05dB 0.416fs Passband -6dB 0.5fs Passband Ripple +/- 0.05 dB Stopband 0.584fs Stopband Attenuation f > 0.584fs -60 dB ADC Filter Type 1 (USB mode, 272fs or Normal mode operation) +/- 0.05dB 0.4535fs Passband -6dB 0.5fs Passband Ripple +/- 0.05 dB Stopband 0.5465fs Stopband Attenuation f > 0.5465fs -60 dB -3dB 3.7 -0.5dB 10.4 High Pass Filter Corner Frequency -0.1dB 21.6 Hz DAC Filter Type 0 (USB mode, 250fs operation) +/- 0.03dB 0.416fs Passband -6dB 0.5fs Passband Ripple +/-0.03 dB Stopband 0.584fs Stopband Attenuation f > 0.584fs -50 dB DAC Filter Type 1 (USB mode, 272fs or Normal mode operation) +/- 0.03dB 0.4535fs Passband -6dB 0.5fs Passband Ripple +/- 0.03 dB Stopband 0.5465fs Stopband Attenuation f > 0.5465fs -50 dB Table 39 Digital Filter Characteristics TERMINOLOGY Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band) Pass-band Ripple – any variation of the frequency response in the pass-band region

w AI Rev 3.0 March 2004 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 46 Recommended External Components Diagram

w AI Rev 3.0 March 2004 COMPONENT REFERENCE SUGGESTED VALUE C1 – C4 100nF De-coupling for DBVDD, DCVDD, AVDD, HPVDD C5 – C6 10uF Reservoir capacitor for DVDD, AVDD. Should the supplies use separate sources then additional capacitors will be required of each additional source. C7 – C9 1uF AC input coupling capacitors C13 2.2uF Output AC coupling capacitors to remove DC level from MONOOUT C14 and C15 220uF Output AC coupling capacitors to remove DC level from headphone output (If used as a line-out only, use 2.2uF caps) C16 100nF De-coupling for VMID. C17 10uF Reservoir capacitor for VMID C18 100nF De-coupling for VREF C19 10uF Reservoir capacitor for VREF C20 100nF De-coupling for MICBIAS – Not required if MICBIAS output is not used C21 10uF Reservoir capacitor for MICBIAS – Not required if MICBIAS output is not used Table 40 External Components Descriptions Note: For Capacitors C5, C6, C17, C19 and C21 it is recommended that very low ESR components are used. LINE INPUT CONFIGURATION When LINPUT1/RINPUT1 or MIC are used as line inputs, the microphone boost and ALC functions should normally be disabled. In order to avoid clipping, the user must ensure that the input signal does not exceed AVDD. This may require a potential divider circuit in some applications. It is also recommended to remove RF interference picked up on any cables using a simple first-order RC filter, as high-frequency components in the input signal may otherwise cause aliasing distortion in the audio band. AC signals with no DC bias should be fed to the WM8971L through a DC blocking capacitor, e.g. 1µF. MICROPHONE INPUT CONFIGURATION Figure 47 Recommended Circuit for Line Input For interfacing to a microphone, the ALC function should be enabled and the microphone boost switched on. Microphones held close to a speaker’s mouth would normally use the 13dB gain setting, while tabletop or room microphones would need a 29dB boost. The recommended application circuit is shown above. R1 and R2 form part of the biasing network (refer to Microphone Bias section). R1 connected to MICBIAS is necessary only for electret type microphones that require a voltage bias. R2 should always be present to prevent the microphone 47kOhm 220pF 1uF AGND AGND AGND L/RINPUT1 MIC FROM MICROPHONE 680 Ohm to 2.2kOhm check microphone's specification MICBIAS

w AI Rev 3.0 March 2004 input from charging to a high voltage which may damage the microphone on connection. R1 and R2 should be large so as not to attenuate the signal from the microphone, which can have source impedance greater than 2kOhm. C1 together with the source impedance of the microphone and the WM8971L input impedance forms an RF filter. C2 is a DC blocking capacitor to allow the microphone to be biased at a different DC voltage to the MICIN signal. MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS To minimise any pop or click noise when the system is powered up or down, the following procedures are recommended. POWER UP Switch on power supplies. By default the WM8971L is in Standby Mode, the DAC is digitally muted and the Audio Interface, Line outputs and Headphone outputs are all OFF (DACMU = 1 Power Management registers 1 and 2 are all zeros). Enable Vmid and VREF, then wait for time TBD Enable DACs as required Enable line and / or headphone output buffers as required. Set DACMU = 0 to soft-un-mute the audio DACs. POWER DOWN Set DACMU = 1 to soft-mute the audio DACs. Disable all output buffers, then wait for time TBD. Switch off the power supplies. POWER MANAGEMENT EXAMPLES POWER MANAGEMENT (1) POWER MANAGEMENT (2) PGAs ADCs DACs Output Buffers OPERATION MODE VREF AINL/R PGL PGR ADL ADR MBI DAL DAR LO1 RO1 LO2 RO2 MO Stereo Headphone Playback Stereo Line-in Record Stereo Microphone Record Mono Microphone Record Stereo Line-in to Headphone Out Phone Call Speaker Phone Call [ROUT2INV = 1] Record Phone Call [L channel = mic with boost, R channel = RX, enable mono mix] Table 41 Register Settings for Power Management

w AI Rev 3.0 March 2004 PACKAGE DIMENSIONS DM030.C FL: 32 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.9 mm BODY, 0.50 mm LEAD PITCH NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. DIMENSION L1 REPRESENTS TERMINAL PULL BACK FROM PACKAGE SIDE WALL. MAXIMUM OF 0.1mm IS ACCEPTABLE. WHERE TERMINAL PULL BACK EXISTS, ONLY UPPER HALF OF LEAD IS VISIBLE ON PACKAGE SIDE WALL DUE TO HALF ETCHING OF LEADFRAME. 2. FALLS WITHIN JEDEC, MO-220 WITH THE EXCEPTION OF D2, E2: D2,E2: LARGER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION 3. ALL DIMENSIONS ARE IN MILLIMETRES 4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 5. SHAPE AND SIZE OF CORNER TIE BAR MAY VARY WITH PACKAGE TERMINAL COUNT. CORNER TIE BAR IS CONNECTED TO EXPOSED PAD INTERNALLY SEE DETAIL B E2/2 b B A e CORNER TIE BAR C 0.08 C ccc A C (A3) SEATING PLANE B L D2/2 SEE DETAIL A INDEX AREA (D/2 X E/2) TOP VIEW D C aaa 2 X C aaa 2 X E DETAIL B TERMINAL TIP R DATUM e e/2 DETAIL A B C bbb M A 32x b L 32x K R 0.566 mm 0.43 mm CORNER TIE BAR Symbols Dimensions (mm) MIN NOM MAX NOTE A b D E e L R 0.85 0.90 1.00 0.05 0.02

0.2 REF

0.30 0.23 0.18 5.00 3.4 3.3 3.2

0.5 BSC

0.35 0.4 0.45 0.1 b(min)/2 K 0.20 aaa bbb ccc REF: 0.15 0.10 0.10 JEDEC, MO-220, VARIATION VKKD-2 Tolerances of Form and Position 4.90 5.10 5.00 4.90 5.10 3.4 3.3 3.2 EXPOSED CENTRE PAD

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