WM8955L

Wolfson Microelectronic...

STEREO DAC FOR PORTABLE AUDIO APPLICATIONS

Manufacturer: Wolfson Microelectronic...

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WM8955L WOLFSON | Alldatasheet

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STEREODACFORPORTABLEAUDIOAPPLICATIONS WOLFSON MICROELECTRONICS PLC www.wolfsonmicro.com Product Preview, May2003, Rev 0.4 Copyright 2003 Wolfson Microelectronics plc

DESCRIPTION

The WM8955L is a low power, high qualitystereo DAC with integrated headphone and loudspeaker amplifiers, designed to reduce external component requirements in portable digital audio applications. The on-chip headphone amplifiers can deliver 40mW into a 16Ω load. Advanced on-chip digital signal processing performs bass and treble tone control. The WM8955L can operate as a master or a slave, and includes an on-chip PLL. It can use most master clock frequencies commonlyfound in portable sy stems, including USB, GSM, CDMA or PDC clocks, or standard 256f s clock rates. Different audio sample rates such as 48kHz, 44.1kHz, 8kHz and manyothers are supported. The WM8955L operates on supplyvoltages from 1.8V up to 3.6V, although the digital core can operate on a separate supplydown to 1.42V, saving power. Different sections of the chip can also be powered down under software control. The WM8955L is supplied in a verysmall and thin 5x5mm QFN package, ideal for use in hand-held and portable systems.

FEATURES

DAC SNR 98dB, THD -95dB (‘A’ weighted @ 48kHz, 3.3V)
On-chip 400mW BTL Speaker Driver (mono)
On-chip Headphone Driver ° 40mW output power on 16Ω /3 . 3 V ° THD –80dB at 20mW, SNR 90dB with 16Ω load
Stereo and Mono Line-in mix into DAC output
SeparatelyMixed Stereo and Mono Outputs
Digital Tone Control and Bass Boost
Low Power ° Down to 7mW for stereo playback (1.8V / 1.5V supplies) ° 10µW StandbyMode
Low SupplyVoltages ° Analogue 1.8V to 3.6V ° Digital core: 1.42V to 3.6V ° Digital I/O: 1.42V to 3.6V
Master clocks supported: GSM, CDMA, PDC, USB or standard audio clocks
Audio sample rates supported: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48, 88.2, 96kHz
32-pin QFN package, 5x5x0.9mm size, 0.5mm lead pitch

APPLICATIONS

Smartphone / Multimedia Phone
Digital Audio Player BLOCKDIAGRAM DAC LI2LO MI2LO MI2RO RI2RO LI2MO RI2MO LD2LO RD2LO LD2MO RD2MO LD2RO RD2RO LEFT MIXER RIGHT MIXER MONO MIXER HPDETECT DCVDDDBVDD DGND DIGITAL FILTERS TONE CONTROLDIGITAL AUDIO INTERFACE BCLK DACDAT DACLRC VREF AVDD AGND VMID 50K 50K W WM8955L VREF LINEINL LINEINR DACCONTROL INTERFACE CSB SDIN SCLK MODE ROUT1VOL LOUT1VOL MONOVOL LOUT1 ROUT1 MONOOUT LOUT2 ROUT2 HPVDD HPGND ROUT2 INV Loudspeaker L - (-R) =L + R ROUT2VOL LOUT2VOL OUT3 VREF MONOOUT M U X ROUT1 VREF MONOIN+ MONOIN- DIFF. IN MCLK f/2 PLL CLKOUT f/2 MCLK SEL CLKOUT SEL MCLK DIV2 CLKOUT DIV2

w Product Preview Rev 0.4 May2003 PINCONFIGURATION ORDERINGINFORMATION ORDERCODE TEMPERATURE RANGE PACKAGE WM8955LEFL -25 °Ct o+ 8 5°C 32-pin QFN (5x5x0.9mm) 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 DACDAT BCLK DCVDD DGND DBVDD MCLK DACLRC OUT3 AVDD VMID AGND VREF NC HPDETECT HPGND PLLGND MONOOUT HPVDD ROUT1 LOUT1 ROUT2 LOUT2 CLKOUT CSB MODE MONOIN+ LINEINL LINEINR MONOIN- SDIN SCLK NC

w Product Preview Rev 0.4 May2003 PINDESCRIPTION PIN# NAME TYPE DESCRIPTION 1M C L K Digital Input Master Clock 2D C V D D SupplyDigital Core Supply 3D B V D D SupplyDigital Buffer (I/O) Supply 4D G N D SupplyDigital Ground (return path for both DCVDD and DBVDD) 5B C L K Digital Input / Output Audio Interface Bit Clock 6D A C D A T Digital Input DAC Digital Audio Data 7D A C L R C Digital Input / Output Audio Interface Left / Right Clock 8C L K O U T Digital Output Buffered Clock Output (from MCLK or internal PLL) 9 PLLGND SupplyInternally connected to AGND. Connect this pin to AGND externally for best PLL performance, or leave floating.

10 MONOOUT Analogue Output Mono Output

11 OUT3 Analogue Output Output 3 (can be used as Headphone Pseudo Ground)

12 ROUT1 Analogue Output Right Output 1 (Line or Headphone)

13 LOUT1 Analogue Output Left Output 1 (Line or Headphone)

14 HPGND SupplySupply for Analogue Output Drivers (LOUT1/2, ROUT1/2)

15 ROUT2 Analogue Output Right Output 1 (Line or Headphone or Speaker)

16 LOUT2 Analogue Output Left Output 1 (Line or Headphone or Speaker)

17 HPVDD SupplySupply for Analogue Output Drivers (LOUT1/2, ROUT1/2, MONOUT)

18 AVDD SupplyAnalogue Supply

19 AGND SupplyAnalogue Ground (return path for AVDD)

20 VREF Analogue Output Reference Voltage Decoupling Capacitor

21 VMID Analogue Output Midrail Voltage Decoupling Capacitor

22 NC No Connect No Internal Connection

23 HPDETECT Logic Input Headphone / Speaker switch (referred to AVDD)

24 NC No Connect No Internal Connection

25 MONOIN- Analogue Input Negative end of MONOIN+, for differential mono signals

26 MONOIN+ Analogue Input Analogue Line-in to mixers (mono channel)

27 LINEINR Analogue Input Analogue Line-in to mixers (right channel)

28 LINEINL Analogue Input Analogue Line-in to mixers (left channel)

29 MODE Digital Input Control Interface Selection

30 CSB Digital Input Chip Select / Device Address Selection

31 SDIN Digital Input/Output Control Interface Data Input / 2-wire Acknowledge output

32 SCLK Digital Input Control Interface Clock Input

w Product Preview Rev 0.4 May2003 ABSOLUTEMAXIMUMRATINGS Absolute Maximum Ratings are stress ratings only . Permanent damage to the device maybe caused bycontinuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore genericallysusceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION MIN MAX Supplyvoltages -0.3V +3.63V Voltage range digital inputs DGND -0.3V DBVDD +0.3V Voltage range analogue inputs AGND -0.3V AVDD +0.3V Operating temperature range, TA -25°C+ 8 5 °C Storage temperature prior to soldering 30°C max / 85% RH max Storage temperature after soldering -65°C +150 °C Package bodytemperature (soldering 10 seconds) +260°C Package bodytemperature (soldering 2 minutes) +183°C Notes 1. Analogue and digital grounds must always be within 0.3V of each other. 2. All digital and analogue supplies are completelyindependent from each other. RECOMMENDEDOPERATINGCONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital supplyrange (Core) DCVDD 1.42 2.0 3.6 V Digital supplyrange (Buffer) DBVDD 1.8 2.0 3.6 V Analogue supplies range AVDD, HPVDD 1.8 2.0 3.6 V Ground DGND, AGND, HPGND 0 V

w Product Preview Rev 0.4 May2003

ELECTRICAL CHARACTERISTICS

DCVDD = 1.5V, AVDD = HPVDD = 3.3V, TA =+ 2 5oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TESTCONDITIONS MIN TYP MAX UNIT DACto Line-Out(LOUT1/2, ROUT1/2, MONOOUTwith 10kΩΩΩΩ / 50pFload) AVDD = 3.3V 98Signal to Noise Ratio (A-weighted) SNR AVDD = 1.8V 95 dB AVDD = 3.3V -95Total Harmonic Distortion THD AVDD = 1.8V -90 dB Channel Separation 1kHz signal 90 dB AnalogueMixerInputs(LINEINL,LINEINR,MONOIN) AVDD = 3.3V 1.0Full-scale Input Signal Level V INFS AVDD = 1.8V 0.516 Vr m s AVDD = 3.3V 95Signal to Noise Ratio Line-in to Line-Out (A-weighted) SNR AVDD = 1.8V 90 dB AVDD = 3.3V -92 dBTotal Harmonic Distortion THD AVDD = 1.8V -92 dB PGA gain = 0dB 20Input Resistance (signal enters one mixer only) PGA gain = +6dB 10 PGA gain = 0dB 10Input Resistance (signal enters two mixers) RLINEIN PGA gain = +6dB 5 kΩ MONOIN- input resistance R MONOIN- anygain 20 k Ω Programmable Gain -15 +6 dB Programmable Gain Step Size Monotonic 3 dB Mute Attenuation TBD dB AnalogueOutputs(LOUT1/2,ROUT1/2,MONOOUT) 0dB Full scale output voltage AVDD/3.3 Vrms Programmable Gain 1kHz signal -67 +6 dB Programmable Gain Steps Monotonic 80 steps Mute attenuation 1kHz, full scale signal 85 dB Channel Separation 80 90 dB HeadphoneOutput(LOUT1/2,ROUT1/2with 16or32Ohmload) Output Power per channel P O Output power is verycloselycorrelated with THD; see below. HPVDD=1.8V, RL=32Ω PO=5mW 0.013 -78 HPVDD=1.8V, RL=16Ω PO=5mW 0.013 -78 HPVDD=3.3V, RL=32Ω , PO=20mW 0.01 -80 Total Harmonic Distortion THD HPVDD=3.3V, RL=16Ω , PO=20mW 0.01 -80 dB HPVDD = 3.3V 90 dBSignal to Noise Ratio (A-weighted) SNR HPVDD = 1.8V 90 dB

w Product Preview Rev 0.4 May2003 TestConditions DCVDD = 1.5V, AVDD = HPVDD = 3.3V, TA =+ 2 5oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TESTCONDITIONS MIN TYP MAX UNIT SpeakerOutput(LOUT2/ROUT2 with 8ΩΩΩΩ bridgetiedload, ROUT2INV=1) Output Power per channel P O Output power is verycloselycorrelated with THD; see below. Po=180mW, RL=8Ω , HPVDD=3.3V -50 0.3 Total Harmonic Distortion THD Po=400mW, RL=8Ω HPVDD=3.3V -40 dB HPVDD=3.3V, RL=8Ω 90Signal to Noise Ratio (A-weighted) SNR HPVDD=2.5V, RL=8Ω 90 dB AnalogueReferenceLevels Midrail Reference Voltage VMID –3% AVDD/2 +3% V Buffered Reference Voltage VREF –3% AVDD/2 +3% V VREF source current I VREF 5m A VREF sink current I VREF 5m A DigitalInput/Output Input HIGH Level VIH 0.7×DBVDD V Input LOW Level VIL 0.3×DBVDD V Output HIGH Level V OH 0.9×DBVDD V Output LOW Level VOL 0.1×DBVDD V TERMINOLOGY 1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). 2. Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal. Normallya THD+N measurement at 60dB below full scale. The measured signal is then corrected byadding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). 3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. 4. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normallymeasured bysending a full scale signal down one channel and measuring the other.

w Product Preview Rev 0.4 May2003 OUTPUTPGA’SLINEARITY OutputPGAGains -70.000 -60.000 -50.000 -40.000 -30.000 -20.000 -10.000 0.000 10.000 40 50 60 70 80 90 100 110 120 130 XXXVOLRegisterSetting(binary) MeasuredGain[dB] LOUT1 ROUT1 LOUT2 ROUT2 MONOOUT OutputPGAGainStepSize 0.000 0.250 0.500 0.750 1.000 1.250 1.500 1.750 2.000 40 50 60 70 80 90 100 110 120 130 XXXVOLRegister Setting(binary) StepSize[dB] LOUT1 ROUT1 LOUT2 ROUT2 MONOOUT

w Product Preview Rev 0.4 May2003 HEADPHONEOUTPUTTHD VERSUSPOWER(SIMULATION) Headphone Power vs THD+N(32Ohm load) -100 -80 -60 -40 -20 0 5 10 15 20 25 30 Power (mW) THD+N(dB ) AVDD=1.8V AVDD=1.8V, capless AVDD=3.3V AVDD=3.3V,capless Headphone Power vs THD+N(16Ohm load) -100 -80 -60 -40 -20 0 1 02 03 04 05 06 0 Power (mW) THD+N(dB ) AVDD=1.8V AVDD=1.8V,capless AVDD=3.3V AVDD=3.3V,capless

w Product Preview Rev 0.4 May2003 SPEAKEROUTPUTTHD VERSUSPOWER (SIMULATION) Speaker Power vs THD+N(8Ohm BTLload) -70 -60 -50 -40 -30 -20 -10 0 100 200 300 400 500 Power (mW) THD+N(dB ) AVDD=1.8V AVDD=2.5V AVDD=3.3V SpeakerPowervsTHD+N(8Ohm BTL load) 0 100 200 300 400 500 Power(mW) THD+N(%) AVDD=1.8V AVDD=2.5V AVDD=3.3V

w Product Preview Rev 0.4 May2003 POWERCONSUMPTION The power consumption of the WM8955L depends on the following factors.

Supplyvoltages: Reducing the supplyvoltages also reduces supplycurrents, and therefore results in significant power savings.
Operating mode: Power consumption is lower in mono modes than in stereo, as one DAC is switched OFF. Unused analogue outputs should be switched off. Control Register R24 R23 R38 Other settings Tot. Power Bit VMIDSEL VREF DACL DACR LOUT1 ROUT1 LOUT2 ROUT2 MONO OUT3 DACOSR VSEL DMEN PLLEN CLKOUTENV I (mA) V I (mA) V I (mA) V I (mA) (mW) OFF 00 0 0 0 0 0 0 0 0 0 0 11 0 0 0 Clocks stopped 3.3 3.3 3.3 3.3 01 0 0 0 2.5 2.5 2.5 2.5 00 0 0 0 1.8 1.5 1.5 1.8 Low-power standby(LPS) 10 1 0 0 0 0 0 0 0 0 0 11 0 0 0 3.3 3.3 3.3 3.3 using 500 KOhm VMID string 01 0 0 0 2.5 2.5 2.5 2.5 00 0 0 0 1.8 1.5 1.5 1.8 Playback to Line-out 01 1 1 1 0 0 1 1 0 0 0 11 0 0 0 3.3 3.3 3.3 3.3 01 0 0 0 2.5 2.5 2.5 2.5 00 0 0 0 1.8 1.5 1.5 1.8 Playback to Line-out 01 1 1 1 1 1 0 0 0 0 1 11 0 0 0 3.3 3.3 3.3 3.3 (64x oversampling mode) 01 0 0 0 2.5 2.5 2.5 2.5 00 0 0 0 1.8 1.5 1.5 1.8 Playback 01 1 1 1 1 1 0 0 0 0 0 11 0 0 0 3.3 3.3 3.3 3.3 to 16 Ohm headphone 01 0 0 0 2.5 2.5 2.5 2.5 using caps on HPOUTL/R 00 0 0 0 1.8 1.5 1.5 1.8 Playback 01 1 1 1 1 1 0 0 0 1 0 11 0 0 0 R24, OUT3SW=00 3.3 3.3 3.3 3.3 to 16 Ohm headphone 01 0 0 0 2.5 2.5 2.5 2.5 capless mode using OUT3 00 0 0 0 1.8 1.5 1.5 1.8 Playback 01 1 1 1 0 0 1 1 0 0 0 11 0 0 0 R24, ROUT2INV=1 3.3 3.3 3.3 3.3 to 8 Ohm BTL speaker 01 0 0 0 2.5 2.5 2.5 2.5 00 0 0 0 1.8 1.5 1.5 1.8 Headphone Amp 01 1 0 0 1 1 0 0 0 0 0 11 0 0 0 3.3 3.3 3.3 3.3 line-in to 16 Ohm h/phone 01 0 0 0 2.5 2.5 2.5 2.5 00 0 0 0 1.8 1.5 1.5 1.8 Speaker Amp 01 1 0 0 0 0 1 1 0 0 0 11 0 0 0 R24, ROUT2INV=1 3.3 3.3 3.3 3.3 line-in to 8 Ohm speaker 01 0 0 0 2.5 2.5 2.5 2.5 00 0 0 0 1.8 1.5 1.5 1.8 P h o n e C a l l 0 1100110011 0 1 1 1 00 3 . 3 3 . 3 3 . 3 3 . 3 PLL only00 0 0 0 0 0 0 0 0 0 0 11 0 1 0 3.3 3.3 3.3 3.3 01 0 1 0 2.5 2.5 2.5 2.5 00 0 1 0 1.8 1.5 1.5 1.8 PLL and CLKOUT 00 0 0 0 0 0 0 0 0 0 0 11 0 1 1 3.3 3.3 3.3 3.3 01 0 1 1 2.5 2.5 2.5 2.5 00 0 1 1 1.8 1.5 1.5 1.8 Maximum Power 01 1 1 1 1 1 1 1 1 1 0 11 1 1 1 R24, ROUT2INV=1 3.3 3.3 3.3 3.3 everything ON 01 1 1 1 2.5 2.5 2.5 2.5 00 1 1 1 1.8 1.5 1.5 1.8 DBVDD HPVDDR43R25 R26 (1Ah) AVDD DCVDD Table1 SupplyCurrentConsumption(datatofollow) Notes: 1. T A =+ 2 5oC, Slave Mode, fs = 48kHz, MCLK = 12.288 MHz (256fs), 24-bit data 2. All figures are quiescent, with no signal. 3. The power dissipated in the headphone itself is not included in the above table.

w Product Preview Rev 0.4 May2003 TestConditions DBVDD = 3.3V, DGND = 0V, TA =+ 2 5oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT System ClockTiming Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns DACLRC setup time to BCLK rising edge tLRSU 10 ns DACLRC hold time from BCLK rising edge tLRH 10 ns DACDAT hold time from BCLK rising edge tDH 10 ns CONTROLINTERFACETIMING–3-WIREMODE CSB SCLK SDIN tCSL tDHOtDSU tCSH tSCY tSCH tSCL tSCS LSB tCSS Figure4 ControlInterfaceTiming –3-WireSerialControlMode TestConditions DBVDD = 3.3V, DGND = 0V, TA =+ 2 5oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program RegisterInputInformation SCLK rising edge to CSB rising edge tSCS 500 ns SCLK pulse cycle time tSCY 200 ns SCLK pulse width low tSCL 80 ns SCLK pulse width high tSCH 80 ns SDIN to SCLK set-up time tDSU 40 ns SCLK to SDIN hold time t DHO 40 ns CSB pulse width low tCSL 40 ns CSB pulse width high tCSH 40 ns CSB rising to SCLK rising tCSS 40 ns Pulse width of spikes that will be suppressed t ps 05 n s

w Product Preview Rev 0.4 May2003 CONTROLINTERFACETIMING–2-WIREMODE SDIN SCLK t6 t2 Figure5 ControlInterfaceTiming –2-WireSerialControlMode TestConditions DBVDD = 3.3V, DGND = 0V, TA =+ 2 5oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program RegisterInputInformation SCLK Frequency 0 400 kHz SCLK Low Pulse-Width t1 600 ns SCLK High Pulse-Width t2 1.3 us Hold Time (Start Condition) t3 600 ns Setup Time (Start Condition) t 4 600 ns Data Setup Time t5 100 ns SDIN, SCLK Rise Time t6 300 ns SDIN, SCLK Fall Time t7 300 ns Setup Time (Stop Condition) t 8 600 ns Data Hold Time t9 900 ns Pulse width of spikes that will be suppressed tps 05 n s

w Product Preview Rev 0.4 May2003 DEVICEDESCRIPTION INTRODUCTION The WM8955L is a low power audio DAC offering a combination of high qualityaudio, advanced features, low power and small size. These characteristics make it ideal for portable digital audio applications such as portable music players and smartphones. The device has a configurable digital audio interface where digital audio data is fed to the internal digital filters and then the DAC. The interface supports a number of audio data formats including I2S, DSP Mode (a burst mode in which frame sync plus 2 data packed words are transmitted), Left Justified and Right Justified formats, and can operate in master or slave modes. The on-chip digital filters perform tone control and digital volume control according to the user setting, and convert the audio data into oversampled bitstreams, which are passed to the left and right channel DACs. A multi-bit, low-order Σ∆ DAC architecture with dynamic element matching is used, delivering optimum performance with low power consumption. The DAC output signal enters an analogue mixer where analogue input signals can be added to it. The WM8955L has a total of six analogue output pins, which can be configured as stereo line-outs, mono line-outs, differential mono line-outs, stereo headphone outputs or differential mono (BTL) speaker outputs. The WM8955L includes an on-chip PLL to generate commonlyused audio rates, such as 48kHz and 44.1kHz, from system clocks found in GSM, CDMA and PDC phones and other portable systems. To allow full software control over all its features, the WM8955L offers a choice of 2 or 3 wire MPU control interface. It is fullycompatible and an ideal partner for a wide range of industrystandard microprocessors, controllers and DSPs. The design of the WM8955L has given much attention to power consumption without compromising performance. It operates at verylow voltages, and includes the abilityto power off parts of the circuitryunder software control, including standbyand power off modes.

w Product Preview Rev 0.4 May2003 SIGNAL PATH The WM8955L signal paths consists of digital filters, DACs, analogue mixers and output drivers. Each circuit block can be enabled or disabled separatelyusing the control bits in register 26 (see “Power Management”). Thus it is possible to utilise the analogue mixing and amplification provided bythe WM8955L, irrespective of whether the DACs are running or not. The WM8955L receives digital input data on the DACDAT pin. The digital filter block processes the data to provide the following functions:

Digital volume control
Tone control and Bass Boost
Digital Mono Mix
Sigma-Delta Modulation Two high performance, sigma-delta audio DACs convert the digital data into two analogue signals (left and right). These can then be mixed with analogue signals from the LINEINL, LINEINR and MONOIN pins, and the mix is fed to the output drivers, LOUT1/ROUT1, LOUT2/ROUT2, MONOOUT and OUT3.
LOUT1/ROUT1: can drive 16Ω or 32Ω stereo headphones or stereo line output.
LOUT2/ROUT2: can drive an 8Ω mono speaker, stereo headphones or a stereo line-out.
MONOOUT: line output designed to drive a 10kΩ load.
OUT3: multi-function output, maybe used for capacitor-less headphone drive, differential mono-out, line-out or 32Ω earpiece driver.

w Product Preview Rev 0.4 May2003 DIGITALVOLUMECONTROL The WM8955L has on-chip digital attenuation from –127dB to 0dB in 0.5dB steps, allowing the user to adjust the volume of each channel separately. The level of attenuation for an eight-bit code X is given by: -0.5 × (255 – X) dB for 1≤ X ≤ 255; MUTE for X = 0 The LDVU and RDVU control bits control the loading of digital volume control data. When LDVU or RDVU are set to 0, the LDACVOL or RDACVOL control data is loaded into an intermediate register, but the actual gain does not change. Both left and right gain settings are updated simultaneously when either LDVU or RDVU are set to 1. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7:0 LDACVOL[7:0] 11111111 ( 0dB ) Left DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB R10 (0Ah) Left Channel Digital Volume

8 LDVU 0 Left DAC Volume Update

0 = Store LDACVOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = LDACVOL, right = intermediate latch) 7:0 RDACVOL[7:0] 11111111 ( 0dB ) Right DAC Digital Volume Control similar to LDACVOL R11 (0Bh) Right Channel Digital Volume 8 RDVU 0 Right DAC Volume Update 0 = Store RDACVOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = intermediate latch, right = RDACVOL) Table2 DigitalVolumeControl

w Product Preview Rev 0.4 May2003 TONECONTROL The WM8955L provides separate controls for bass and treble with programmable gains and filter characteristics. This function operates on digital audio data before it is passed to the audio DACs. Bass control can take two different forms:

Linear bass control: bass signals are amplified or attenuated bya user programmable gain. This is independent of signal volume, and veryhigh bass gains on loud signals maylead to signal clipping.
Adaptive bass boost: The bass volume is amplified bya variable gain. When the bass volume is low, it is boosted more than when the bass volume is high. This method is recommended because it prevents clipping, and usuallysounds more pleasant to the human ear. Treble control applies a user programmable gain, without anyadaptive boost function. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 7B B 0 B a s s M o d e 0 = Linear bass control 1 = Adaptive bass boost

6 BC 0 Bass Filter Characteristic

0 = Low Cutoff (130 Hz at 48kHz sampling) 1 = High Cutoff (200 Hz at 48kHz sampling) Bass Intensity Code BB=0 BB=1 0000 +9dB 15 (max) 0001 +9dB 14 0010 +7.5dB 13 … (1.5dB steps) … 0111 0dB 8 … (1.5dB steps) … 1011-1101 -6dB 4-2 1110 -6dB 1 (min) R12 (0Ch) Bass Control 3:0 BASS 1111 (OFF)

1111 Bypass (OFF)

6 TC 0 Treble Filter Characteristic

0 = High Cutoff (8kHz at 48kHz sampling) 1 = Low Cutoff (4kHz at 48kHz sampling) R13 (0Dh) Treble Control 3:0 TRBL 1111 (Disabled) Treble Intensity 0000 or 0001 = +9dB 0010 = +7.5dB … (1.5dB steps) 1011 to 1110 = -6dB 1111 = Disable Table3 ToneControl Note: 1. All cut-off frequencies change proportionallywith the DAC sample rate.

w Product Preview Rev 0.4 May2003 DIGITALTOANALOGUECONVERTER(DAC) Treble and linear bass enhancement mayproduce signals that exceed full-scale. In order to avoid limiting under these conditions, it is recommended to set the DAT bit to attenuate the digital input signal by6dB. The gain at the outputs should be increased by6dB to compensate for the attenuation. Cut-onlytone adjustment and adaptive bass boost cannot produce signals above full- scale and therefore do not require the DAT bit to be set. After passing through the tone control filters, digital ‘de-emphasis’ can be applied to the audio data if necessary(e.g. when the data comes from a CD with pre-emphasis used in the recording). De- emphasis filtering is available for sample rates of 48kHz, 44.1kHz and 32kHz. The WM8955L also has a Soft Mute function, which graduallyattenuates the volume of the digital signal to zero. This function is enabled bydefault. To playback an audio signal, the WM8955L must first be unmuted bysetting the DACMU bit to zero. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

7 DAT 0 DAC 6dB attenuate enable

0 = disabled (0dB) 1 = -6dB enabled

3 DACMU 1 Digital Soft Mute

1=m u t e 0 = no mute (signal active) R5 (05h) DAC Control 2:1 DEEMPH 00 De-emphasis Control 11 = 48kHz sample rate 10 = 44.1kHz sample rate 01 = 32kHz sample rate 00 = No De-emphasis Table4 DACControl The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters two multi-bit, sigma-delta DACs, which convert them to high qualityanalogue audio signals. The multi-bit DAC architecture reduces high frequencynoise and sensitivityto clock jitter. It also uses a Dy namic Element Matching technique for high linearityand low distortion. In normal operation, the left and right channel digital audio data are converted to analogue in two separate DACs. However, it is also possible to disable one channel, so that the same signal (left or right) appears on both analogue output channels. Additionally, there is a mono-mix mode where the two audio channels are mixed together digitallyand then converted to analogue using onlyone DAC, while the other DAC is switched off. The mono-mix signal can be selected to appear on both analogue output channels (see Analogue Outputs). REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R23 (17h) Additional (1) 5:4 DMONOMIX[1:0] 00 DAC mono mix 00: stereo 01: mono ((L+R)/2) into DACL, ‘0’ into DACR 10: mono ((L+R)/2) into DACR, ‘0’ into DACL 11: mono ((L+R)/2) into DACL & DACR Table5 DACMonoMixSelect

w Product Preview Rev 0.4 May2003 LINE INPUTS AND OUTPUTMIXERS The WM8955L provides the option to mix the DAC output signal with analogue line-in signals from the LINEINL, LINEINR and MONOIN+ and MONOIN- pins. The level of the mixed-in signals can be controlled with PGAs (Programmable Gain Amplifiers). LINEINL, LINEINR, MONOIN+ and MONOIN- are high impedance, low capacitance AC coupled analogue inputs. Theyare biased internallyto the reference voltage VREF. Whenever these inputs are muted or the device placed into standbymode, the inputs remain biased to VREF using special anti-thump circuitry. This reduces any audible clicks that may otherwise be heard when re-activating the inputs. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION