WM8940GEFL/RV

WM8940_07 WOLFSON | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 85

Technical content

w WM8940 Mono CODEC with Speaker Driver WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ Pre-Production, Rev 3.0, February 2007, Copyright ©2007 Wolfson Microelectronics plc

DESCRIPTION

The WM8940 is a low power, high quality mono CODEC designed for portable applications such as digital still cameras or camcorders. The device integrates support for a differential or single ended mic, and includes drivers for speakers or headphone, and mono line output. External component requirements are reduced as no separate microphone or headphone amplifiers are required. Advanced Sigma Delta Converters are used along with digital decimation and interpolation filters to give high quality audio at sample rates from 8 to 48ks/s. A selectable high pass filter and four fully-programmable notch filters are available in the ADC path. An advanced mixed signal ALC function with noise gate is provided, while readback of PGA gain during ALC operation is supported. The digital audio interface supports A- law and µ-law companding. An on-chip PLL is provided to generate the required Master Clock from an external reference clock. The PLL clock can also be output if required elsewhere in the system. The WM8940 operates at supply voltages from 2.5 to 3.6V, although the digital supplies can operate at voltages down to 1.71V to save power. Different sections of the chip can also be powered down under software control using the selectable two or three wire control interface. WM8940 is supplied in a very small 4x4mm QFN package, offering high levels of functionality in minimum board area, with high thermal performance.

FEATURES

Mono CODEC: Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1, 48kHz DAC SNR 98dB, THD -84dB (‘A’-weighted @ 8 – 48ks/s) ADC SNR 94dB, THD -80dB (‘A’-weighted @ 8 – 48ks/s) On-chip Headphone/Speaker Driver 40mW output power into 16Ω BTL speaker drive 0.4W into 8Ω Additional MONO Line output Multiple analog or ‘Aux’ inputs, plus analog bypass path Mic Preamps: Differential or single end Microphone Interface Programmable preamp gain Pseudo differential inputs with common mode rejection Programmable ALC / Noise Gate in ADC path Low-noise bias supplied for electret microphones OTHER FEATURES Digital Playback Limiter Programmable high pass filter (wind noise reduction) 4 notch filters (narrowband noise suppression) On-chip PLL Low power, low voltage 2.5V to 3.6V (digital: 1.71V to 3.6V) 4x4x0.9mm 24 lead QFN package

APPLICATIONS

Digital still cameras and camcorders General purpose mono audio CODEC

w Pre-Production, Rev 3.0, February 2007 BLOCK DIAGRAM

w Pre-Production, Rev 3.0, February 2007 TABLE OF CONTENTS

w Pre-Production, Rev 3.0, February 2007

w Pre-Production, Rev 3.0, February 2007 PIN CONFIGURATION TOP VIEW

ORDERING INFORMATION

-25°C to +85°C 24-lead QFN (4x4x0.9mm) (Pb-free) MSL3 260oC WM8940GEFL/RV -25°C to +85°C 24-lead QFN (4x4x0.9mm) (Pb-free, tape and reel) MSL3 260oC Note: Reel Quantity = 3,500

w Pre-Production, Rev 3.0, February 2007 PIN DESCRIPTION PIN NAME TYPE Digital Supply (Core) DBVDD Supply Digital supply (Input/Output) DGND Supply Digital ground ADCDAT Digital Output ADC digital audio data output DACDAT Digital Input DAC digital audio data input FRAME Digital Input / Output DAC and ADC sample rate clock or frame synch BCLK Digital Input / Output Digital audio port clock MCLK Digital Input Master clock input CSB/GPIO Digital Input / Output 3-Wire control interface chip select or GPIO pin. SCLK Digital Input 3-Wire control interface clock Input / 2-Wire control interface clock input SDIN Digital Input / Output 3-Wire control interface data Input / 2-Wire control interface data input MODE / GPIO Digital Input Control interface mode selection pin or GPIO pin. MONOOUT Analogue Output Mono output SPKOUTP Analogue Output Speaker output positive SPKGND Supply Speaker ground SPKOUTN Analogue Output Speaker output negative SPKVDD Supply Speaker supply AUX Analogue Input Auxiliary analogue input VMID Reference Decoupling for midrail reference voltage MICN Analogue Input Microphone negative input (common mode) MICP Analogue Input Microphone positive input Note: It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB. Refer to the application note WAN_0118 on “Guidelines on How to Use QFN Packages and Create Associated PCB Footprints”

w Pre-Production, Rev 3.0, February 2007 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION MIN MAX DBVDD, DCVDD, AVDD, SPKVDD supply voltages -0.3V +4.2 Voltage range digital inputs DGND -0.3V DVDD +0.3V Voltage range analogue inputs AGND -0.3V AVDD +0.3V Operating temperature range, TA -25°C +85°C Storage temperature prior to soldering 30°C max / 85% RH max Storage temperature after soldering -65°C +150°C Notes Analogue and digital grounds must always be within 0.3V of each other. All digital and analogue supplies are completely independent from each other. RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital supply range (Core) DCVDD 1.71 3.6 V Digital supply range (Buffer) DBVDD 1.71 3.6 V Analogue supplies range AVDD, SPKVDD1 2.5 3.6 V Ground DGND,AGND, SPKGND V Notes Analogue supply voltages must not be less than the digital supply voltages DBVDD should not be < DCVDD

w Pre-Production, Rev 3.0, February 2007

ELECTRICAL CHARACTERISTICS

DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD =3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Microphone Input PGA Inputs (MICN, MICP) INPPGAVOL and PGABOOST = 0dB Full-scale Input Signal Level – Single- ended input via LIN/RIN 1 AVDD/3.3 Vrms Full-scale Input Signal Level – Pseudo-differential input 1,2 AVDD*0.7/ 3.3 Vrms Input PGA equivalent input noise INPPGAVOL = +35.25dB No input signal 0 to 20kHz 76.5 dB MICN input resistance INPPGAVOL = +35.25dB 1.6 kΩ MICN input resistance INPPGAVOL = 0dB kΩ MICN input resistance INPPGAVOL = -12dB kΩ MICP input resistance All gain settings kΩ Input Capacitance All analogue input pins pF Input PGA Programmable Gain Gain adjusted by INPPGAVOL -12 +35.25 dB Programmable Gain Step Size Guaranteed monotonic 0.75 dB Input PGA Mute Attenuation INPPGAMUTE 108 dB Input Gain Boost PGABOOST= 0 dB Input Gain Boost PGABOOST = 1 +20 dB Auxiliary Analogue Inputs (AUX) Full-scale Input Signal Level 2 AVDD/3.3 Vrms Input Resistance Input boost and mixer enabled, at 0dB gain kΩ Input Capacitance All analogue Inputs pF Gain range from AUX input PGA mixers Gain adjusted by AUX2BOOSTVOL -12 dB AUXLBOOSTVOL and AUXRBOOSTVOL step size dB Analogue to Digital Converter (ADC) - Input from MICN and MICN in differential configuration to input PGA INPPGAVO, PGABOOST and ADCVOL = 0dB Signal to Noise Ratio 3 SNR A-weighted AVDD=3.3V dB Total Harmonic Distortion 4 THD -1dBV Input AVDD=3.3V -83 dB Total Harmonic Distortion + Noise 5 THD+N -1dBV Input AVDD=3.3V -77 dB Channel Separation 6 1kHz full scale input signal 100 dBFS

w Pre-Production, Rev 3.0, February 2007 Digital to Analogue Converter (DAC) to MONO Output with 10kΩ / 50pF load and DACVOL 0dB Full-scale output 1 DACVOL = 0dB AVDD1/3.3 Vrms Signal to Noise Ratio 3 SNR A-weighted AVDD1=AVDD2=3.3V dB Total Harmonic Distortion 4 THD 0dBFS input AVDD1=AVDD2=3.3V -80 dBFS Total Harmonic Distortion + Noise 5 THD+N 0dBFS input AVDD1=AVDD2=3.3V -78 dBFS Channel Separation 6 1kHz signal 100 dB MICP and MICN input PGA to input boost stage into 10kΩ / 50pF load on SPKOUTP and SPKOUTP INPPGAVOL, PGABOOST = 0dB Full-scale output voltage, 0dB gain AVDD2/3.3 Vrms Signal to Noise Ratio 3 SNR A-weighted AVDD1=AVDD2=3.3V dB Total Harmonic Distortion 4 THD full-scale signal AVDD1=AVDD2=3.3V -80 dBFS Total Harmonic Distortion + Noise 5 THD+N full-scale signal AVDD1=AVDD2=3.3V -78 dBFS Channel Separation 6 100 dB Speaker Output (SPKOUTP, SPKOUTN with 8Ω bridge tied load) Output Power Po Output power is closely correlated with THD see below Po=150mW, RL = 8Ω SPKVDD=3.3V 0.03 -68 dB Total Harmonic Distortion 4 THD Po=350mW, RL = 8Ω SPKVDD=3.3V 2.944 -30.6 dB Signal to Noise Ratio 3 SNR A-weighted SPKVDD=3.3V dB Power Supply Rejection Ratio (50Hz-22kHz) PSRR RL = 8Ω BTL dB Headphone Output (SPKOUTP, SPKOUTN with resistive load to GND) Signal to Noise Ratio 3 SNR A-weighted SPKVDD=3.3V dB Total Harmonic Distortion 4 THD Po=20mW, RL = 16Ω SPKVDD=3.3V 0.02 -72 dB Microphone Bias MBVSEL=0 0.9*AVDD1 V Bias Voltage MBVSEL=1 0.65*AVDD1 V Bias Current Source for VMICBIAS within +/-3% Ma Output Noise Voltage 1kHz to 20kHz nV/√Hz Digital Input / Output Input HIGH Level VIH 0.7× DBVDD V Input LOW Level VIL 0.3×DBVDD V Output HIGH Level VOH IOL=1mA 0.9× DBVDD V Output LOW Level VOL IOH-1mA 0.1xDBVDD V Input Capacitance All digital pins pF

w Pre-Production, Rev 3.0, February 2007 TERMINOLOGY Full-scale input and output levels scale in relation to AVDD or AVDD2 depending upon the input or output used. For example, when AVDD = 3.3V, 0dBFS = 1Vrms (0dBV). When AVDD < 3.3V the absolute level of 0dBFS will decrease with a linear relationship to AVDD. Input level to RIP and LIP in differential configurations is limited to a maximum of -3dB or performance will be reduced. Signal-to-noise ratio (dB) – SNR is the difference in level between a reference full scale output signal and the device output with no signal applied. This ratio is also called idle channel noise. (No Auto-zero or Automute function is employed in achieving these results). Total Harmonic Distortion (dB) – THD is the difference in level between a reference output signal and the first seven harmonics of that signal. The reference output signal need not be at full scale amplitude; THD is typically measured using an output power of 20mW into a 16ohm load, corresponding to a reference signal level of -5dB. However the stated test conditions include input signal level, signal gain settings, output load characteristics and power supply voltages To calculate the ratio, the fundamental frequency of the output signal is notched out and an RMS value of the next seven harmonics is calculated. THD is the difference in level between a reference output signal and the first seven harmonics of the output signal. To calculate the ratio, the fundamental frequency of the output signal is notched out and an RMS value of the next seven harmonics is calculated. Total Harmonic Distortion plus Noise (dB) – THD+N is the difference in level between a reference output signal and the sum of the harmonics, wide-band noise and interference on the output signal. To calculate the ratio, the fundamental frequency of the output signal is notched out and an RMS value of the total harmonics, wide-band noise and interference is calculated. Channel Separation (dB) – Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down

w Pre-Production, Rev 3.0, February 2007 POWER CONSUMPTION Typical current consumption for various scenarios is shown below. MODE AVDD (3V3) MA SPKVDD (3V3) MA DCVDD (1.8V) MA DBVDD (1.8V) UA TOTAL POWER (MW) Power OFF (No Clocks) 0.038 0.2 0.126 Sleep (VMID maintained, No Clocks) 0.190 0.2 0.627 Mono Record (MIC input, +20dB gain, 8kHz, quiescent) SLAVE 4.1 0.3 14.3 Mono Record (MIC input, +20dB gain, 44.1kHz, PLL, quiescent) MASTER 5.3 1.9 115 21.0 Mono 16Ω Headphone Playback (0.1mW, 1kHz sine wave, ac coupled) SLAVE 2.8 1.5 1.6 3.7 17.1 Mono 8Ω BTL speaker Playback (44.1kHz, 200mW, 1kHz sine wave) SLAVE 2.8 1.6 3.8 216.8 Mono 8Ω BTL speaker Playback (44.1kHz, PLL, quiescent) MASTER 3.9 1.5 1.8 21.1 Table 1 Power Consumption Note: Power consumption figures include any power dissipated in the load (e.g. in the headphone or speaker)

w Pre-Production, Rev 3.0, February 2007 Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information FRAME propagation delay from BCLK falling edge tDL ns ADCDAT propagation delay from BCLK falling edge tDDA ns DACDAT setup time to BCLK rising edge tDST ns DACDAT hold time from BCLK rising edge tDHT ns AUDIO INTERFACE TIMING – SLAVE MODE Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK= 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 81.38 ns BCLK pulse width high tBCH 32.55 ns BCLK pulse width low tBCL 32.55 ns FRAME set-up time to BCLK rising edge tLRSU ns FRAME hold time from BCLK rising edge tLRH ns DACDAT hold time from BCLK rising edge tDH ns DACDAT set-up time to BCLK rising edge tDS ns ADCDAT propagation delay from BCLK falling edge tDD ns Note: BCLK period should always be greater than or equal to MCLK period.

w Pre-Production, Rev 3.0, February 2007 CONTROL INTERFACE TIMING – 3-WIRE MODE Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CSB rising edge tSCS ns SCLK pulse cycle time tSCY 200 ns SCLK pulse width low tSCL ns SCLK pulse width high tSCH ns SDIN to SCLK set-up time tDSU ns SCLK to SDIN hold time tDHO ns CSB pulse width low tCSL ns CSB pulse width high tCSH ns CSB rising to SCLK rising tCSS ns Pulse width of spikes that will be suppressed tps ns

w Pre-Production, Rev 3.0, February 2007 CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK Frequency 526 kHz SCLK Low Pulse-Width 1.3 us SCLK High Pulse-Width 600 ns Hold Time (Start Condition) 600 ns Setup Time (Start Condition) 600 ns Data Setup Time 100 ns SDIN, SCLK Rise Time 300 ns SDIN, SCLK Fall Time 300 ns Setup Time (Stop Condition) 600 ns Data Hold Time 900 ns Pulse width of spikes that will be suppressed tps ns

w Pre-Production, Rev 3.0, February 2007 DEVICE DESCRIPTION INTRODUCTION The WM8940 is a low power audio codec combining a high quality mono audio DAC and ADC, with flexible line and microphone input and output processing. Applications for this device include digital still cameras or camcorders with mono audio, record and playback capability. The chip offers great flexibility in use, and so can support many different modes of operation as follows: MICROPHONE INPUTS Two microphone inputs are provided, allowing for either a differential microphone input or a single ended microphone to be connected. These inputs have a user programmable gain range of -12dB to +35.25dB using internal resistors. After the input PGA stage comes a boost stage which can add a further 20dB of gain. A microphone bias is output from the chip which can be used to bias the microphones. The signal routing can be configured to allow manual adjustment of mic levels, or to allow the ALC loop to control the level of mic signal that is transmitted. Total gain through the microphone paths of up to +55.25dB can be selected. PGA AND ALC OPERATION A programmable gain amplifier is provided in the input path to the ADC. This may be used manually or in conjunction with a mixed analogue/digital automatic level control (ALC) which keeps the recording volume constant. AUX INPUT The device includes a mono input, AUX, that can be used as an input for warning tones (beep) etc. The output from this circuit can be summed into the mono output and/or the speaker output paths, so allowing for mixing of audio with ‘backing music’ etc as required. This path can also be summed into the input in a flexible fashion, either to the input PGA as a second microphone input or as a line input. The configuration of this circuit, with integrated on-chip resistors allows several analogue signals to be summed into the single AUX input if required. ADC The mono ADC uses a multi-bit high-order over sampling architecture to deliver optimum performance with low power consumption. Various sample rates are supported, from the 8ks/s rate typically used in voice dictation, up to the 48ks/s rate used in high quality audio applications. HI-FI DAC The hi-fi DAC provides high quality audio playback suitable for all portable mono audio type applications. DIGITAL FILTERING Advanced Sigma Delta Converters are used along with digital decimation and interpolation filters to give high quality audio at sample rates from 8ks/s to 48ks/s. Application specific digital filters are also available which help to reduce the effect of specific noise sources such as wind noise or narrowband noise from other parts of the system. The filters include a programmable ADC high pass filter and four fully programmable ADC notch filters. OUTPUT MIXING AND VOLUME ADJUST Flexible mixing is provided on the outputs of the device; a mixer is provided for the speaker outputs, and an additional mono summer for the mono output. These mixers allow the output of the DAC, the output of the ADC volume control and the Auxiliary input to be combined. The output volume can be adjusted using the integrated digital volume control and there is additional analogue gain adjustment capability on the speaker output. AUDIO INTERFACES The WM8940 has a standard audio interface, to support the transmission of audio data to and from the chip. This interface is a 4 wire standard audio interface which supports a number of audio data formats including I2S, DSP Mode, MSB-First, left justified and MSB-First, right justified, and can operate in master or slave modes.

w Pre-Production, Rev 3.0, February 2007 CONTROL INTERFACES To allow full software control over all its features, the WM8940 supports 2 or 3 wire control interface. It is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. The selection between 2-wire mode and 3-wire mode is determined by the state of the MODE pin. If MODE is high then 3-wire control mode is selected, if MODE is low then 2- wire control mode is selected. In 2 wire mode, only slave operation is supported, and the address of the device is fixed as 0011010. CLOCKING SCHEMES WM8940 offers the normal audio DAC clocking scheme operation, where 256fs MCLK is provided to the DAC/ADC. However, a PLL is also included which may be used to generate the internal master clock frequency in the event that this is not available from the system controller. This PLL uses an input clock, typically the 12MHz USB or ilink clock, to generate high quality audio clocks. If this PLL is not required for generation of these clocks, it can be reconfigured to generate alternative clocks which may then be output on the CLKOUT pin and used elsewhere in the system. POWER CONTROL The design of the WM8940 has given much attention to power consumption without compromising performance. It operates at low supply voltages, and includes the facility to power off any unused parts of the circuitry under software control. As a power saving measure, ADC or DAC logic in the DSP core is held in its last enabled state when the ADC or DAC is disabled. In order to prevent pops and clicks on restart due to residual data in the filters, the master clock must remain for at least 64 input samples after the ADC or DAC has been disabled. INPUT SIGNAL PATH The WM8940 has 3 flexible analogue inputs: two microphone inputs, and an auxiliary input. These inputs can be used in a variety of ways. The input signal path before the ADC has a flexible PGA block which then feeds into a gain boost/mixer stage. MICROPHONE INPUTS The WM8940 can accommodate a variety of microphone configurations including single ended and differential inputs. The inputs through the MICN, MICP and optionally AUX pins are amplified through the input PGA as shown in Figure 6 . A pseudo differential input is the preferential configuration where the positive terminal of the input PGA is connected to the MICP input pin by setting MICP2INPPGA=1. The microphone ground should then be connected to MICN (when MICN2INPPGA=1) or optionally to AUX (when AUX2INPPGA=1) input pins. Alternatively a single ended microphone can be connected to the MICN input with MICN2INPPGA set to 1. The non-inverting terminal of the input PGA should be connected internally to VMID by setting MICP2INPPGA to 0. In pseudo-differential mode the larger signal should be input to MICP and the smaller (e.g. noisy ground connections) should be input to MICN.

w Pre-Production, Rev 3.0, February 2007 Figure 6 Microphone Input PGA Circuit (switch positions shown are for differential mic input) REGISTER ADDRESS BIT LABEL DEFAULT Select AUX amplifier output as input PGA signal source. 0=AUX not connected to input PGA 1=AUX connected to input PGA amplifier negative terminal. MICN2INPPGA Connect MICN to input PGA negative terminal. 0=MICN not connected to input PGA 1=MICN connected to input PGA amplifier negative terminal. R44 Input Control MICP2INPPGA Connect input PGA amplifier positive terminal to MICP or VMID. 0 = input PGA amplifier positive terminal connected to VMID 1 = input PGA amplifier positive terminal connected to MICP through variable resistor string Table 2 Input Control The input PGA is enabled by the IPPGAEN register bit. REGISTER ADDRESS BIT LABEL DEFAULT Input microphone PGA enable 0 = disabled 1 = enabled Table 3 Input PGA Enable Control

w Pre-Production, Rev 3.0, February 2007 INPUT PGA VOLUME CONTROL The input microphone PGA has a gain range from -12dB to +35.25dB in 0.75dB steps. The gain from the MICN input to the PGA output and from the AUX amplifier to the PGA output are always common and controlled by the register bits INPPGAVOL[5:0]. These register bits also affect the MICP pin when MICP2INPPGA=1. When the Automatic Level Control (ALC) is enabled the input PGA gain is then controlled automatically and the INPPGAVOL bits should not be used. REGISTER ADDRESS BIT LABEL DEFAULT Input PGA zero cross enable: 0=Update gain when gain register changes 1=Update gain on 1st zero cross after gain register write. INPPGAMUTE Mute control for input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). R45 Input PGA volume control 5:0 INPPGAVOL 010000 Input PGA volume 000000 = -12dB 000001 = -11.25db 010000 = 0dB 111111 = 35.25dB R32 ALC control 1 ALCSEL ALC function select: 0=ALC off (PGA gain set by INPPGAVOL register bits) 1=ALC on (ALC controls PGA gain) Table 4 Input PGA Volume Control AUXILLIARY INPUT An auxiliary input circuit (Figure 7) is provided which consists of an amplifier which can be configured either as an inverting buffer for a single input signal or as a mixer/summer for multiple inputs with the use of external resistors. The circuit is enabled by the register bit AUXEN. Figure 7 Auxiliary Input Circuit

w Pre-Production, Rev 3.0, February 2007 The AUXMODE register bit controls the auxiliary input mode of operation: In buffer mode (AUXMODE=0) the switch labelled AUXSW in Figure 7 is open and the signal at the AUX pin will be buffered and inverted through the aux circuit using only the internal components. In mixer mode (AUXMODE=1) the on-chip input resistor is bypassed, this allows the user to sum in multiple inputs with the use of external resistors. When used in this mode there will be gain variations through this path from part to part due to the variation of the internal 20kΩ resistors relative to the higher tolerance external resistors. REGISTER ADDRESS BIT LABEL DEFAULT Auxiliary input buffer enable 0 = OFF 1 = ON R44 Input control AUXMODE 0 = inverting buffer 1 = mixer (on-chip input resistor bypassed) Table 5 Auxiliary Input Buffer Control INPUT BOOST The input BOOST circuit has 3 selectable inputs: the input microphone PGA output, the AUX amplifier output and the MICP input pin (when not using a differential microphone configuration). These three inputs can be mixed together and have individual gain boost/adjust as shown in Figure Figure 8 Input Boost Stage The input PGA path can have a +20dB boost (PGABOOST=1) a 0dB pass through (PGABOOST=0) or be completely isolated from the input boost circuit (INPPGAMUTE=1).

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT Mute control for input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). R47 Input BOOST control PGABOOST 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. Table 6 Input BOOST Stage Control The Auxiliary amplifier path to the BOOST stage is controlled by the AUX2BOOSTVOL[2:0] register bits. When AUX2BOOSTVOL=000 this path is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB. The MICP path to the BOOST stage is controlled by the MICP2BOOSTVOL[2:0] register bits. When MICP2BOOSTVOL=000 this input pin is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB. REGISTER ADDRESS BIT LABEL DEFAULT 6:4 MICP2BOOSTVOL 000 Controls the MICP pin to the input boost stage (NB, when using this path set MICP2INPPGA=0): 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage 111=+6dB gain through boost stage R47 Input BOOST control 2:0 AUX2BOOSTVOL 000 Controls the auxiliary amplifier to the input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage 111=+6dB gain through boost stage Table 7 Input BOOST Stage Control The BOOST stage is enabled under control of the BOOSTEN register bit. REGISTER ADDRESS BIT LABEL DEFAULT 0 = Boost stage OFF 1 = Boost stage ON Table 8 Input BOOST Enable Control MICROPHONE BIASING CIRCUIT The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. Refer to the Applications Information section for recommended external components. The MICBIAS voltage can be altered via the MBVSEL register bit. When MBVSEL=0, MICBIAS=0.9*AVDD and when MBVSEL=1, MICBIAS=0.65*AVDD. The output can be enabled or disabled using the MICBEN control bit.

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT 0 = OFF (high impedance output) 1 = ON Table 9 Microphone Bias Enable REGISTER ADDRESS BIT LABEL DEFAULT Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.65 * AVDD Table 10 Microphone Bias Voltage Control The internal MICBIAS circuitry is shown in Figure 9. Note that the maximum source current capability for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit the MICBIAS current to 3mA. Figure 9 Microphone Bias Schematic ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8940 uses a multi-bit, over sampled sigma-delta ADC channel. The use of multi-bit feedback and high over sampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is 1.0Vrms. Any voltage greater than full scale may overload the ADC and cause distortion. ADC DIGITAL FILTERS The ADC filters perform true 24 bit signal processing to convert the raw multi-bit over sampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital filter path is illustrated in . AGND MBVSEL=0 MICBIAS = 1.8 x VMID = 0.9 X AVDD VMID internal resistor internal resistor MB MBVSEL=1 MICBIAS = 1.3 x VMID = 0.65 X AVDD

w Pre-Production, Rev 3.0, February 2007 Figure 10 ADC Digital Filter Path The ADC is enabled by the ADCEN register bit. REGISTER ADDRESS BIT LABEL DEFAULT 0 = ADC disabled 1 = ADC enabled Table 11 ADC Enable The polarity of the output signal can also be changed under software control using the ADCPOL register bit. REGISTER ADDRESS BIT LABEL DEFAULT 0=normal 1=inverted Table 12 ADC Polarity SELECTABLE HIGH PASS FILTER A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown in Table 14. REGISTER ADDRESS BIT LABEL DEFAULT 0=disabled 1=enabled HPFAPP Select audio mode or application mode 0=Audio mode (1st order, fc = ~3.7Hz) 1=Application mode (2nd order, fc = HPFCUT) R14 ADC Control 6:4 HPFCUT 000 Application mode cut-off frequency See Table 14 for details. Table 13 ADC Filter Select

w Pre-Production, Rev 3.0, February 2007 FS (KHZ) SR=101/100 SR=011/010 SR=001/000 HPFCUT 11.025 22.05 44.1 000 113 122 113 122 113 122 001 102 141 153 102 141 153 102 141 153 010 131 180 156 131 180 156 131 180 156 011 163 225 245 163 225 245 163 225 245 100 204 281 306 204 281 306 204 281 306 101 261 360 392 261 360 392 261 360 392 110 327 450 490 327 450 490 327 450 490 111 408 563 612 408 563 612 408 563 612 Table 14 High Pass Filter Cut-off Frequencies (HPFAPP=1) Note that the High Pass filter values (when HPFAPP=1) work on the basis that the SR register bits are set correctly for the actual sample rate as shown in Table 14. PROGRAMMABLE NOTCH FILTERS Four programmable notch filters are provided. These filters have a programmable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits NFx_A0[13:0] and NFx_A1[13:0]. Notch Filter 3 can also be programmed as a 1st order low pass filter. Because these coefficient values require two register writes to set up there is an NFx_UP (Notch Filter Update) flag for each filter which should be set only when both A0 and A1 for the filter have been set. The notch filters can be individually enabled, using the corresponding NFx_EN register bit, as can be seen in Figure 11. Figure 11 Labelling of Notch Filters and Arrangement of Notch Filter Enables REGISTER ADDRESS BIT LABEL DEFAULT NF0_UP Notch filter 0 update. The notch filter 0 values used internally only update when one of the NF0_UP bits is set high. NF0_EN Notch filter 0 enable: 0=Disabled 1=Enabled R16 Notch Filter 0A 13:0 NF0_A0 Notch Filter 0 a0 coefficient NF0_UP Notch filter 0 update. The notch filter 0 values used internally only update when one of the NF0_UP bits is set high. R17 Notch Filter 0B 13:0 NF0_A1 Notch Filter 0 a1 coefficient Table 15 Notch Filter 0 Function

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT NF1_UP Notch filter 1 update. The notch filter 1 values used internally only update when one of the NFU bits is set high. NF1_EN Notch Filter 1 enable. 0=Disabled 1=Enabled R18 Notch Filter 1A 13:0 NF1_A0 Notch Filter 1 a0 coefficient NF1_UP Notch filter 1 update. The notch filter 1 values used internally only update when one of the NFU bits is set high. R19 Notch Filter 1B 13:0 NF1_A1 Notch Filter 1 a1 coefficient Table 16 Notch Filter 1 Function REGISTER ADDRESS BIT LABEL DEFAULT NF2_UP Notch filter 2 update. The notch filter 2 values used internally only update when one of the NFU bits is set high. NF2_EN Notch Filter 2 enable. 0=Disabled 1=Enabled R20 Notch Filter 2A 13:0 NF2_A0 Notch Filter 2 a0 coefficient NF2_UP Notch filter 2 update. The notch filter 2 values used internally only update when one of the NFU bits is set high. R21 Notch Filter 2B 13:0 NF2_A1 Notch Filter 2 a1 coefficient Table 17 Notch Filter 2 Function REGISTER ADDRESS BIT LABEL DEFAULT NF3_UP Notch filter 3 update. The notch filter 3 values used internally only update when one of the NFU bits is set high. NF3_EN Notch Filter 3 enable. 0=Disabled 1=Enabled R22 Notch Filter 3A 13:0 NF3_A0 Notch Filter 3 a0 coefficient NF3_UP Notch filter 3 update. The notch filter 3 values used internally only update when one of the NFU bits is set high. NF3_LP Notch Filter 3 mode select 0 = Notch Filter mode 1 = Low Pass Filter mode R23 Notch Filter 3B 13:0 NF3_A1 Notch Filter 3 a1 coefficient Table 18 Notch Filter 3 Function The notch filter coefficients must be entered using a sign / magnitude notation. The MSB of the 14- bit register word (NFx_Ax[13]) is reserved for the sign part, leaving the 13 remaining bits for the magnitude part. The notch filter coefficients are calculated as follows:

w Pre-Production, Rev 3.0, February 2007 tan( tan( b b w w a cos( w a a Where: s c f f w π s b b f f w fc = centre frequency in Hz, fb = -3dB bandwidth in Hz, fs = sample frequency in Hz The actual register values can be determined from the coefficients as follows: NFn_A0 = -a0 x 213 NFn_A1 = -a1 x 212 To configure Notch Filter 3 as a 1st order low pass filter, set the NF3_LP bit to 1 and calculate the coefficients as follows: 0 = a tan( tan( c c w w a Where: s c c f f w fc = cutoff frequency in Hz, fs = sample frequency in Hz The actual register values can be determined from the coefficients as follows: NF3_A0 = 0 NF3_A1 = -a1 x212 DIGITAL ADC VOLUME CONTROL The output of the ADCs can be digitally attenuated over a range from –127dB to 0dB in 0.5dB steps. The gain for a given eight-bit code X is given by: Gain = 0.5 x (x–255) dB for 1 ≤ x ≤ 255, MUTE for x = 0 REGISTER ADDRESS BIT LABEL DEFAULT 7:0 ADCVOL [7:0] 11111111 ( 0dB ) ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB Table 19 ADC Volume

w Pre-Production, Rev 3.0, February 2007 INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) The WM8940 has an automatic PGA gain control circuit, which can function as an input peak limiter or as an automatic level control (ALC). The Automatic Level Control (ALC) provides continuous adjustment of the input PGA in response to the amplitude of the input signal. A digital peak detector monitors the input signal amplitude and compares it to a register defined threshold level (ALCLVL). If the signal is below the threshold, the ALC will increase the gain of the PGA at a rate set by ALCDCY. If the signal is above the threshold, the ALC will reduce the gain of the PGA at a rate set by ALCATK. The ALC has two modes selected by the ALCMODE register: normal mode and peak limiter mode. The ALC/limiter function is enabled by setting the register bit R32[8] ALCSEL. REGISTER ADDRESS BIT LABEL DEFAULT 2:0 ALCMIN [2:0] 000 (-12dB) Set minimum gain of PGA 000 = -12dB 001 = -6dB 010 = 0dB 011 = +6dB 100 = +12dB 101 = +18dB 110 = +24dB 111 = +30dB 5:3 ALCMAX [2:0] 111 (+35.25dB) Set Maximum Gain of PGA 111 = +35.25dB 110 = +29.25dB 101 = +23.25dB 100 = +17.25dB 011 = +11.25dB 010 = +5.25dB 001 = -0.75dB 000 = -6.75dB R32 (20h) ALC Control 1 ALCSEL ALC function select 0 = ALC disabled 1 = ALC Enabled R33 (21h) ALC Control 2 3:0 ALCLVL [3:0] 1011 (-6dB) ALC target – sets signal level at ADC input 1111 = -1.5dBFS 1110 = -1.5dBFS 1101 = -3dBFS 1100 = -4.5dBFS 1011 = -6dBFS 1010 = -7.5dBFS 1001 = -9dBFS 1000 = -10.5dBFS 0111 = -12dBFS 0110 = -13.5dBFS 0101 = -15dBFS 0100 = -16.5dBFS 0011 = -18dBFS 0010 = -19.5dBFS 0001 = -21dBFS 0000 = -22.5dBFS

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT 7:4 ALCHLD [3:0] 0000 (0ms) ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms 0011 = 10.66ms 0100 = 21.32ms 0101 = 42.64ms 0110 = 85.28ms 0111 = 0.17s 1000 = 0.34s 1001 = 0.68s 1010 or higher = 1.36s ALCMODE Determines the ALC mode of operation: 0 = ALC mode (Normal Operation) 1 = Limiter mode. Decay (gain ramp-up) time (ALCMODE ==0) Per step Per 6dB 90% of range 0000 410us 3.38ms 23.6ms 0001 820us 6.56ms 47.2ms 0010 1.64ms 13.1ms 94.5ms … (time doubles with every step) 0011 (26ms/6dB) 1010 or higher 420ms 3.36s 24.2s Decay (gain ramp-up) time (ALCMODE ==1) Per step Per 6dB 90% of range 0000 90.8us 726us 5.23ms 0001 182us 1.45ms 10.5ms 0010 363us 2.91ms 20.9ms … (time doubles with every step) 7:4 ALCDCY [3:0] 0011 (5.8ms/6dB) 1010 93ms 744ms 5.36s ALC attack (gain ramp-down) time (ALCMODE == 0) Per step Per 6dB 90% of range 0000 104us 832us 6ms 0001 208us 1.66ms 12ms 0010 416us 3.33ms 24ms … (time doubles with every step) 0010 (3.3ms/6dB) 1010 or higher 106ms 852ms 6.13s ALC attack (gain ramp-down) time (ALCMODE == 1) Per step Per 6dB 90% of range 0000 22.7us 182.4us 1.31ms 0001 45.4us 363us 2.62ms 0010 90.8us 726us 5.23ms R34 (22h) ALC Control 3 3:0 ALCATK [3:0] 0010 (726us/6dB) … (time doubles with every step)

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT 23.2ms 186ms 1.34s R42 (2Ah) ALC Control 4 ALCZC 0 (zero cross off) ALC uses zero cross detection circuit. 0 = Disabled (recommended) 1 = Enabled Table 20 ALC Control Registers When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update must be made by writing to the INPPGAVOLL/R register bits. NORMAL MODE In normal mode, the ALC will attempt to maintain a constant signal level by increasing or decreasing the gain of the PGA. The following diagram shows an example of this. Figure 12 ALC Normal Mode Operation

w Pre-Production, Rev 3.0, February 2007 LIMITER MODE In limiter mode, the ALC will reduce peaks that go above the threshold level, but will not increase the PGA gain beyond the starting level. The starting level is the PGA gain setting when the ALC is enabled in limiter mode. If the ALC is started in limiter mode, this is the gain setting of the PGA at start-up. If the ALC is switched into limiter mode after running in ALC mode, the starting gain will be the gain at switchover. The diagram below shows an example of limiter mode. Figure 13 ALC Limiter Mode Operation ATTACK AND DECAY TIMES The attack and decay times set the update times for the PGA gain. The attack time is the time constant used when the gain is reducing. The decay time is the time constant used when the gain is increasing. In limiter mode, the time constants are faster than in ALC mode. The time constants are shown below in terms of a single gain step, a change of 6dB and a change of 90% of the PGAs gain range. Note that, these times will vary slightly depending on the sample rate used (specified by the SR register).

w Pre-Production, Rev 3.0, February 2007 NORMAL MODE ALCMODE = 0 (Normal Mode) ALCATK tATK tATK6dB tATK90% 0000 104µs 832µs 6ms 0001 208µs 1.66ms 12ms 0010 416µs 3.33ms 24ms 0011 832µs 6.66ms 48ms 0100 1.66ms 13.3ms 96ms 0101 3.33ms 26.6ms 192ms 0110 6.66ms 53.2ms 384ms 0111 13.3ms 106ms 767ms 1000 26.6ms 213.2ms 1.53s 1001 53.2ms 426ms 3.07s 1010 106ms 852ms 6.13s Attack Time (s) ALCMODE = 0 (Normal Mode) ALCDCY tDCY tDCY6dB tDCY90% 0000 410µs 3.28ms 23.6ms 0001 820µs 6.56ms 47.2ms 0010 1.64ms 13.1ms 94.5ms 0011 3.28ms 26.2ms 189ms 0100 6.56ms 52.5ms 378ms 0101 13.1ms 105ms 756ms 0110 26.2ms 210ms 1.51s 0111 52.5ms 420ms 3.02s 1000 105ms 840ms 6.05s 1001 210ms 1.68s 12.1s 1010 420ms 3.36s 24.2s Decay Time (s) Table 21 ALC Normal Mode (Attack and Decay times)

w Pre-Production, Rev 3.0, February 2007 LIMITER MODE ALCMODE = 1 (Limiter Mode) ALCATK tATKLIM tATKLIM6dB tATKLIM90% 0000 22.7µs 182µs 1.31ms 0001 45.4µS 363µs 2.62ms 0010 90.8µS 726µs 5.23ms 0011 182µS 1.45ms 10.5ms 0100 363µS 2.91ms 20.9ms 0101 726µS 5.81ms 41.8ms 0110 1.45ms 11.6ms 83.7ms 0111 2.9ms 23.2ms 167ms 1000 5.81ms 46.5ms 335ms 1001 11.6ms 93ms 669ms 1010 23.2ms 186ms 1.34s Attack Time (s) ALCMODE = 1 (Limiter Mode) ALCDCY tDCYLIM tDCYLIM6dB tDCYLIM90% 0000 90.8µs 726µs 5.23ms 0001 182µS 1.45ms 10.5ms 0010 363µS 2.91ms 20.9ms 0011 726µS 5.81ms 41.8ms 0100 1.45ms 11.6ms 83.7ms 0101 2.91ms 23.2ms 167ms 0110 5.81ms 46.5ms 335ms 0111 11.6ms 93ms 669ms 1000 23.2ms 186ms 1.34s 1001 46.5ms 372ms 2.68s 1010 93ms 744ms 5.36s Attack Time (s) Table 22 ALC Limiter Mode (Attack and Decay times)

w Pre-Production, Rev 3.0, February 2007 MINIMUM AND MAXIMUM GAIN The ALCMIN and ALCMAX register bits set the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is not enabled. REGISTER ADDRESS BIT LABEL DEFAULT 5:3 ALCMAX 111 Set Maximum Gain of PGA R32 ALC Control 1 2:0 ALCMIN 000 Set minimum gain of PGA Table 23 ALC Max/Min Gain In normal mode, ALCMAX sets the maximum boost which can be applied to the signal. In limiter mode, ALCMAX will normally have no effect (assuming the starting gain value is less than the maximum gain specified by ALCMAX) because the maximum gain is set at the starting gain level. ALCMIN sets the minimum gain value which can be applied to the signal. Figure 14 ALC Min/Max Gain ALCMAX Maximum Gain (dB) 111 35.25 110 29.25 101 23.25 100 17.25 011 11.25 010 5.25 001 -0.75 000 -6.75 Table 24 ALC Max Gain Values

w Pre-Production, Rev 3.0, February 2007 ALCMIN Minimum Gain (dB) 000 -12 001 010 011 100 101 110 111 Table 25 ALC Min Gain Values Note that if the ALC gain setting strays outside the ALC operating range, either by starting the ALC outside of the range or changing the ALCMAX or ALCMIN settings during operation, the ALC will immediately adjust the gain to return to the ALC operating range. It is recommended that the ALC starting gain is set between the ALCMAX and ALCMIN limits. ALC HOLD TIME (NORMAL MODE ONLY) In Normal mode, the ALC has an adjustable hold time which sets a time delay before the ALC begins its decay phase (gain increasing). The hold time is set by the ALCHLD register. REGISTER ADDRESS BIT LABEL DEFAULT 7:4 ALCHLD 0000 ALC hold time before gain is increased. Table 26 ALC Hold Time If the hold time is exceeded this indicates that the signal has reached a new average level and the ALC will increase the gain to adjust for that new average level. If the signal goes above the threshold during the hold period, the hold phase is abandoned and the ALC returns to normal operation.

w Pre-Production, Rev 3.0, February 2007 Figure 15 ALCLVL

w Pre-Production, Rev 3.0, February 2007 Figure 16 ALC Hold Time ALCHLD tHOLD (s) 0000 0001 2.67ms 0010 5.34ms 0011 10.7ms 0100 21.4ms 0101 42.7ms 0110 85.4ms 0111 171ms 1000 342ms 1001 684ms 1010 1.37s Table 27 ALC Hold Time Values

w Pre-Production, Rev 3.0, February 2007 PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ALCATK = 0000), until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled. Note: If ALCATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed to prevent clipping when long attack times are used. NOISE GATE (NORMAL MODE ONLY) When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise pumping”, i.e. loud hissing noise during silence periods. The WM8940 has a noise gate function that prevents noise pumping by comparing the signal level at the input pins against a noise gate threshold, NGTH. The noise gate cuts in when: Signal level at ADC [dBFS] < NGTH [dBFS] + PGA gain [dB] + Mic Boost gain [dB] This is equivalent to: Signal level at input pin [dBFS] < NGTH [dBFS] The PGA gain is then held constant (preventing it from ramping up as it normally would when the signal is quiet). The table below summarises the noise gate control register. The NGTH control bits set the noise gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps. Levels at the extremes of the range may cause inappropriate operation, so care should be taken with set–up of the function. The noise gate only operates in conjunction with the ALC and cannot be used in limiter mode. REGISTER ADDRESS BIT LABEL DEFAULT 2:0 NGTH 000 Noise gate threshold: 000 = -39dB 001 = -45dB 010 = -51db 011 = -57dB 100 = -63dB 101 = -69dB 110 = -75dB 111 = -81dB R35 (23h) ALC Noise Gate Control NGATEN Noise gate function enable 1 = enable 0 = disable Table 28 ALC Noise Gate Control

w Pre-Production, Rev 3.0, February 2007 The diagrams below show the response of the system to the same signal with and without noise gate. Figure 17 ALC Operation Above Noise Gate Threshold

w Pre-Production, Rev 3.0, February 2007 Figure 18 Noise Gate Operation

w Pre-Production, Rev 3.0, February 2007 OUTPUT SIGNAL PATH The WM8940 output signal paths consist of digital application filters, up-sampling filters, a Hi-Fi DAC, analogue mixers, speaker and mono output drivers. The digital filters and DAC are enabled by bit DACEN. The mixers and output drivers can be separately enabled by individual control bits (see Analogue Outputs). Thus it is possible to utilise the analogue mixing and amplification provided by the WM8940, irrespective of whether the DACs are running or not. The WM8940 DAC receives digital input data on the DACDAT pin. The digital filter block processes the data to provide the following functions: Digital volume control A digital peak limiter. Sigma-Delta Modulation The high performance sigma-delta audio DAC converts the digital data into an analogue signal. Figure 19 DAC Digital Filter Path The analogue output from the DAC can then be mixed with the AUX analogue input and the ADC analogue input. The mix is fed to the output drivers, SPKOUTP/N, and MONOOUT. MONOOUT: can drive a 16Ω or 32Ω headphone or line output or can be a buffered version of VMID (When MONOMUTE=1). SPKOUTP/N: can drive a 16Ω or 32Ω stereo headphone or stereo line output, or an 8Ω BTL mono speaker. DIGITAL HI-FI DAC VOLUME CONTROL The signal volume from each Hi-Fi DAC can be controlled digitally. The gain and attenuation range is –127dB to 0dB in 0.5dB steps. The level of attenuation for an eight-bit code X is given by: 0.5 × (X-255) dB for 1 ≤ X ≤ 255; MUTE for X = 0 REGISTER ADDRESS BIT LABEL DEFAULT 7:0 DACVOL [7:0] 11111111 ( 0dB ) DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB Table 29 DAC Volume DIGITAL AUDIO INTERFACE DIGITAL GAIN DIGITAL FILTERS INTERP SDM DAC DIGITAL PEAK LIMITER DAC DIGITAL FILTERS

w Pre-Production, Rev 3.0, February 2007 HI-FI DIGITAL TO ANALOGUE CONVERTER (DAC) The DAC is enabled by the DACEN register bit. REGISTER ADDRESS BIT LABEL DEFAULT 0 = DAC disabled 1 = DAC enabled Table 30 DAC Enable The WM8940 also has a Soft Mute function, which gradually attenuates the volume of the digital signal to zero. When removed, the gain will step back up to the digital gain setting. This function is disabled by default. To play back an audio signal, it must first be disabled by setting the DACMU bit to zero. REGISTER ADDRESS BIT LABEL DEFAULT 0 = DACMU disabled 1 = DACMU enabled Table 31 DAC Control Register The digital audio data is converted to over sampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bit stream data enters a multi-bit, sigma-delta DAC, which converts it to a high quality analogue audio signal. The multi-bit DAC architecture reduces high frequency noise and sensitivity to clock jitter. The DAC output defaults to non-inverted. Setting DACPOL will invert the DAC output phase. AUTOMUTE The DAC has an automute function which applies an analogue mute when 1024 consecutive zeros are detected. The mute is released as soon as a non-zero sample is detected. Automute can be enabled using the AMUTE control bit. REGISTER ADDRESS BIT LABEL DEFAULT 0 = auto mute disabled 1 = auto mute enabled Table 32 DAC Auto Mute Control Register

w Pre-Production, Rev 3.0, February 2007 DAC OUTPUT LIMITER The WM8940 has a digital output limiter function. The operation of this is shown in Figure 20. In this diagram the upper graph shows the envelope of the input/output signals and the lower graph shows the gain characteristic. Figure 20 DAC Digital Limiter Operation The limiter has a programmable upper threshold which is close to 0dB. Referring to Table 33, in normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the limiter. Signals above the upper threshold are attenuated at a specific attack rate (set by the LIMATK register bits) until the signal falls below the threshold. The limiter also has a lower threshold 1dB below the upper threshold. When the signal falls below the lower threshold the signal is amplified at a specific decay rate (controlled by LIMDCY register bits) until a gain of 0dB is reached. Both threshold levels are controlled by the LIMLVL register bits. The upper threshold is 0.5dB above the value programmed by LIMLVL and the lower threshold is 0.5dB below the LIMLVL value. VOLUME BOOST The limiter has programmable upper gain which boosts signals below the threshold to compress the dynamic range of the signal and increase its perceived loudness. This operates as an ALC function with limited boost capability. The volume boost is from 0dB to +12dB in 1dB steps, controlled by the LIMBOOST register bits. The output limiter volume boost can also be used as a stand alone digital gain boost when the limiter is disabled.

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT Enable the DAC digital limiter: 0=disabled 1=enabled 7:4 LIMDCY 0011 Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate: 0000=750us 0001=1.5ms 0010=3ms 0011=6ms 0100=12ms 0101=24ms 0110=48ms 0111=96ms 1000=192ms 1001=384ms 1010=768ms 1011 to 1111=1.536s R24 DAC digital limiter control 1 3:0 LIMATK 0010 Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate. 0000=94us 0001=188s 0010=375us 0011=750us 0100=1.5ms 0101=3ms 0110=6ms 0111=12ms 1000=24ms 1001=48ms 1010=96ms 1011 to 1111=192ms R25 DAC digital limiter control 2 6:4 LIMLVL 000 Programmable signal threshold level (determines level at which the limiter starts to operate) 000=-1dB 001=-2dB 010=-3dB 011=-4dB 100=-5dB 101 to 111=-6dB

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT 3:0 LIMBOOST 0000 Limiter volume boost (can be used as a stand alone volume boost when LIMEN=0): 0000 = 0dB 0001 = +1dB 0010 = +2dB 0011 = +3dB 0100 = +4dB 0101 = +5dB 0110 = +6dB 0111 = +7dB 1000 = +8dB 1001 = +9dB 1010 = +10dB 1011 = +11dB 1100 = +12dB 1101 to 1111 = reserved Table 33 DAC Digital Limiter Control ANALOGUE OUTPUTS The WM8940 has a single MONO output and two outputs SPKOUTP and SPOUTN for driving a mono BTL speaker. These analogue output stages are supplied from SPKVDD and are capable of driving up to 1V rms signals. SPKOUTP/SPKOUTN OUTPUTS The SPKOUT pins can drive a single bridge tied 8Ω speaker or two headphone loads of 16Ω or 32Ω or a line output (see Headphone Output and Line Output sections, respectively). The signal to be output on SKPKOUT comes from the Speaker Mixer circuit and can be any combination of the DAC output, the Bypass path (output of the boost stage) and the AUX input. The SPKOUTP/N volume is controlled by the SPKVOL register bits. Note that gains over 0dB may cause clipping if the signal is large. The SPKMUTE register bit causes the speaker outputs to be muted (the output DC level is driven out). The output pins remains at the same DC level (VMIDOP), so that no click noise is produced when muting or un-muting. The SPKOUTN pin always drives out an inverted version of the SPKOUTP signal. REGISTER ADDRESS BIT LABEL DEFAULT Output of auxiliary amplifier to speaker mixer input 0 = not selected 1 = selected BYP2SPK Bypass path (output of input boost stage) to speaker mixer input 0 = not selected 1 = selected R50 Speaker mixer control DAC2SPK Output of DAC to speaker mixer input 0 = not selected 1 = selected R54 Bypass path attenuation control SPKATTN Attenuation control for bypass path (output of input boost stage) to speaker mixer input 0 = 0dB 1 = -10dB Table 34 Speaker Mixer Control

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT Speaker Volume control zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately SPKMUTE Speaker output mute enable 0=Speaker output enabled 1=Speaker output muted (VMIDOP) R54 Speaker volume control 5:0 SPKVOL [5:0] 111001 (0dB) Speaker Volume Adjust 111111 = +6dB 111110 = +5dB … (1.0 dB steps) 111001=0dB 000000=-57dB Table 35 SPKOUT Volume Control ZERO CROSS TIMEOUT A zero-cross timeout function is also provided so that if zero cross is enabled on the input or output PGAs the gain will automatically update after a timeout period if a zero cross has not occurred. This is enabled by setting SLOWCLKEN. The timeout period is either 31Hz or 47Hz. REGISTER ADDRESS BIT LABEL DEFAULT Slow clock enable. Used for both the jack insert detect de-bounce circuit and the zero cross timeout. 0 = slow clock disabled 1 = slow clock enabled Table 36 Timeout Clock Enable Control MONO MIXER AND OUTPUT The MONOOUT pin can drive a 16Ω or 32Ω headphone or a line output or be used as a DC reference for a headphone output (see Headphone Output section). It can be selected to drive out any combination of DAC, Bypass (output of input BOOST stage) and AUX. This output is enabled by setting bit MONOEN.

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT Attenuation control for bypass path (output of input boost stage) to mono mixer input 0 = 0dB 1 = -10dB MONOMUTE 0=No mute 1=Output muted. During mute the mono output will output VMID which can be used as a DC reference for a headphone out. AUX2MONO Output of Auxilary amplifier to mono mixer input: 0 = not selected 1 = selected BYP2MONO Bypass path (output of input boost stage) to mono mixer input 0 = non selected 1 = selected R56 Mono mixer control DAC2MONO Output of DAC to mono mixer input 0 = not selected 1 = selected Table 37 Mono Mixer Control ENABLING THE OUTPUTS Each analogue output of the WM8940 can be separately enabled or disabled. The analogue mixer associated with each output has a separate enable. All outputs are disabled by default. To save power, unused parts of the WM8940 should remain disabled. Outputs can be enabled at any time, but it is not recommended to do so when BUFIO is disabled (BUFIOEN=0), as this may cause pop noise (see “POP Minimisation” section). REGISTER ADDRESS BIT LABEL DEFAULT Analogue amplifiers bias enable Power management 1 BUFIOEN VMID buffer enable MONOEN MONOOUT enable SPKNEN SPKOUTN enable SPKPEN SPKOUTP enable MONOMIXEN Mono mixer enable Power management 3 SPKMIXEN Speaker Mixer enable Note: All “Enable” bits are 1 = ON, 0 = OFF Table 38 Output Stages Power Management Control UNUSED ANALOGUE INPUTS/OUTPUTS Whenever an analogue input/output is disabled, it remains connected to AVDD/2 through a resistor. This helps to prevent pop noise when the output is re-enabled. The resistance between the voltage buffer and the output pins can be controlled using the VROI control bit. The default impedance is low, so that any capacitors on the outputs can charge up quickly at start-up. If a high impedance is desired for disabled outputs, VROI can then be set to 1, increasing the resistance to about 30kΩ.

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT VREF (AVDD/2) to analogue output resistance 0: approx 1kΩ 1: approx 30 kΩ Table 39 Disabled Outputs to VREF Resistance A dedicated buffer is available for tying off unused analogue I/O pins as shown in Figure 21. This buffer can be enabled using the BUFIOEN register bit. Table 40 summarises the tie-off options for the speaker and mono output pins. Figure 21 Unused Input/Output Pin Tie-off Buffers MONOEN/ SPKN/PEN VROI OUTPUT CONFIGURATION 1kΩ tieoff to AVDD/2 30kΩ tieoff to AVDD/2 X Output enabled (DC level=AVDD/2) Table 40 Unused Output Pin Tie-off Options OUTPUT SWITCH When the device is configured with a 2-wire interface the CSB/GPIO pin can be used as a switch control input to automatically disable the speaker outputs and enable the mono output. As an example when a line is plugged into a jack socket. In this mode, enabled by setting GPIOSEL=001, pin CSB/GPIO switches between mono and speaker outputs (e.g. when pin 12 is connected to a mechanical switch in the headphone socket to detect plug-in). The GPIOPOL bit reverses the polarity of the CSB/GPIO input pin. Note that the speaker outputs and the mono output must be enabled for this function to work (see Table 41). The CSB/GPIO pin has an internal de-bounce circuit when in this mode in order to prevent the output enables from toggling multiple times due to input glitches. This de-bounce circuit is clocked from a slow clock with period 221 x MCLK, enabled using the SLOWCLKEN register bit.

w Pre-Production, Rev 3.0, February 2007 GPIOPOL CSB/GPIO SPKNEN/ SPKPEN MONOEN SPEAKER ENABLED MONO OUTPUT ENABLED X No No X Yes No X No No X No Yes X No No X No Yes X No No X Yes No Table 41 Output Switch Operation (GPIOSEL=001) THERMAL SHUTDOWN The speaker outputs can drive very large currents. To protect the WM8940 from overheating a thermal shutdown circuit is included. The thermal shutdown can be configured to produce an interrupt when the device reaches approximately 125oC. See General Purpose Input/Output section. REGISTER ADDRESS BIT LABEL DEFAULT 0 : thermal shutdown disabled 1 : thermal shutdown enabled Table 42 Thermal Shutdown SPEAKER OUTPUT SPKOUTP/N can differentially drive a mono 8Ω Bridge Tied Load (BTL) speaker as shown below. Figure 22 Speaker Output Connection

w Pre-Production, Rev 3.0, February 2007 DIGITAL AUDIO INTERFACES The audio interface has four pins: ADCDAT: ADC data output DACDAT: DAC data input FRAME: Data alignment clock BCLK: Bit clock, for synchronisation The clock signals BCLK, and FRAME can be outputs when the WM8940 operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). Four different audio data formats are supported: Left justified Right justified I2S DSP mode A / B All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for timing information. MASTER AND SLAVE MODE OPERATION The WM8940 audio interface may be configured as either master or slave. As a master interface device the WM8940 generates BCLK and FRAME and thus controls sequencing of the data transfer on ADCDAT and DACDAT. To set the device to master mode register bit MS should be set high. In slave mode (MS=0), the WM8940 responds with data to clocks it receives over the digital audio interfaces. AUDIO DATA FORMATS In Left Justified mode, the MSB is available on the first rising edge of BCLK following an FRAME transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each FRAME transition. Figure 25 Left Justified Audio Interface (assuming n-bit word length) In Right Justified mode, the LSB is available on the last rising edge of BCLK before a FRAME transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each FRAME transition.

w Pre-Production, Rev 3.0, February 2007 LEFT CHANNEL RIGHT CHANNEL LRC BCLK DACDAT / ADCDAT n n-2 n-1 LSB MSB n n-2 n-1

1 BCLK

Input Word Length (WL) 1/fs falling edge can occur anywhere in this area Figure 29 DSP/PCM Mode Audio Interface (Mode B, FRAMEP=1) AUDIO INTERFACE CONTROL The register bits controlling audio format, word length and master / slave mode are summarised below. Register bit MS selects audio interface operation in master or slave mode. In Master mode BCLK, and FRAME are outputs. The frequency of BCLK and FRAME in master mode are controlled with BCLKDIV. These are divided down versions of master clock. This may result in short BCLK pulses at the end of a frame if there is a non-integer ratio of BCLKs to FRAME clocks. REGISTER ADDRESS BIT LABEL DEFAULT 0=normal 1=Input mono channel data output on both left and right channels BCP BCLK polarity 0=normal 1=inverted FRAMEP Frame clock polarity (for RJ, LJ and I2S formats) 0=normal 1=inverted DSP Mode control 1 = Configures interface so that MSB is available on 1st BCLK rising edge after FRAME rising edge 0 = Configures interface so that MSB is available on 2nd BCLK rising edge after FRAME rising edge 6:5 WL Word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits (see note) Audio interface control 4:3 FMT Audio interface Data Format Select: 00=Right Justified 01=Left Justified 10=I2S format 11= DSP/PCM mode

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT Controls whether DAC data appears in ‘right’ or ‘left’ phases of FRAME clock: 0=DAC data appear in ‘left’ phase of FRAME 1=DAC data appears in ‘right’ phase of FRAME ALRSWAP Controls whether ADC data appears in ‘right’ or ‘left’ phases of FRAME clock: 0=ADC data appear in ‘left’ phase of FRAME 1=ADC data appears in ‘right’ phase of FRAME Companding Control WL8

8 Bit Word Length Enable

Only recommended for use with companding 0=Word Length controlled by WL 1=8 bits Table 43 Audio Interface Control Note: Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected the device will operate in 24-bit mode. REGISTER ADDRESS BIT LABEL DEFAULT Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output 7:5 MCLKDIV 010 Sets the scaling for either the MCLK or PLL clock output (under control of CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 4:2 BCLKDIV 000 Configures the BCLK and FRAME output frequency, for use when the chip is master over BCLK. 000=divide by 1 (BCLK=MCLK) 001=divide by 2 (BCLK=MCLK/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved Clock generation control MS Sets the chip to be master over FRAME and BCLK 0=BCLK and FRAME clock are inputs 1=BCLK and FRAME clock are outputs generated by the WM8940 (MASTER) Table 44 Clock Control

w Pre-Production, Rev 3.0, February 2007 AUDIO SAMPLE RATES The WM8940 sample rates for the ADC and the DAC are set using the SR register bits. The cutoffs for the digital filters and the ALC attack/decay times stated are determined using these values and assume a 256fs master clock rate. If a sample rate that is not explicitly supported by the SR register settings is required then the closest SR value to that sample rate should be chosen, the filter characteristics and the ALC attack, decay and hold times will scale appropriately. REGISTER ADDRESS BIT LABEL DEFAULT 3:1 SR 000 Approximate sample rate (configures the coefficients for the internal digital filters): 000=48kHz 001=32kHz 010=24kHz 011=16kHz 100=12kHz 101=8kHz 110-111=reserved Table 45 Sample Rate Control MASTER CLOCK AND PHASE LOCKED LOOP (PLL) The WM8940 has an on-chip phase-locked loop (PLL) circuit that can be used to: Generate master clocks for the WM8940 audio functions from another external clock, e.g. in telecoms applications. Generate an output clock, on pin CSB/GPIO, for another part of the system (derived from an existing audio master clock). Figure 30 shows the PLL and internal clocking arrangement on the WM8940. The PLL is enabled or disabled by the PLLEN register bit. Note: In order to minimise current consumption, the PLL is disabled when the VMIDSEL[1:0] bits are set to 00b. VMIDSEL[1:0] must be set to a value other than 00b to enable the PLL. REGISTER ADDRESS BIT LABEL DEFAULT 0=PLL off 1=PLL on Table 46 PLLEN Control Bit

w Pre-Production, Rev 3.0, February 2007 Figure 30 PLL and Clock Select Circuit The PLL frequency ratio R = f2/f1 (see Figure 30) can be set using the register bits PLLK and PLLN. N controls the ratio of the division, and K the fractional part. The nominal output frequency of the PLL (PLL_OUT) is 98.304MHz. The PLL output then passes through a fixed divide by 4, and can also be further divided by MCLKDIV[3:0] (see figure 34). The divided clock (SYSCLK) can be used to clock the WM8940 DSP. REGISTER ADDRESS BIT LABEL DEFAULT PLL_POWERDOWN PLL POWER 0=ON 1=OFF FRACEN Fractional Divide within the PLL 0=Disabled (Lower Power) 1=Enabled 5:4 PLLPRESCALE 00 = MCLK input multiplied by 2 (default) 01 = MCLK input not divided (default) 10 = Divide MCLK by 2 before input to PLL 11 = Divide MCLK by 4 before input to PLL R36 PLL N value 3:0 PLLN 1100 Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. R37 PLL K value 1 5:0 PLLK [23:18] 0Ch R38 PLL K Value 2 8:0 PLLK [17:9] 093h R39 PLL K Value 3 8:0 PLLK [8:0] 0E9h Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Table 47 PLL Frequency Ratio Control

w Pre-Production, Rev 3.0, February 2007 INTEGER N DIVISION The integer division ratio (N) is determined by N[3:0] and must be in the range 5 to 12. If the PLL frequency is an exact integer (5,6,7,8,9,10,11,12) then FRAC_EN can be set to 0 for low power operation. INPUT CLOCK (PLL_IN) DESIRED PLL OUTPUT (PLL_OUT) DIVISION REQUIRED (X) FRACTIONAL DIVISION (K) INTEGER DIVISION (N) SDM 11.2896MHz 90.3168MHz 12.288MHz 98.304MHz Table 48 PLL Modes of Operation (Integer N mode) FRACTIONAL K MODE The Fractional K bits provides K[23:0] provide finer divide resolution for the PLL frequency ratio (up to 1/224). If these are used then FRAC_EN must be set. The relationship between the required division X, the fractional division K[23:0] and the integer division N[3:0] is: K = 223 ( X – N) where 0 < (X – N) < 1 and K is rounded to the nearest whole number. For example, if the PLL input clock (PLL_IN) is 13MHz and the desired PLL output clock (PLLCLK) is 98.304MHz then the desired division, X, is 7.561800. So N[3:0] will be 7h and K[23:0] will be 23F400h to produce the desired 98.304MHz clock. The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings are shown in Table 49. MCLK (MHz) (F1) DESIRED OUTPUT (MHz) (MHz) PRESCALE DIVIDE POSTSCALE DIVIDE (FIXED) R N (Hex) K (Hex) 11.29 90.3168 MCLK/2 7.5264 86C220 12.288 98.304 MCLK/2 8.192 3126E8 11.29 90.3168 MCLK/2 6.947446 F28BD4 12.288 98.304 MCLK/2 7.561846 8FD525 14.4 11.29 90.3168 MCLK/2 6.272 45A1CA 14.4 12.288 98.304 MCLK/2 6.826667 D3A06E 19.2 11.29 90.3168 MCLK/4 9.408 6872AF 19.2 12.288 98.304 MCLK/4 10.24 A 3D70A3 19.68 11.29 90.3168 MCLK/4 9.178537 2DB492 19.68 12.288 98.304 MCLK/4 9.990243 FD809F 19.8 11.29 90.3168 MCLK/4 9.122909 1F76F7 19.8 12.288 98.304 MCLK/4 9.929697 EE009E 11.29 90.3168 MCLK/4 7.5264 86C226 12.288 98.304 MCLK/4 8.192 3126E8 11.29 90.3168 MCLK/4 6.947446 F28BD4 12.288 98.304 MCLK/4 7.561846 8FD525 11.29 90.3168 MCLK/4 6.690133 BOAC93 12.288 98.304 MCLK/4 7.281778 482296 Table 49 PLL Frequency Examples

w Pre-Production, Rev 3.0, February 2007 LOOPBACK Setting the ADC_LOOPBACK or DAC_LOOPBACK register bit enables digital loopback. When the ADC_LOOPBACK bit is set the output data from the ADC audio interface is fed directly into the DAC data input. When the DAC_LOOPBACK bit is set the output data from the DAC audio interface is fed directly to the input of the ADC audio interface. COMPANDING The WM8940 supports A-law and µ-law companding on both transmit (ADC) and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively. If packed mode companding is desired the WL8 register bit is available. It will override the normal audio interface WL bits to give an 8-bit word length. Refer to Table 43 Audio Interface Control for setting the output word length. REGISTER ADDRESS BIT LABEL DEFAULT DAC_LOOPBACK Digital loopback function 0=No DAC loopback 1=Loopback enabled, DAC audio interface output is fed directly into ADC audio interface input. 4:3 DAC_COMP DAC decompanding 00=off 01=reserved 10=µ-law 11=A-law 2:1 ADC_COMP ADC companding 00=off 01=reserved 10=µ-law 11=A-law Companding control ADC_LOOPBACK Digital loopback function 0=No ADC loopback 1=Loopback enabled, ADC data output is fed directly into DAC data input. Table 50 Companding Control Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: µ-law (where µ=255 for the U.S. and Japan): A-law (where A=87.6 for Europe): F(x) = A|x| / ( 1 + lnA) } for x ≤ 1/A F(x) = ( 1 + lnA|x|) / (1 + lnA) } for 1/A ≤ x ≤ 1 The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted for µ-law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSB’s of data. Companding converts 13 bits (µ-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The input data range is separated into 8 levels, allowing low amplitude signals better precision than that of high amplitude signals. This is to exploit the operation of the human auditory system, where louder sounds do not require as much resolution as quieter sounds. The companded signal is an 8- bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits).

w Pre-Production, Rev 3.0, February 2007 GENERAL PURPOSE INPUT/OUTPUT In 2-wire mode, the CSB pin is not required and it can be used as a GPIO pin. In 3 wire mode, the MODE / GPIO can be configured as a GPIO by setting the MODE_GPIO register bit Whichever pin is used for GPIO, it is controlled from the GPIO control register R8. The GPIOSEL bits allow the chosen pin to be configured to perform a variety of useful tasks as shown in Table 57. Note that SLOWCLKEN must be enabled when using the jack detect function. REGISTER ADDRESS BIT LABEL DEFAULT 5:4 OPCLKDIV PLL Output clock division ratio 00=divide by 1 01=divide by 2 10=divide by 3 11=divide by 4 GPIOPOL GPIO Polarity invert 0=Non inverted 1=Inverted GPIO control 2:0 GPIOSEL 000 CSB/GPIO pin function select: 000=CSB input 001= Jack insert detect 010=Temp ok 011=Amute active 100=SYSCLK clock o/p 101=PLL lock 110=Reserved 111=Reserved Table 52 CSB/GPIO Control CONTROL INTERFACE SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS The control interface can operate as either a 3-wire or 2-wire interface. The MODE pin determines the 2 or 3 wire mode as shown in Table 57. The WM8940 is controlled by writing to registers through a serial control interface. A control word consists of 24 bits. The first 7 bits (B23 to B16) are address bits that select which control register is accessed. The remaining 16 bits (B15 to B0) are register bits, corresponding to the 16 bits in each control register. MODE INTERFACE FORMAT Low 2 wire Hi-Z 3 wire High 3 wire Table 53 Control Interface Mode Selection USE OF MODE AS A GPIO PIN IN 3-WIRE MODE In 3-wire mode, MODE can be used as a GPIO pin. If MODE is being used as a GPIO output, the partner device doesn’t have to drive MDE - the pin will be pulled-up internally causing 3-wire mode will be selected. The GPIO function is enabled by setting the MODE_GPIO register bit. The MODE pin can then be controlled using the GPIO register bits as described in <Table 39> [add as x- reference]. To use MODE as a GPIO input, MODE must be undriven or driven high at start-up. Specifically MODE must be high or hi-Z during an initial write to the control interface which sets the MODE_GPIO register bit. After MODE_GPIO has been set, 3-wire mode selection is overridden internally and the MODE pin can be used freely as a GPIO input or output.

w Pre-Production, Rev 3.0, February 2007 Figure 33 Example Usage of MODE Pin to Generate a Clock out in 3-wire Mode This example shows how the MODE_GPIO register bit interfaces to the MODE pad in the case there MODE is used as a GPIO output. When MODE_GPIO is set, the internal version of MODE is overridden to high and the MODE pin output driver is enabled. The pull up, which is used to default 3-wire mode at start-up, is disabled as a power saving measure. MODE_GPIO cannot be set in 2-wire m–de - this would prevent correct operation of the control interface. Internal timing is arranged to ensure that the override is in place before the pull-up is disabled. REGISTER ADDRESS BIT LABEL DEFAULT MODE_GPIO Selects MODE as a GPIO pin 0 = MODE is an input. MODE selects 2- wire mode when low and 3-wire mode when high. 1 = MODE can be an input or output under the control of the GPIO control register. Interface operates in 3-wire mode regardless of what happens on the MODE pin. Table 54 Mode is GPIO Control Auto-incremental writes are supported in 2 wire and 3 wire modes. This is enabled by default. REGISTER ADDRESS BIT LABEL DEFAULT Auto-Incremental write enable 0=Auto-Incremental writes disabled 1=Auto-Incremental writes enabled Table 55 Control Interface

w Pre-Production, Rev 3.0, February 2007 2-WIRE SERIAL CONTROL MODE The WM8940 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit address of each register in the WM8940). The WM8940 operates as a slave device only. The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8940, then the WM8940 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is ‘1’ when operating in write only mode, the WM8940 returns to the idle condition and wait for a new start condition and valid address. During a write, once the WM8940 has acknowledged a correct address, the controller sends the first byte of control data (B23 to B16, i.e. the WM8940 8 bit register address). The WM8940 then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then sends the second byte of control data (B15 to B8, i.e. the most significant 8 bits of register data), and the WM8940 acknowledges again by pulling SDIN low for one clock pulse. The controller then sends the third byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8940 acknowledges again by pulling SDIN low for one clock pulse. Transfers are complete when there is a low to high transition on SDIN while SCLK is high. After a complete sequence the WM8940 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition. Figure 37 2-Wire Serial Control Interface In 2-wire mode the WM8940 has a fixed device address, 0011010. RESETTING THE CHIP The WM8940 can be reset by performing a write of any value to the software reset register (address 0 hex). This will cause all register values to be reset to their default values. In addition to this there is a Power-On Reset (POR) circuit which ensures that the registers are set to default when the device is powered up. POWER SUPPLIES The WM8940 requires four separate power supplies: AVDD and AGND: Analogue supply, powers all analogue functions except the speaker output and mono output drivers. AVDD can range from 2.5V to 3.6V and has the most significant impact on overall power consumption (except for power consumed in the headphone). A larger AVDD slightly improves audio quality. SPKVDD and SPKGND: Headphone and Speaker supplies, power the speaker and mono output drivers. SPKVDD can range from 2.5V to 3.6V. SPKVDD can be tied to AVDD, but it requires separate layout and decoupling capacitors to curb harmonic distortion. With a larger SPKVDD, louder headphone and speaker outputs can be achieved with lower distortion. If SPKVDD is lower than AVDD, the output signal may be clipped. DCVDD: Digital core supply, powers all digital functions except the audio and control interfaces. DCVDD can range from 1.71V to 3.6V, and has no effect on audio quality. The return path for DCVDD is DGND, which is shared with DBVDD. DBVDD can range from 1.71V to 3.6V. DBVDD return path is through DGND.

w Pre-Production, Rev 3.0, February 2007 It is possible to use the same supply voltage for all four supplies. However, digital and analogue supplies should be routed and decoupled separately on the PCB to keep digital switching noise out of the analogue signal paths. RECOMMENDED POWER UP/DOWN SEQUENCE In order to minimise output pop and click noise, it is recommended that the WM8940/WM8941 device is powered up and down using one of the following sequences: Power Up: Turn on external power supplies. Wait for supply voltages to settle. Reset internal registers to default state (software reset). Enable non-VMID derived bias generator (VMID_OP_EN = 1) and level shifters (LVLSHIFT_EN = 1). Enable DAC soft mute (DACMU = 1). Select Clock source to MCLK (CLKSEL = 0) and audio mode (Master or Slave). Enable Power on Bias Control (POB_CTRL = 1) and VMID soft start (SOFT_START = 1). Enable speaker outputs (SPKPEN = 1, SPKNEN = 1) and wait for outputs to settle. Set VMIDSEL[1:0] bits for 75kΩ reference string impedance. Wait for the VMID supply to settle. *Note 2. 10. Enable analogue amplifier bias control (BIASEN = 1) and VMID buffer (BUFIOEN = 1). *Notes 1 and 2. 11. Disable Power on Bias Control (POB_CTRL = 0) and VMID soft start (SOFT_START = 0). 12. Enable DAC (DACEN =1) and Speaker Mixer (SPKMIXEN = 1). 13. Enable output of DAC to speaker mixer (DAC2SPK = 1). 14. Disable speaker mute (SPKMUTE = 0) and set SPKVOL = -57dB. 15. Ramp up the SPKVOL using the following values: 16. -27 dB, -21 dB, -15 dB, -13 dB, -11 dB, -9 dB, -8 dB, -7 dB, -6 dB, -5 dB, -4 dB, -3 dB, -2 dB, -1 dB, 0 dB. 17. Disable DAC soft mute (DACMU = 0). Power Down: Enable DAC soft mute (DACMU = 1). Enable non-VMID derived bias generator (VMID_OP_EN = 1). Enable on Bias Control (POB_CTRL = 1). Disable analogue amplifier bias control (BIASEN = 0) and VMID (VMIDSEL[1:0] bits set to OFF). Enable Fast VMID Discharge (TOGGLE = 1) to discharge VMID capacitor. Wait for VMID capacitor to fully discharge. Enable speaker output mute (SPKMUTE = 1).

w Pre-Production, Rev 3.0, February 2007 Disable DAC (DACEN = 0), speaker mixer (SPKMIX = 0), and speaker outputs (SPKPEN = 0 and SPKNEN = 0). Reset all registers to their default state (software reset). 10. Turn off external power supply voltages. Notes: This step enables the internal device bias buffer and the VMID buffer for unassigned inputs/outputs. This will provide a startup reference for all inputs and outputs. This will cause the inputs and outputs to ramp towards VMID in a way that is controlled and predictable. Choose the value of VMIDSEL bits based on the startup time (VMIDSEL = 10 for the slowest startup, VMIDSEL = 11 for the fastest startup). Startup time is defined by the value of the VMIDSEL bits (the reference impedance) and the external decoupling capacitor on VMID. In addition to the power on sequence, it is recommended that the zero cross functions are used when changing the volume in the PGAs to avoid any audible pops and clicks. POWER MANAGEMENT VMID The analogue circuitry will not work when VMID is disabled (VMIDSEL[1:0] = 00b). The impedance of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the start-up time of the VMID circuit. REGISTER ADDRESS BIT LABEL DEFAULT 1:0 VMIDSEL Reference string impedance to VMID pin (determines startup time): 00=off (open circuit) 01=75kΩ 10=300kΩ 11=2.5kΩ (for fastest startup) Table 57 VMID Impedance Control BIASEN REGISTER ADDRESS BIT LABEL DEFAULT Analogue amplifier bias control 0=Disabled 1=Enabled Table 58 BIASEN Control ESTIMATED SUPPLY CURRENTS When either the DAC or ADC are enabled it is estimated that approximately 4mA will be drawn from DCVDD when fs=48kHz (This will be lower at lower sample rates). When the PLL is enabled an additional 700 microamps will be drawn from DCVDD.

w Pre-Production, Rev 3.0, February 2007 Table 59 shows the estimated 3.3V AVDD current drawn by various circuits, by register bit. REGISTER BIT AVDD CURRENT (MILLIAMPS) MONOEN 0.2mA PLLEN 1.4mA (with clocks applied) MICBEN 0.5mA BIASEN 0.3mA BUFIOEN 0.1mA VMIDSEL 10K=>0.3mA, less than 0.1mA for 100k/500k BOOSTEN 0.2mA INPPGAEN 0.2mA ADCEN 2.6mA MONOEN 0.2mA SPKPEN 1mA from SPKVDD SPKNEN 1mA from SPKVDD MONOMIXEN 0.2mA SPKMIXEN 0.2mA DACEN 1.8mA Table 59 AVDD Supply Current POP MINIMISATION Power-On-Bias Control (POB_CTRL) selects the bias current source for the output stages of the WM8940. 0 selects the VMID derived bias source (normal operation), 1 selects a non-VMID derived source which allows the output amplifiers to be enabled before VMID at start-up. This feature can be used to minimise pops. Once VMID is enabled and has stabilised, POBCTRL should be set to 0. Register SOFT_START is the enable bit for the VMID soft-start function. Setting the bit to 1 causes charging of the VMID decoupling cap to follow a soft-start profile which minimises pops. This soft- start profile has minimal impact on VMID charge time. Fast VMID discharge is enabled using TOGGLE. Setting to 1 opens a low impedance discharge path from VMID to GND. This function can be used during power down to reduce the discharge time of the VMID decoupling cap. Must be set to 0 for normal operation. REGISTER ADDRESS BIT LABEL DEFAULT POB_CTRL Power on Bias Control 0=normal (current bias based on VMID) 1=Startup (current bias not based on VMID) SOFT_START VMID Soft Start 0=disabled 1=enabled Additional Control TOGGLE Fast VMID Discharge 0=normal 1=enable (used during power-down) Table 60 POP Minimisation Control

w Pre-Production, Rev 3.0, February 2007 REGISTER MAP Dec Hex Software Reset 1000_1001_0100_0000 BUFIOEN 0000_0000_0000_0000 Power management 2 BOOSTEN INPPGAEN ADCEN 0000_0000_0000_0000 Power management 3 MONOEN SPKNEN SPKPEN VBUFEN MONOMIXEN SPKMIXEN DACEN 0000_0000_0000_0000 Audio Interface LOUTR BCP FRAMEP DLRSWAP ALRSWAP 0000_0000_0101_0000 Companding control DAC_LOOPBACK WL8 ADC_LOOPBACK 0000_0000_0000_0000 Clock Gen control CLKSEL MS 0000_0001_0100_0000 Additional control POB_CTRL SOFT_START TOGGLE SLOWCLKEN 0000_0000_0000_0000 GPIO Stuff MODE_GPIO GPIOPOL 0000_0000_0000_0000 Control Interface AUTOINC 0000_0000_0000_0010 DAC Control SOFTMUTE AMUTE DACPOL 0000_0000_0000_0000 DAC digital Vol 0000_0000_1111_1111 Reserved Reserved ADC Control HPFEN HPFAPP ADCPOL 0000_0001_0000_0000 ADC Digital Vol 0000_0000_1111_1111 Notch Filter 1 NF0_UP NF0_EN 0000_0000_0000_0000 Notch Filter 2 NF0_UP 0000_0000_0000_0000 Notch Filter 3 NF1_UP NF1_EN 0000_0000_0000_0000 Notch Filter 4 NF1_UP 0000_0000_0000_0000 Notch Filter 5 NF2_UP NF2_EN 0000_0000_0000_0000 Notch Filter 6 NF2_UP 0000_0000_0000_0000 Notch Filter 7 NF3_UP NF3_EN 0000_0000_0000_0000 Notch Filter 8 NF3_UP NF3_LP 0000_0000_0000_0000 DAC Limiter 1 LIMEN 0000_0000_0011_0010 DAC Limiter 2 0000_0000_0000_0000 Reserved Reserved Reserved Reserved Reserved Reserved ALC control 1 ALCSEL 0000_0000_0011_1000 ALC control 2 0000_0000_0000_1011 ALC control 3 ALCMODE 0000_0000_0011_0010 Noise Gate NGEN 0000_0000_0000_0000 PLL N PLL_POWERDO WN FRACEN 0000_0000_0100_1000 PLL K 1 0000_0000_0000_1100 PLL K 2 0000_0000_1001_0011 PLL K 3 0000_0000_1110_1001 Reserved 0000_0000_0000_0000 Reserved ALC control 4 ALCZC 0000_0000_0011_0000 Reserved Input ctrl MICBVSEL AUXMODE AUX2INPPGA MICN2INPPGA MICP2INPPGA 0000_0000_0000_0010 INP PGA gain ctrl INPPGAZC INPPGAMUTE 0000_0000_0101_0000 Reserved ADC BOOST ctrl PGABOOST 0000_0000_0000_0000 Reserved Output ctrl TSDEN VROI 0000_0000_0000_0010 SPK mixer control AUX2SPK BYP2SPK DAC2SPK 0000_0000_0000_0000 Reserved Reserved Reserved SPK volume ctrl SPKATTN SPKZC SPKMUTE 0000_0000_0111_1001 Reserved MONO mixer control MONOATTN MONOMUTE AUX2MONO BYP2MONO DAC2MONO 0000_0000_0000_0000 SOTWARE RESET ON WRITE / CHIP ID ON READ Power management 1 VMID_OP_EN LVLSHIFT_EN AUXEN PLLEN MICBEN BIASEN VMIDSEL[1:0] DEVICE_REVISION[2:0] WL[1:0] FMT[1:0] DAC_COMP[1:0] ADC_COMP[1:0] MCLKDIV[2:0] BCLKDIV[2:0] SR[2:0] OPCLKDIV[1:0] GPIOSEL[2:0] DACVOL[7:0] HPFCUT[2:0] ADCVOL[7:0] NF0_A0[13:0] NF0_A1[13:0] NF1_A0[13:0] NF1_A1[13:0] NF2_A0[13:0] NF2_A1[13:0] NF3_A0[13:0] NF3_A1[13:0] LIMDCY[3:0] LIMATK[3:0] LIMLVL[2:0] LIMBOOST[3:0] ALCGAIN[5:0] ALCMAX[2:0] ALCMIN[2:0] ALCHLD[3:0] ALCLVL[3:0] PLLK[23:18] PLLK[17:9] PLLK[8:0] ALCDCY[3:0] ALCATK[3:0] NGTH[2:0] PLL_PRESCALE[1:0] PLLN[3:0] INPPGAVOL[5:0] MICP2BOOSTVOL[2:0] AUX2BOOSTVOL[2:0] SPKVOL[5:0] ADDR Register Name B15 B14 B13 B12 B11 B10 Default Value (Bin)

w Pre-Production, Rev 3.0, February 2007 REGISTER BITS BY ADDRESS Notes: 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as "Reserved" should not be changed from the default. REGISTER ADDRESS BIT LABEL DEFAULT 0 (00h) [15:0] RESET / CHIP_ID N/A Writing to this register will apply a software reset. Reading from this register will return the device id Resetting the Chip / Control Interface 15:9 Reserved VMID_OP_EN Enables the non-VMID derived bias current generator without enabling the VMID buffer. This bit must be set to 1 if output amplifiers are to be enabled before VMID is active. Once VMID and VMID buffer are enabled this bit can be left set to 0 or left set to 1. Power Management LVLSHIFT_EN Enable bit for the level shifters. 1 for normal operation, 0 for standby. Power Management AUXEN Auxiliary input buffer enable 0 = OFF 1 = ON Auxiliary Inputs PLLEN PLL enable 0=PLL off 1=PLL on Master Clock and Phase Locked Loop (PLL) MICBEN Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON Microphone Biasing Circuit BIASEN Analogue amplifier bias control 0=Disabled 1=Enabled Power Management 2:0 DEVICE_REVI SION 000 Readback from this register will return the device revision in this position Control Interface BUFIOEN Enable bit for the VMID buffer. The VMID buffer is used to maintain a buffered VMID voltage on all analogue input and output pins. 1. for normal operation 0. for standby (where inputs and outputs settle to GND). Enabling the Outputs 1 (01h) 1:0 VMIDSEL Reference string impedance to VMID pin: 00=off (open circuit) 01=75kΩ 10=300kΩ 11=2.5kΩ Power Management 15:5 000h Reserved BOOSTEN Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON Input Boost Reserved INPPGAEN Input microphone PGA enable 0 = disabled 1 = enabled Input Signal Path Reserved 2 (02h) ADCEN ADC Enable Control 0 = ADC disabled 1 = ADC enabled Analogue to Digital Converter (ADC) 3 (03h) 15:8 00h Reserved

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT 0 = disabled 1 = enabled Analogue Outputs SPKNEN SPKOUTN enable 0 = disabled 1 = enabled Analogue Outputs SPKPEN SPKOUTP enable 0 = disabled 1 = enabled Analogue Outputs Reserved MONOMIXEN Mono Mixer Enable 0 = disabled 1 = enabled Analogue Outputs SPKMIXEN Speaker Mixer Enable 0 = disabled 1 = enabled Analogue Outputs Reserved DACEN DAC enable 0 = DAC disabled 1 = DAC enabled Analogue Outputs 15:10 00h Reserved LOUTR LOUTR control 0=normal 1=Input mono channel data output on left and right channels Digital Audio Interfaces BCP BCLK polarity 0=normal 1=inverted Digital Audio Interfaces Frame clock polarity 0=normal 1=inverted FRAMEP DSP Mode control 1 = Configures the interface so that MSB is available on 1st BCLK rising edge after FRAME rising edge 0 = Configures the interface so that MSB is available on 2nd BCLK rising edge after FRAME rising edge Digital Audio Interfaces 6:5 WL Word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits Digital Audio Interfaces 4:3 FMT Audio interface Data Format Select: 00=Right Justified 01=Left Justified 10=I2S format 11= DSP/PCM mode Digital Audio Interfaces DLRSWAP Controls whether DAC data appears in ‘right’ or ‘left’ phases of FRAME clock: 0=DAC data appear in ‘left’ phase of FRAME 1=DAC data appears in ‘right’ phase of FRAME Digital Audio Interfaces 4 (04h) ALRSWAP Controls whether ADC data appears in ‘right’ or ‘left’ phases of FRAME clock: 0=ADC data appear in ‘left’ phase of FRAME 1=ADC data appears in ‘right’ phase of FRAME Digital Audio Interfaces

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT 15:7 0000 Reserved DAC_LOOPBA CK Digital loopback function 0=No DAC loopback 1=Loopback enabled, DAC data input is fed directly into ADC data output. Digital Audio Interfaces WL8

8 Bit Word Length for companding

0=Word Length controlled by WL 1=8 bits Digital Audio Interfaces 4:3 DAC_COMP DAC companding 00=off 01=reserved 10=µ-law 11=A-law Digital Audio Interfaces 2:1 ADC_COMP ADC companding 00=off 01=reserved 10=µ-law 11=A-law Digital Audio Interfaces 5 (05h) ADC_LOOPBA CK Digital loopback function 0=No ADC loopback 1=Loopback enabled, ADC data output is fed directly into DAC data input. Digital Audio Interfaces 15:9 00h Reserved CLKSEL Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output Digital Audio Interfaces 7:5 MCLKDIV 010 Sets the scaling for either the MCLK or PLL clock output (under control of CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 Digital Audio Interfaces 4:2 BCLKDIV 000 Configures the BCLK and FRAME output frequency, for use when the chip is master over BCLK. 000=divide by 1 (BCLK=MCLK) 001=divide by 2 (BCLK=MCLK/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved Digital Audio Interfaces Reserved 6 (06h) MS Sets the chip to be master over FRAME and BCLK 0=BCLK and FRAME clock are inputs 1=BCLK and FRAME clock are outputs generated by the WM8940 (MASTER) Digital Audio Interfaces 7 (07h) 15:7 00000 Reserved

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT POB_CTRL Power on Bias Control 0=normal (current bias based on VMID) 1=Startup (current bias not based on VMID) POP Minimisation SOFT_START VMID Soft Start 0=disabled 1=enabled POP Minimisation TOGGLE Fast VMID Discharge 0=normal 1=enable (used during powerdown) POP Minimisation 3:1 SR 000 Approximate sample rate (configures the coefficients for the internal digital filters): 000=48kHz 001=32kHz 010=24kHz 011=16kHz 100=12kHz 101=8kHz 110-111=reserved Audio Sample Rates SLOWCLKEN Enables the Timeout Clock for zero cross detection. Zero Cross Timeout 15:8 00h Reserved MODE_GPIO Selects MODE as a GPIO pin 0 = MODE is an input. MODE selects 2-wire mode when low and 3-wire mode when high. 1 = MODE can be an input or output under the control of the GPIO control register. Interface operates in 3- wire mode regardless of what happens on the MODE pin. Control Interface Reserved 5:4 OPCLKDIV PLL Output clock division ratio 00=divide by 1 01=divide by 2 10=divide by 3 11=divide by 4 General Purpose Input Output GPIOPOL GPIO Polarity invert 0=Non inverted 1=Inverted General Purpose Input Output 8 (08h) 2:0 GPIOSEL 000 CSB/GPIO pin function select: 000=CSB input 001= Jack insert detect 010=Temp ok 011=Amute active 100=PLL clk o/p 101=PLL lock 110=Reserved 111=Reserved General Purpose Input Output 15:2 Reserved AUTOINC Auto-Incremental write enable 0=Auto-Incremental writes disabled 1=Auto-Incremental writes enabled Control Interface 9 (09h) Reserved 10 (0Ah) 15:7 Reserved

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT 0 = DACMU disabled 1 = DACMU enabled Output Signal Path 5:3 Reserved AMUTE DAC auto mute enable 0 = auto mute disabled 1 = auto mute enabled Output Signal Path Reserved DACPOL DAC Polarity Invert 0 = No inversion 1 = DAC output inverted Output Signal Path 15:8 00h Reserved 11 (0Bh) 7:0 DACVOL 11111111 DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB Output Signal Path 12 (0Ch) 15:0 Reserved 13 (0Dh) 15:0 Reserved 15:9 00h Reserved HPFEN High Pass Filter Enable 0=disabled 1=enabled Analogue to Digital Converter (ADC) HPFAPP Select audio mode or application mode 0=Audio mode (1st order, fc = ~3.7Hz) 1=Application mode (2nd order, fc = HPFCUT) Analogue to Digital Converter (ADC) 6:4 HPFCUT 000 Application mode cut-off frequency See Table 14 for details. Analogue to Digital Converter (ADC) 3:1 Reserved 14 (0Eh) ADCPOL ADC Polarity 0=normal 1=inverted Analogue to Digital Converter (ADC) 15:8 00h Reserved 15 (0Fh) 7:0 ADCVOL 11111111 ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB Analogue to Digital Converter (ADC) NF0_UP Notch filter 0 update. The notch filter 0 values used internally only update when one of the NF0_UP bits is set high. Analogue to Digital Converter (ADC) NF0_EN Notch filter 0 enable: 0=Disabled 1=Enabled Analogue to Digital Converter (ADC) 16 (10h) 13:0 NF0_A0 0000h Notch Filter 0 a0 coefficient Analogue to Digital Converter (ADC) NF0_UP Notch filter 0 update. The notch filter 0 values used internally only update when one of the NF0_UP bits is set high. Analogue to Digital Converter (ADC) 17 (11h) Reserved

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT 13:0 NF0_A1 0000h Notch Filter 0 a1 coefficient Analogue to Digital Converter (ADC) NF1_UP Notch filter 1 update. The notch filter 1 values used internally only update when one of the NFU bits is set high. Analogue to Digital Converter (ADC) NF1_EN Notch Filter 1 enable. 0=Disabled 1=Enabled Analogue to Digital Converter (ADC) 18 (12h) 13:0 NF1_A0 0000h Notch Filter 1 a0 coefficient Analogue to Digital Converter (ADC) NF1_UP Notch filter 1 update. The notch filter 1 values used internally only update when one of the NFU bits is set high. Analogue to Digital Converter (ADC) Reserved 19 (13h) 13:0 NF1_A1 0000h Notch Filter 1 a1 coefficient Analogue to Digital Converter (ADC) NF2_UP Notch filter 2 update. The notch filter 2 values used internally only update when one of the NFU bits is set high. Analogue to Digital Converter (ADC) NF2_EN Notch Filter 2 enable. 0=Disabled 1=Enabled Analogue to Digital Converter (ADC) 20 (14h) 13:0 NF2_A0 0000h Notch Filter 2 a0 coefficient Analogue to Digital Converter (ADC) NF2_UP Notch filter 2 update. The notch filter 2 values used internally only update when one of the NFU bits is set high. Analogue to Digital Converter (ADC) Reserved 21 (15h) 13:0 NF2_A1 0000h Notch Filter 2 a1 coefficient Analogue to Digital Converter (ADC) NF3_UP Notch filter 3 update. The notch filter 3 values used internally only update when one of the NFU bits is set high. Analogue to Digital Converter (ADC) NF3_EN Notch Filter 3 enable. 0=Disabled 1=Enabled Analogue to Digital Converter (ADC) 22 (16h) 13:0 NF3_A0 0000h Notch Filter 3 a0 coefficient Analogue to Digital Converter (ADC) NF3_UP Notch filter 3 update. The notch filter 3 values used internally only update when one of the NFU bits is set high. Analogue to Digital Converter (ADC) NF3_LP Notch Filter 3 mode select 0 = Notch Filter mode 1 = Low Pass Filter mode Analogue to Digital Converter (ADC) 23 (17h) 13:0 NF3_A1 0000h Notch Filter 3 a1 coefficient Analogue to Digital Converter (ADC) 24 (18h) 15:9 00h Reserved

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT Enable the DAC digital limiter: 0=disabled 1=enabled Output Signal Path 7:4 LIMDCY 0011 DAC Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate: 0000=750us 0001=1.5ms 0010=3ms 0011=6ms 0100=12ms 0101=24ms 0110=48ms 0111=96ms 1000=192ms 1001=384ms 1010=768ms 1011 to 1111=1.536s Output Signal Path 24 (18h) 3:0 LIMATK 0010 DAC Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate. 0000=94us 0001=188s 0010=375us 0011=750us 0100=1.5ms 0101=3ms 0110=6ms 0111=12ms 1000=24ms 1001=48ms 1010=96ms 1011 to 1111=192ms Output Signal Path 15:7 000h Reserved 6:4 LIMLVL 000 DAC Limiter Programmable signal threshold level (determines level at which the limiter starts to operate) 000=-1dB 001=-2dB 010=-3dB 011=-4dB 100=-5dB 101 to 111=-6dB Output Signal Path 25 (19h) 3:0 LIMBOOST 0000 DAC Limiter volume boost (can be used as a stand alone volume boost when LIMEN=0): 0000=0dB 0001=+1dB 0010=+2dB … (1dB steps) 1011=+11dB 1100=+12dB 1101 to 1111=reserved Output Signal Path 26 (1Ah) 15:0 0000h Reserved 27 (1Bh) 15:0 0000h Reserved

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT 28 (1Ch) 15:0 0000h Reserved 29 (1Dh) 15:0 0000h Reserved 30 (1Eh) 15:0 0000h Reserved 31(1Fh) 15:0 0000h Reserved 15:10 ALCGAIN [5:0] 000000 Readback from this register will return the ALC gain in this position Input Limiter / Automatic Level Control (ALC) Reserved ALCSEL ALC function select 0=ALC disabled 1=ALC enabled Input Limiter / Automatic Level Control (ALC) 7:6 Reserved 5:3 ALCMAX 111 Set Maximum Gain of PGA Input Limiter / Automatic Level Control (ALC) 32 (20h) 2:0 ALCMIN 000 Set minimum gain of PGA Input Limiter / Automatic Level Control (ALC) 15:8 000h Reserved 7:4 ALCHLD 000 ALC hold time before gain is increased. Input Limiter / Automatic Level Control (ALC) 33 (21h) 3:0 ALCLVL 1011 ALC threshold level. Sets the desired signal level. Input Limiter / Automatic Level Control (ALC) 15:9 00h Reserved ALCMODE Determines the ALC mode of operation: 0=Normal mode 1=Limiter mode. Input Limiter / Automatic Level Control (ALC) 7:4 ALCDCY 0011 Decay (gain ramp-up) time Input Limiter / Automatic Level Control (ALC) 34 (22h) 3:0 ALCATK 0010 ALC attack (gain ramp-down) time Input Limiter / Automatic Level Control (ALC) 15:4 000h Reserved NGEN Noise gate function enable 1 = enable 0 = disable Input Limiter / Automatic Level Control (ALC) 35 (23h) 2:0 NGTH 000 Noise gate threshold Input Limiter / Automatic Level Control (ALC) 15:8 00h Reserved PLL_POWERD OWN PLL POWER 0=On 1=Off Master Clock and Phase Locked Loop (PLL) FRACEN Fractional Divide within the PLL 0=Disabled (Lower Power) 1=Enabled Master Clock and Phase Locked Loop (PLL) 36 (24h) 5:4 PLLPRESCALE 00 00 = MCLK input multiplied by 2 (default) 01 = MCLK input not divided (default) 10 = Divide MCLK by 2 before input to PLL 11 = Divide MCLK by 4 before input to PLL Master Clock and Phase Locked Loop (PLL)

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT 3:0 PLLN[3:0] 1100 Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. Master Clock and Phase Locked Loop (PLL) 15:6 000h Reserved 37 (25h) 5:0 PLLK[23:18] 001100 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Master Clock and Phase Locked Loop (PLL) 15:9 00h Reserved 38 (26h) 8:0 PLLK[17:9] 010010011 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Master Clock and Phase Locked Loop (PLL) 15:9 00h Reserved 39 (27h) 8:0 PLLK[8:0] 011101001 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Master Clock and Phase Locked Loop (PLL) 40 (28h) 15:0 0000h Reserved 41 (29h) 15:0 0000h Reserved 15:2 Reserved ALCZC 0 (zero cross off) ALC uses zero cross detection circuit. 0 = Disabled (recommended) 1 = Enabled ALC Control 4 42 (2Ah) Reserved 43 (2Bh) 15:0 0000h Reserved 15:9 00h Reserved MBVSEL Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.75 * AVDD Input Signal Path 7:4 Reserved AUXMODE Auxiliary Input Mode 0 = inverting buffer 1 = mixer (on-chip input resistor bypassed) Input Signal Path AUX2INPPGA Select AUX amplifier output as input PGA signal source. 0=AUX not connected to input PGA 1=AUX connected to input PGA amplifier negative terminal. Input Signal Path MICN2INPPGA 1 Connect MICN to input PGA negative terminal. 0=MICN not connected to input PGA 1=MICN connected to input PGA amplifier negative terminal. Input Signal Path 44 (2Ch) MICP2INPPGA Connect input PGA amplifier positive terminal to MICP or VMID. 0 = input PGA amplifier positive terminal connected to VMID 1 = input PGA amplifier positive terminal connected to MICP through variable resistor string Input Signal Path 15:8 00h Reserved INPPGAZC Input PGA zero cross enable: 0=Update gain when gain register changes 1=Update gain on 1st zero cross after gain register write. Input Signal Path 45 (2Dh) INPPGAMUTE Mute control for input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). Input Signal Path

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT 5:0 INPPGAVOL 010000 Input PGA volume 000000 = -12dB 000001 = -11.25db 010000 = 0dB 111111 = 35.25dB Input Signal Path 46 (2Eh) 15:0 0000h Reserved 15:9 00h Reserved PGABOOST Input Boost 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. Input Signal Path Reserved 6:4 MICP2BOOSTVOL 000 Controls the MICP pin to the input boost stage (NB, when using this path set MICP2INPPGA=0): 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage 111=+6dB gain through boost stage Input Signal Path Reserved 47 (2Fh) 2:0 AUX2BOOSTVOL 000 Controls the auxiliary amplifier to the input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage 111=+6dB gain through boost stage Input Signal Path 48 (30h) 15:0 0000h Reserved 15:2 0000h Reserved TSDEN Thermal Shutdown Enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled Output Switch 49 (31h) VROI VREF (AVDD/2 or 1.5xAVDD/2) to analogue output resistance 0: approx 1kΩ 1: approx 30 kΩuthorize Analogue Outputs 15:6 000h Reserved AUX2SPK Output of auxiliary amplifier to speaker mixer input 0 = not selected 1 = selected Analogue Outputs 4:2 000 Reserved BYP2SPK Bypass path (output of input boost stage) to speaker mixer input 0 = not selected 1 = selected Analogue Outputs 50 (32h) DAC2SPK Output of DAC to speaker mixer input 0 = not selected 1 = selected Analogue Outputs 51 (33h) 15:0 0000h Reserved 52 (34h) 15:0 0000h Reserved 53 (35h) 15:0 0000h Reserved

w Pre-Production, Rev 3.0, February 2007 REGISTER ADDRESS BIT LABEL DEFAULT 15:9 00h Reserved SPKATTN Attenuation control for bypass path (output of input boost stage) to speaker mixer input 0 = 0dB 1 = -10dB Analogue Outputs SPKZC Speaker Volume control zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Analogue Outputs SPKMUTE Speaker output mute enable 0=Speaker output enabled 1=Speaker output muted (VMIDOP) Analogue Outputs 54 (36h) 5:0 SPKVOL 111001 Speaker Volume Adjust 111111 = +6dB 111110 = +5dB … (1.0 dB steps) 111001=0dB 000000=-57dB Analogue Outputs 55 (37h) 15:0 0000h Reserved 15:8 00h Reserved MONOATTN Attenuation control for bypass path (output of input boost stage) to mono mixer input 0 = 0dB 1 = -10dB Analogue Outputs MONOMUTE MONOOUT Mute Control 0=No mute 1=Output muted. During mute the mono output will output VMID which can be used as a DC reference for a headphone out. Analogue Outputs 5:3 Reserved AUX2MONO Output of Auxiliary amplifier to mono mixer input: 0 = not selected 1 = selected Analogue Outputs BYP2MONO Bypass path (output of input boost stage) to mono mixer input 0 = non selected 1 = selected Analogue Outputs 56 (38h) DAC2MONO Output of DAC to mono mixer input 0 = not selected 1 = selected Analogue Outputs

w Pre-Production, Rev 3.0, February 2007 DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC Filter +/- 0.025dB 0.454fs Passband -6dB 0.5fs Passband Ripple +/- 0.025 dB Stopband 0.546fs Stopband Attenuation f > 0.546fs -60 dB Group Delay 21/fs ADC High Pass Filter -3dB 3.7 -0.5dB 10.4 High Pass Filter Corner Frequency -0.1dB 21.6 Hz DAC Filter +/- 0.035dB 0.454fs Passband -6dB 0.5fs Passband Ripple +/-0.035 dB Stopband 0.546fs Stopband Attenuation f > 0.546fs -55 dB Group Delay 29/fs Table 61 Digital Filter Characteristics TERMINOLOGY Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band) Pass-band Ripple – any variation of the frequency response in the pass-band region Note that this delay applies only to the filters and does not include additional delays through other digital circuits. See Table 62 for the total delay. PARAMETER MIN TYP MAX UNIT Total Delay (ADC analogue input to digital audio interface output) 28/fs 30/fs 32/fs fs Total Delay (Audio interface input to DAC analogue output) 33/fs 35/fs 37/fs fs Table 62 Total Group Delay Notes Wind noise filter is disabled.

w Pre-Production, Rev 3.0, February 2007 Figure 48 Cumulative Notch + Low Pass Filters Responses (48kHz); NF0 fc = 1kHz; NF1 fc = 5kHz; NF2 fc = 10kHz; LPF fc = 11kHz; fb = 100Hz, 600Hz, 2kHz NOTCH FILTER WORKED EXAMPLE The following example illustrates how to calculate the a0 and a1 coefficients for a desired centre frequency and -3dB bandwidth. fc = 1000 Hz fb = 100 Hz fs = 48000 Hz s c f w π π x (1000 / 48000) = 0.1308996939 rads s b b f w π = π x (100 / 48000) = 0.01308996939 rads w tan( w tan( a b b 0130899693 tan( 0130899693 tan( = 0.9869949627 w cos( a a 1308996939 cos( 9869949627 ( + = -1.969995945 NFn_A0 = -a0 x 213 = -8085 (rounded to nearest whole number) NFn_A1 = -a1 x 212 = 8069 (rounded to nearest whole number) These values are then converted to a 14-bit sign / magnitude notation: NFn_A0[13] = 1; NFn_A0[12:0] = 13’h1F95; NFn_A0 = 14’h3F95 = 14’b11111110010101 NFn_A1[13] = 0; NFn_A1[12:0] = 13’h1F85; NFn_A1 = 14’h1F85 = 14’b01111110000101 -40 -35 -30 -25 -20 -15 -10 R E S P O N S E (dB) 20k 100 200 500 10k Frequency (Hz) T T T

w Pre-Production, Rev 3.0, February 2007 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 49 Recommended External Components

w Pre-Production, Rev 3.0, February 2007 PACKAGE DIAGRAM DM035.C FL: 24 PIN QFN PLASTIC PACKAGE 4 X 4 X 0.9 mm BODY, 0.50 mm LEAD PITCH INDEX AREA (D/2 X E/2) TOP VIEW D E NOTES: 1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP. 2. FALLS WITHIN JEDEC, MO-220, VARIATION VGGD-2. 3. ALL DIMENSIONS ARE IN MILLIMETRES. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JEDEC 95-1 SPP-002. 5. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 6. REFER TO APPLICATIONS NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING. 7. DEPENDING ON THE METHOD OF LEAD TERMINATION AT THE EDGE OF THE PACKAGE, PULL BACK (L1) MAY BE PRESENT. 8. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. G T H W b Exposed lead Half etch tie bar Dimensions (mm) Symbols MIN NOM MAX NOTE A 0.80 0.90 1.00 0.05 0.02

0.20 REF

b D E e L 0.30 0.18 4.00 2.25 2.15 2.00

0.50 BSC

0.30 0.40 0.50 4.00 2.25 2.15 2.00 0.10 aaa bbb ccc REF: 0.15 0.10 JEDEC, MO-220, VARIATION VGGD-2. Tolerances of Form and Position 0.25 H 0.1 0.213 G T 0.1 W 0.2 DETAIL 1 DETAIL 2 A e b B C bbbM A BOTTOM VIEW C aaa 2 X C aaa 2 X C SEATING PLANE DETAIL 2 C 0.08 C ccc A SIDE VIEW L 0.15 0.03 EXPOSED GROUND PADDLE DETAIL 1 0.32mm degrees EXPOSED GROUND PADDLE e Datum DETAIL 2 Terminal tip e/2 R SEE DETAIL 2

w Pre-Production, Rev 3.0, February 2007 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS Wolfson Microelectronics plc Westfield House

26 Westfield Road

Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com