WM8734

WM8734_06 WOLFSON | Alldatasheet

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w WM8734 Stereo Audio CODEC WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ Production Data, November 2006, Rev 4.1 Copyright 2006 Wolfson Microelectronics plc

DESCRIPTION

The WM8734 is a low power stereo CODEC ideal for MD, CD-RW machines and DAT recording applications. Stereo line inputs are provided, along with a mute function and programmable line level volume control. Stereo 24-bit multi-bit sigma delta ADCs and DACs are used with oversampling digital interpolation and decimation filters. Digital audio input word lengths from 16-32 bits and sampling rates from 8kHz to 96kHz are supported. Stereo audio line level outputs are provided along with anti- thump mute and power up/down circuitry. The device is controlled via a 2 or 3 wire serial interface. The interface provides access to all features including level controls, mutes, de-emphasis and power management facilities. The device is available in 20-lead SSOP or 28- lead, 5x5mm QFN packages.

FEATURES

90dB SNR (‘A’ weighted @ 48kHz) ADC 100dB SNR (‘A’ weighted @ 48kHz) DAC 2.7 – 3.6V Digital Supply Operation 2.7 – 3.6V Analogue Supply Operation ADC and DAC Sampling Frequency: 8kHz – 96kHz Selectable ADC High Pass Filter 2 or 3-Wire MPU Serial Control Interface Programmable Audio Data Interface Modes I2S, Left, Right Justified or DSP 16/20/24/32 bit Word Lengths Master or Slave Clocking Mode Stereo Audio Inputs and Outputs 20-lead SSOP or 5x5mm QFN Package Options

APPLICATIONS

+12 to -34.5dB, 1.5dB Steps +12 to -34.5dB, 1.5dB Steps DCVDD ADCLRC DACLRC BCLK DACDAT ADCDAT MCLK MODE MUTE MUTE VOL W WM8734 CLKIN DIVIDER (Div x1, x2) VOL

w PD Rev 4.1 November 2006 TABLE OF CONTENTS

w PD Rev 4.1 November 2006 PIN CONFIGURATION – SSOP AGND VMID RLINEIN MCLK LLINEIN MODE CSB SDIN SCLK DCVDD BCLK DACDAT DBVDD DGND ADCDAT LOUT DACLRC ADCLRC ROUT AVDD ORDERING INFORMATION - SSOP DEVICE TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE XWM8734EDS -25 to +85oC 20-lead SSOP (Pb-free) MSL1 260°C XWM8734EDS/R -25 to +85oC 20-lead SSOP (Pb-free tape and reel) MSL1 260°C Note: Reel quantity = 2,000

w PD Rev 4.1 November 2006 PIN DESCRIPTION - SSOP PIN NAME TYPE Digital Audio Bit Clock, Pull Down, (see Note 1) DACDAT Digital Input DAC Digital Audio Data Input DACLRC Digital Input/Output DAC Sample Rate Left/Right Clock. Pull Down (see Note 1) ADCDAT Digital Output ADC Digital Audio Data Output ADCLRC Digital Input/Output ADC Sample Rate Left/Right Clock, Pull Down (see Note 1) LOUT Analogue Output Left Channel Line Output ROUT Analogue Output Right Channel Line Output AVDD Supply Analogue VDD AGND Ground Analogue GND VMID Analogue Output Mid-rail reference decoupling point RLINEIN Analogue Input Right Channel Line Input (AC coupled) LLINEIN Analogue Input Left Channel Line Input (AC coupled) MODE Digital Input Control Interface Selection, Pull Up (see Note 1) CSB Digital Input 3-Wire MPU Chip Select / 2-Wire MPU interface address selection, active low, Pull up (see Note 1) SDIN Digital Input/Output 3-Wire MPU Data Input / 2-Wire MPU Data Input SCLK Digital Input 3-Wire MPU Clock Input / 2-Wire MPU Clock Input MCLK Digital Input Master Clock Input (MCLK) DCVDD Supply Digital Core VDD Note: Pull Up/Down only present when Control Register Interface ACTIVE = 0 to conserve power.

w PD Rev 4.1 November 2006 PIN CONFIGURATION – QFN TOP VIEW ORDERING INFORMATION - QFN DEVICE TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM8734SEFL -25 to +85oC 28-lead QFN (5x5x0.9mm) (Pb-free) MSL 1 260°C WM8734SEFL/R -25 to +85oC 28-lead QFN (5x5x0.9mm) (Pb-free, tape and reel) MSL 1 260°C Note: Reel quantity = 3,500

w PD Rev 4.1 November 2006 PIN DESCRIPTION - QFN PIN NAME TYPE Master Clock Input (MCLK) NC Do Not Connect Test Pin, must be left unconnected DCVDD Supply Digital Core VDD DGND Ground Digital GND DBVDD Supply Digital Buffers VDD NC Do Not Connect Test Pin, must be left unconnected BCLK Digital Input/Output Digital Audio Bit Clock, Pull Down, (see Note 1) DACDAT Digital Input DAC Digital Audio Data Input DACLRC Digital Input/Output DAC Sample Rate Left/Right Clock. Pull Down (see Note 1) ADCDAT Digital Output ADC Digital Audio Data Output ADCLRC Digital Input/Output ADC Sample Rate Left/Right Clock, Pull Down (see Note 1) NC Do Not Connect Test Pin, must be left unconnected NC Do Not Connect Test Pin, must be left unconnected NC Do Not Connect Test Pin, must be left unconnected NC Do Not Connect Test Pin, must be left unconnected LOUT Analogue Output Left Channel Line Output ROUT Analogue Output Right Channel Line Output AVDD Supply Analogue VDD AGND Ground Analogue GND VMID Analogue Output Mid-rail reference decoupling point NC Do Not Connect Test Pin, must be left unconnected NC Do Not Connect Test Pin, must be left unconnected RLINEIN Analogue Input Right Channel Line Input (AC coupled) LLINEIN Analogue Input Left Channel Line Input (AC coupled) MODE Digital Input Control Interface Selection, Pull Up (see Note 1) CSB Digital Input 3-Wire MPU Chip Select / 2-Wire MPU interface address selection, active low, Pull up (see Note 1) SDIN Digital Input/Output 3-Wire MPU Data Input / 2-Wire MPU Data Input SCLK Digital Input 3-Wire MPU Clock Input / 2-Wire MPU Clock Input Note: It is recommended that the QFN ground paddle is connected to analogue ground on the application PCB.

w PD Rev 4.1 November 2006 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. CONDITION MIN MAX Digital supply voltage -0.3V +3.63V Analogue supply voltage -0.3V +3.63V Voltage range digital inputs DGND -0.3V DVDD +0.3V Voltage range analogue inputs AGND -0.3V AVDD +0.3V Operating temperature range, TA -25°C +85°C Storage temperature after soldering -65°C +150°C Notes: Analogue and digital grounds must always be within 0.3V of each other. The digital supply core voltage (DCVDD) must always be less than or equal to the analogue supply voltage (AVDD) RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital supply range (Core) DCVDD 2.7 3.6 V Digital supply range (Buffer) DBVDD 2.7 3.6 V Analogue supply range AVDD 2.7 3.6 V Ground DGND, AGND V Total analogue supply current IAVDD DCVDD, DBVDD, AVDD = 3.3V mA Digital supply current IDCVDD, IDBVDD DCVDD, DBVDD AVDD = 3.3V mA Standby Current Consumption uA

w PD Rev 4.1 November 2006

ELECTRICAL CHARACTERISTICS

AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Logic Levels (CMOS Levels) Input LOW level VIL 0.3 x DBVDD V Input HIGH level VIH 0.7 x DBVDD V Output LOW VOL 0.10 x DBVDD V Output HIGH VOH 0.9 x DBVDD V Power On Reset Threshold (DCVDD) DCVDD Threshold On -> Off Vth 0.9 V Hysteresis VIH 0.3 V DCVDD Threshold Off -> On VOL 0.6 V Analogue Reference Levels Reference voltage VVMID AVDD/2 V Potential divider resistance RVMID 50k Ω Line Input to ADC Input Signal Level (0dB) VINLINE 1.0 AVDD/3.3 Vrms A-weighted, 0dB gain @ fs = 48kHz A-weighted, 0dB gain @ fs = 96kHz Signal to Noise Ratio (Note 1,2,3) SNR A-weighted, 0dB gain @ fs = 48kHz, AVDD = 2.7V dB Dynamic Range (Note 3) DNR A-weighted, -60dB full scale input dB Total Harmonic Distortion THD -1dB input, 0dB gain -84 -74 dB 1kHz 100mVpp Power Supply Rejection Ratio PSSR 20Hz to 20kHz 100mVpp dB ADC channel separation 1kHz input dB Programmable Gain 1kHz input Rsource < 50Ω -34.5 +12 dB Programmable Gain Step Size Guaranteed Monotonic 1.5 dB Mute attenuation 0dB, 1kHz input dB 0dB gain 20k 30k Input Resistance RINLINE 12dB gain 10k 15k Ω Input Capacitance CINLINE pF

w PD Rev 4.1 November 2006 Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Line Output for DAC Playback Only (Load = 47kΩΩΩΩ. 50pF) 0dBfs Full scale output voltage At LINE outputs 1.0 x AVDD/3.3 Vrms A-weighted, @ fs = 48kHz 100 A-weighted @ fs = 96kHz Signal to Noise Ratio (Note 1,2,3) SNR A-weighted, @ fs = 48kHz, AVDD = 2.7V dB Dynamic Range (Note 3) DNR A-weighted, -60dB full scale input dB 1kHz, 0dBfs -88 -80 Total Harmonic Distortion THD 1kHz, -3dBfs -92 dB 1kHz 100mVpp Power Supply Rejection Ratio PSSR 20Hz to 20kHz 100mVpp dB DAC channel separation 1kHz, 0dB 100 dB Notes: Ratio of output level with 1kHz full scale input, to the output level with the input short circuited, measured ‘A’ weighted over a 20Hz to 20kHz bandwidth using an Audio analyser. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted over a 20Hz to 20kHz bandwidth. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance). TERMINOLOGY Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Stop band attentuation (dB) – Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. Pass-Band Ripple – Any variation of the frequency response in the pass-band region.

w PD Rev 4.1 November 2006 POWER CONSUMPTION (EXAMPLES) CURRENT CONSUMPTION TYPICAL MODE DESCRIPTION POWEROFF OUTPD DACPD ADCPD LINEINPD AVDD (3.3V) DCVDD (1.5V) DBVDD (3.3V) UNITS Record and Playback 12.2 3.2 0.07 mA Playback Only 3.3 2.3 0.07 mA Record Only 9.2 2.6 0.07 mA Standby (clock running) µA Standby (clock stopped) 0.3 0.2 µA Power Down (clock running) 0.3 µA Power Down (clock stopped) 0.3 0.3 0.3 µA Notes: The data presented here was measured with the audio interface in slave mode (MS = 0) All figures are quiescent, with no signal.

w PD Rev 4.1 November 2006 BCLK DACLRC/ ADCLRC tBCH tBCL tBCY DACDAT ADCDAT tLRSU tDS tLRH tDH tDD Figure 5 Digital Audio Data Timing – Slave Mode Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY ns BCLK pulse width high tBCH ns BCLK pulse width low tBCL ns DACLRC/ADCLRC set-up time to BCLK rising edge tLRSU ns DACLRC/ADCLRC hold time from BCLK rising edge tLRH ns DACDAT set-up time to BCLK rising edge tDS ns DACDAT hold time from BCLK rising edge tDH ns ADCDAT propagation delay from BCLK falling edge tDD ns

w PD Rev 4.1 November 2006 MPU INTERFACE TIMING CSB SCLK SDIN tCSL tDHO tDSU tCSH tSCY tSCH tSCL tSCS LSB tCSS Figure 6 Program Register Input Timing – 3-Wire MPU Serial Control Mode Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CSB rising edge tSCS ns SCLK pulse cycle time tSCY ns SCLK pulse width low tSCL ns SCLK pulse width high tSCH ns SDIN to SCLK set-up time tDSU ns SCLK to SDIN hold time tDHO ns CSB pulse width low tCSL ns CSB pulse width high tCSH ns CSB rising to SCLK rising tCSS ns

w PD Rev 4.1 November 2006 SDIN SCLK t10 Figure 7 Program Register Input Timing – 2-Wire MPU Serial Control Mode Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Program Register Input Information SCLK Frequency 526 kHz SCLK Low Pulsewidth 1.3 us SCLK High Pulsewidth 600 ns Hold Time (Start Condition) 600 ns Setup Time (Start Condition) 600 ns Data Setup Time 100 ns SDIN, SCLK Rise Time 300 ns SDIN, SCLK Fall Time 300 ns Setup Time (Stop Condition) 600 ns Data Hold Time t10 900 ns

w PD Rev 4.1 November 2006 DEVICE DESCRIPTION The WM8734 is a high performance audio CODEC designed specifically for audio applications that require recording and playback features. The CODEC includes line inputs to the on-board ADC, line outputs from the on-board DAC, a configurable digital audio interface and a choice of 2 or 3 wire MPU control interface. It is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and DSPs. The CODEC includes a stereo low noise input. Line inputs have +12dB to -34dB logarithmic volume level adjustments and mute. All the required input filtering is contained within the device. The on-board stereo analogue to digital converter (ADC) is of a high quality using a multi-bit high- order oversampling architecture delivering optimum performance with low power consumption. The output from the ADC is available on the digital audio interface. The ADC includes an optional digital high pass filter to remove unwanted dc components from the audio signal. The on-board digital to analogue converter (DAC) accepts digital audio from the digital audio interface. Digital filter de-emphasis at 32kHz, 44.1kHz and 48kHz can be applied to the digital data under software control. The DAC employs a high quality multi-bit high-order oversampling architecture to again deliver optimum performance with low power consumption. Special techniques allow the audio to be muted and the device safely placed into standby, sections of the device powered off and volume levels adjusted without any audible clicks, pops or zipper noises. Therefore standby and power off modes may be used dynamically under software control, whenever recording or playback is not required. The device caters for a number of different sampling rates including industry standard 8kHz, 32kHz, 44.1kHz, 48kHz, 88.2kHz and 96kHz. The digital filters used for both record and playback are optimised for each sampling rate used. The digitised output is available in a number of audio data formats I2S, DSP Mode (a burst mode in which frame sync plus 2 data packed words are transmitted), MSB-First, left justified and MSB-First, right justified. The digital audio interface can operate in both master or slave modes. The software control uses either a 2 or 3-wire MPU interface. AUDIO SIGNAL PATH LINE INPUTS The WM8734 provides Left and Right channel line inputs (RLINEIN and LLINEIN). The inputs are high impedance and low capacitance, thus ideally suited to receiving line level signals from external hi-fi or audio equipment. Both line inputs include independent programmable volume level adjustments and input mute. The scheme is illustrated in Figure 8. Passive RF and active Anti-Alias filters are also incorporated within the line inputs. These prevent high frequencies aliasing into the audio band or otherwise degrading performance.

w PD Rev 4.1 November 2006 12.5K VMID LINEIN To ADC Figure 8 Line Input Schematic The gain between the line inputs and the ADC is logarithmically adjustable from +12dB to –34.5dB in voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with AVDD. The gain is independently adjustable on both Right and Left Line Inputs. However, by setting the INBOTH bit whilst programming the volume control, both channels are simultaneously updated with the same value. Use of INBOTH reduces the required number of software writes required. The line inputs to the ADC can be muted in the analogue domain under software control. The software control registers are shown below. REGISTER ADDRESS BIT LABEL DEFAULT 4:0 LINVOL[4:0] 10111 ( 0dB ) Left Channel Line Input Volume Control 11111 = +12dB . . 1.5dB steps down to 00000 = -34.5dB LINMUTE Left Channel Line Input Mute to ADC 1 = Enable Mute 0 = Disable Mute 0000000 Left Line In LRINBOTH Left to Right Channel Line Input Volume and Mute Data Load Control 1 = Enable Simultaneous Load of LINVOL[4:0] and LINMUTE to RINVOL[4:0] and RINMUTE 0 = Disable Simultaneous Load 4:0 RINVOL[4:0] 10111 ( 0dB ) Right Channel Line Input Volume Control 11111 = +12dB . .1.5dB steps down to 00000 = -34.5dB RINMUTE Right Channel Line Input Mute to ADC 1 = Enable Mute 0 = Disable Mute 0000001 Right Line In RLINBOTH Right to Left Channel Line Input Volume and Mute Data Load Control 1 = Enable Simultaneous Load of RINVOL[4:0] and RINMUTE to LINVOL[4:0] and LINMUTE 0 = Disable Simultaneous Load Table 1 Line Input Software Control

w PD Rev 4.1 November 2006 The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with AVDD. The device employs a pair of ADCs. The two channels cannot be selected independently. The digital data from the ADC is fed for signal processing to the ADC Filters. ADC FILTERS The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. Figure 11 illustrates the digital filter path. FROM ADC DIGITAL HPF DIGITAL DECIMATION FILTER TO DIGITAL AUDIO INTERFACE DIGITAL DECIMATOR HPFEN Figure 11 ADC Digital Filter The ADC digital filters contain a digital high pass filter, selectable via software control. The high-pass filter response detailed in Digital Filter Characteristics. When the high-pass filter is enabled the dc offset is continuously calculated and subtracted from the input signal. By setting HPOR the last calculated dc offset value is stored when the high-pass filter is disabled and will continue to be subtracted from the input signal. If the dc offset changed, the stored and subtracted value will not change unless the high-pass filter is enabled. The software control is shown in Table 2. REGISTER ADDRESS BIT LABEL DEFAULT ADC High Pass Filter Enable (Digital) 1 = Disable High Pass Filter 0 = Enable High Pass Filter 00000101 Digital Audio Path Control HPOR Store dc offset when High Pass Filter disabled 1 = store offset 0 = clear offset Table 2 ADC Software Control There are several types of ADC filters, frequency and phase responses of these are shown in Digital Filter Characteristics. The filter types are automatically configured depending on the sample rate chosen. Refer to the sample rate section for more details. DAC FILTERS The DAC filters perform true 24 bit signal processing to convert the incoming digital audio data from the digital audio interface at the specified sample rate to multi-bit oversampled data for processing by the analogue DAC. Figure 12 illustrates the DAC digital filter path.

w PD Rev 4.1 November 2006 Recommended values are C1 = 470nF (10V npo type), R1 = 47KΩ, R2 = 100Ω C1 forms a DC blocking capacitor to the line outputs. R1 prevents the output voltage from drifting so protecting equipment connected to the line output. R2 forms a de-coupling resistor preventing abnormal loads from disturbing the device. Note that poor choice of dielectric material for C1 can have dramatic effects on the measured signal distortion at the output. DEVICE OPERATION DEVICE RESETTING The WM8734 contains a power on reset circuit that resets the internal state of the device to a known condition. The power on reset is applied as DCVDD powers on and released only after the voltage level of DCVDD crosses a minimum turn off threshold. If DCVDD later falls below a minimum turn on threshold voltage then the power on reset is re-applied. The threshold voltages and associated hysteresis are shown in the Electrical Characteristics table. The user also has the ability to reset the device to a known state under software control as shown in the table below. REGISTER ADDRESS BIT LABEL DEFAULT 8:0 RESET not reset Reset Register Writing 00000000 to register resets device Table 5 Software Control of Reset When using the software reset. In 3-wire mode the reset is applied on the rising edge of CSB and released on the next rising edge of SCLK. In 2-wire mode the reset is applied for the duration of the ACK signal (approximately 1 SCLK period, refer to Figure 24). CLOCKING SCHEMES In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s Master Clock. To allow WM8734 to be used in a centrally clocked system, the WM8734 is capable of deriving the sample rate clock from this Master Clock (Master Mode) or receiving the sample rate clock from an external source (Slave Mode). CORE CLOCK The WM8734 DSP core can be clocked either by MCLK or MCLK divided by 2. This is controlled by software as shown in Table 6 below. REGISTER ADDRESS BIT LABEL DEFAULT 1 = Core Clock is MCLK divided by 2 0 = Core Clock is MCLK Table 6 Software Control of Core Clock Having a programmable MCLK divider allows the device to be used in applications where higher frequency master Clocks are available. For example the device can support 512fs master clocks whilst fundamentally operating in a 256fs mode. DIGITAL AUDIO INTERFACES WM8734 may be operated in either one of the 4 offered audio interface modes. These are:

• Right justified
• Left justified
• I2S
• DSP mode All four of these modes are MSB first and operate with data 16 to 32 bits, except right justified mode which does not support 32 bits.

w PD Rev 4.1 November 2006 The digital audio interface takes the data from the internal ADC digital filter and places it on the ADCDAT output. ADCDAT is the formatted digital audio data stream output from the ADC digital filters with left and right channels multiplexed together. ADCLRC is an alignment clock that controls whether Left or Right channel data is present on the ADCDAT lines. ADCDAT and ADCLRC are synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low transition. BCLK maybe an input or an output dependent on whether the device is in master or slave mode. Refer to the MASTER/SLAVE OPERATION section. The digital audio interface also receives the digital audio data for the internal DAC digital filters on the DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters with left and right channels multiplexed together. DACLRC is an alignment clock that controls whether Left or Right channel data is present on DATDAT. DACDAT and DACLRC are synchronous with the BCLK signal with each data bit transition signified by a BCLK transition. DACDAT is always an input. BCLK and DACLRC are either outputs or inputs depending whether the device is in master or slave mode. Refer to the MASTER/SLAVE OPERATION section There are four digital audio interface formats accommodated by the WM8734. These are shown in the figures below. Refer to the Electrical Characteristic section for timing information. Left Justified mode is where the MSB is available on the first rising edge of BCLK following a ADCLR or DACLRC transition. LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC BCLK DACDAT/ ADCDAT 1/fs n n-2 n-1 LSB MSB n n-2 n-1 LSB MSB Figure 16 Left Justified Mode I2S mode is where the MSB is available on the 2nd rising edge of BCLK following a DACLRC or ADCLRC transition. LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC BCLK DACDAT/ ADCDAT 1/fs n n-2 n-1 LSB MSB n n-2 n-1 LSB MSB

1 BCLK

Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a DACLRC or ADCLRC transition, yet MSB is still transmitted first.

16, Figure 17, Figure 18, Figure 19 and Figure 20. number of BCLK cycles to suit the chosen word length. ratios need more careful consideration. In Slave mode, DACLRC and ADCLRC inputs are not required to have a 50:50 mark-space ratio. each DACLRC/ADCLRC transition to clock the chosen data word length. The ADC and DAC digital audio interface modes are software configurable as indicated in Table 7. 16/20/24 or 32 bits. Refer to the software control table below. The data is signed 2’s complement. programmed to receive 32 bit data, then it strips the LSBs. Table 7. Stereo samples are normally generated as a Left/Right sampled pair. LRSWAP reverses the correct channel phase difference. controlled vias the software shown in Table 6. This is especially appropriate for DSP mode. ADCDAT lines are always outputs. They power up and return from standby low. WM8734 is powered off or in standby.

w PD Rev 4.1 November 2006 REGISTER ADDRESS BIT LABEL DEFAULT 1:0 FORMAT[1:0] Audio Data Format Select 11 = DSP Mode, frame sync + 2 data packed words 10 = I2S Format, MSB-First left-1 justified 01 = MSB-First, left justified 00 = MSB-First, right justified 3:2 IWL[1:0] Input Audio Data Bit Length Select 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits LRP DACLRC phase control (in left, right or I2S modes) 1 = Right Channel DAC data when DACLRC high 0 = Right Channel DAC data when DACLRC low (opposite phasing in I2S mode) or DSP mode A/B select (in DSP mode only) 1 = MSB is available on 2nd BCLK rising edge after ADCLRC/DACLRC rising edge 0 = MSB is available on 1st BCLK rising edge after ADCLRC/DACLRC rising edge LRSWAP DAC Left Right Clock Swap 1 = Right Channel DAC Data Left 0 = Right Channel DAC Data Right MS Master Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode 0000111 Digital Audio Interface Format BCLKINV Bit Clock Invert 1 = Invert BCLK 0 = Don’t invert BCLK Table 7 Digital Audio Interface Control Note: If right justified 32 bit mode is selected then the WM8734 defaults to 24 bits. MASTER AND SLAVE MODE OPERATION The WM8734 can be configured as either a master or slave mode device. As a master mode device the WM8734 controls sequencing of the data and clocks on the digital audio interface. As a slave device the WM8734 responds with data to the clocks it receives over the digital audio interface. The mode is set with the MS bit of the control register as shown in Table 8. REGISTER ADDRESS BIT LABEL DEFAULT 1 = Enable Master Mode 0 = Enable Slave Mode Table 8 Programming Master/Slave Modes

w PD Rev 4.1 November 2006 Uniquely, the WM8734 offers the user the ability to sample the ADC and DAC at different rates under software control in both Normal and USB modes. The reduces the burden on any controlling DSP. However, the signal processing in the ADC and DAC over-sampling filters is tightly coupled together in order to minimise power consumption. To this end, only the combinations of sample rates listed in the following sections are supported. Note that these rates supported are anticipated to be the likely combinations used in typical audio systems. REGISTER ADDRESS BIT LABEL DEFAULT 1 = USB mode (250/272fs) 0 = Normal mode (256/384fs) BOSR Base Over-Sampling Rate USB Mode 0 = 250fs 1 = 272fs Normal Mode 96/88.2 kHz 0 = 256fs 0 = 128fs 1 = 384fs 1 = 192fs 0001000 Sampling Control 5:2 SR[3:0] 0000 ADC and DAC sample rate control; See USB Mode and Normal Mode Sample Rate sections for operation Table 9 Sample Rate Control SAMPLE RATE SETTING In normal mode MCLK/crystal oscillator is set up according to the desired sample rates of the ADC and DAC. For ADC or DAC sampling rates of 8, 32, 48 or 96kHz, MCLK frequencies of either 12.288MHz (256fs) or 18.432MHz (384fs) can be used. For ADC or DAC sampling rates of 8, 44.1 or 88.2kHz from MCLK frequencies of either 11.2896MHz (256fs) or 16.9344MHz (384fs) can be used. The table below should be used to set up the device to work with the various sample rate combinations. For example if the user wishes to use the WM8734 in normal mode with the ADC and DAC sample rates at 48kHz and 48kHz respectively then the device should be programmed with BOSR = 0, SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0 with a 12.288MHz MCLK or with BOSR = 1, SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0 with a 18.432MHz MCLK. The ADC and DAC will then operate with a Digital Filter of type 1, refer to Digital Filter Characteristics section for an explanation of the different filter types.

w PD Rev 4.1 November 2006 SAMPLING RATE ADC DAC MCLK FREQUENCY SAMPLE RATE REGISTER SETTINGS DIGITAL FILTER TYPE kHz kHz MHz BOSR SR3 SR2 SR1 SR0 12.288 0 (256fs) 18.432 1 (384fs) 12.288 0 (256fs) 18.432 1 (384fs) 12.288 0 (256fs) 18.432 1 (384fs) 12.288 0 (256fs) 18.432 1 (384fs) 12.288 0 (256fs) 18.432 1 (384fs) 12.288 0 (128fs) 18.432 1 (192fs) 11.2896 0 (256fs) 44.1 44.1 16.9344 1 (384fs) 11.2896 0 (256fs) 44.1 (Note 1) 16.9344 1 (384fs) 11.2896 0 (256fs) (Note 1) 44.1 16.9344 1 (384fs) 11.2896 0 (256fs) (Note 1) (Note 1) 16.9344 1 (384fs) 11.2896 0 (128fs) 88.2 88.2 16.9344 1 (192fs) Table 10 Normal Mode Sample Rate Look-up Table Notes: 8k not exact, actual = 8.018kHz All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid The BOSR bit represents the base over-sampling rate. This is the rate that the WM8734 digital signal processing is carried out at. In Normal mode, with BOSR = 0, the base over-sampling rate is at 256fs, with BOSR = 1, the base over-sampling rate is at 384fs. This can be used to determine the actual audio data rate produced by the ADC and required by the DAC. Example scenarios are: with a requirement that the ADC data rate is 8kHz and DAC data rate is 48kHz, then choosing MCLK = 12.288MHz the device is programmed with BOSR = 0 (256fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 = 0.The ADC output data rate will then be exactly 8kHz (derived from 12.288MHz/256 x1/6) and the DAC expects data at exactly 48kHz (derived from 12.288MHz/256) with a requirement that ADC data rate is 8kHz and DAC data rate is 44.1kHz, then choosing MCLK = 16.9344MHz the device is programmed with BOSR = 1 (384fs), SR3 = 1, SR2 = 0, SR1 = 0, SR0 = 1. The ADC will no longer output data at exactly 8.000kHz, instead it will be 8.018kHz (derived from 16.9344MHz/384 x 2/11), the DAC still is at exactly 44.1kHz (derived from 16.9344MHz/384). A slight (sub 0.5%) pitch shift will therefore result in the 8kHz audio data and (importantly) the user must ensure that the data across the digital interface is correctly synchronised at the 8.018kHz rate.

w PD Rev 4.1 November 2006 The exact sample rates achieved are defined by the relationships in Table 11 below. ACTUAL SAMPLING RATE BOSR=0 BOSR=1 TARGET SAMPLING RATE MCLK=12.288 MCLK=11.2896 MCLK=18.432 MCLK=16.9344 kHz kHz kHz kHz kHz 8.018 8.018 (12.288MHz/256) x 1/6 (11.2896MHz/256) x 2/11 (18.432MHz/384) x 1/6 (16.9344MHz/384) x 2/11 (12.288MHz/256) x 2/3 not available (18.432MHz/384)x 2/3 not available 44.1 44.1 44.1 not available 11.2896MHz/256 not available 16.9344MHz /384 12.288MHz/256 not available 18.432MHz/384 not available 88.2 88.2 88.2 not available (11.2896MHz/384) x 2 not available (16.9344MHz /384) x 2 (12.288MHz/256) x 2 not available (18.432MHz/384) x 2 not available Table 11 Normal Mode Actual Sample Rates 128/192fs NORMAL MODE The Normal Mode sample rates are designed for standard 256fs and 384fs MCLK rates. However the WM8734 is also capable of being clocked from a 128 or 192fs MCLK for application over limited sampling rates as shown in the table below. SAMPLING RATE ADC DAC MCLK FREQUENCY SAMPLE RATE REGISTER SETTINGS DIGITAL FILTER TYPE kHz kHz MHz BOSR SR3 SR2 SR1 SR0 6.144 9.216 5.6448 44.1 44.1 8.4672 Table 12 128fs Normal Mode Sample Rate Look-up Table 512/768fs NORMAL MODE 512 fs and 768 fs MCLK rates can be accommodated by using the CLKIDIV2 bit. The core clock to the DSP will be divided by 2 so an external 512/768 MCLK will become 256/384 fs internally and the device otherwise operates as in Table 8 but with MCLK at twice the specified rate. See Table 6 for software control.

w PD Rev 4.1 November 2006 USB MODE SAMPLE RATES In USB mode the MCLK/crystal oscillator input is 12MHz only. SAMPLING RATE ADC DAC MCLK FREQUENCY SAMPLE RATE REGISTER SETTINGS DIGITAL FILTER TYPE kHz kHz MHz BOSR SR3 SR2 SR1 SR0 12.000 44.1 (Note 2) 44.1 (Note 2) 12.000 12.000 44.1 (Note 2) (Note 1) 12.000 12.000 (Note 1) 44.1 (Note 2) 12.000 12.000 (Note 1) (Note 1) 12.000 12.000 12.000 88.2 (Note 3) 88.2 (Note 3) 12.000 Table 13 USB Mode Sample Rate Look-ip Table Notes: 8k not exact, actual = 8.021kHz 44.1k not exact, actual = 44.118kHz 88.1k not exact, actual = 88.235kHz All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid The table above can be used to set up the device to work with various sample rate combinations. For example if the user wishes to use the WM8734 in USB mode with the ADC and DAC sample rates at 48kHz and 48kHz respectively then the device should be programmed with BOSR = 0, SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0. The ADC and DAC will then operate with a Digital Filter of type 0, refer to Digital Filter Characteristics section for an explanation of the different filter types. The BOSR bit represents the base over-sampling rate. This is the rate that the WM8734 digital signal processing is carried out at and the sampling rate will always be a sub-multiple of this. In USB mode, with BOSR = 0, the base over-sampling rate is defined at 250fs, with BOSR = 1, the base over- sampling rate is defined at 272fs. This can be used to determine the actual audio sampling rate produced by the ADC and required by the DAC. Example scenarios are, :- with a requirement that the ADC data sampling rate is 8kHz and DAC data sampling rate is 48kHz the device is programmed with BOSR = 0 (250fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 = 0.The ADC will then be exactly 8kHz ( derived from 12MHz/250 x 1/6 ) and the DAC expects data at exactly 48kHz ( derived from 12MHz/250 ). with a requirement that ADC data rate is 8kHz and DAC data rate is 44.1kHz the device is programmed with BOSR = 0 (272fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 = 0. The ADC will not output data at exactly 8kHz, instead it will be 8.021kHz ( derived from 12MHz/272 x 2/11 ) and the DAC at 44.118kHz ( derived from 12MHz/272 ). A slight (sub 0.5%) pitch shift will therefore results in the 8kHz and 44.1kHz audio data and (more importantly) the user must ensure that

w PD Rev 4.1 November 2006 the data across the digital interface is correctly synchronised at the 8.021kHz and 44.117kHz rates. The exact sample rates supported for all combinations are defined by the relationships in Table 14 below. ACTUAL SAMPLING RATE TARGET SAMPLING RATE BOSR=0 ( 250fs) BOSR=1 (272fs) kHz kHz kHz 8.021 12MHz/(250 x 48/8) 12MHz/(272 x 11/2) 12MHz/(250 x 48/32) not available 44.117 44.1 not available 12MHz/272 12MHz/250 not available 88.235 88.2 not available 12MHz/136 12MHz/125 not available Table 14 USB Mode Actual Sample Rates ACTIVATING DSP AND DIGITAL AUDIO INTERFACE To prevent any communication problems from arising across the Digital Audio Interface the Audio Interface is disabled (tristate with weak 100k pulldown). Once the Audio Interface and the Sampling Control has been programmed it is activated by setting the ACTIVE bit under Software Control. REGISTER ADDRESS BIT LABEL DEFAULT 1 = Active 0 = Inactive Table 15 Activating DSP and Digital Audio Interface It is recommended that between changing any content of Digital Audio Interface or Sampling Control Register that the active bit is reset then set. SOFTWARE CONTROL INTERFACE The software control interface may be operated using either a 3-wire (SPI-compatible) or 2-wire MPU interface. Selection of interface format is achieved by setting the state of the MODE pin. In 3-wire mode, SDIN is used for the program data, SCLK is used to clock in the program data and CSB is used to latch in the program data. In 2-wire mode, SDIN is used for serial data and SCLK is used for the serial clock. In 2-wire mode, the state of CSB pin allows the user to select one of two addresses. Unused register bits should always be set to ‘0’ unless specified otherwise. SELECTION OF SERIAL CONTROL MODE The serial control interface may be selected to operate in either 2 or 3-wire modes. This is achieved by setting the state of the MODE pin. MODE INTERFACE FORMAT 2 wire 3 wire Table 16 Control Interface Mode Selection

w PD Rev 4.1 November 2006 A stop condition is defined when there is a low to high transition on SDIN while SCLK is high. If a start or stop condition is detected out of sequence at any point in the data transfer then the device will jump to the idle condition. After receiving a complete address and data sequence the WM8734 returns to the idle state and waits for another start condition. Each write to a register requires the complete sequence of start condition, device address and R/W bit followed by the 16 register address and data bits. Note that the 16 bit control word is made up of 7 address bits, B[15:9], and 9 data bits, B[8:0]. These are transmitted as 2 blocks of 8 bits. The first block contains 7 address bits and the data HSB. The second block contains the 8 data LSBs. POWER DOWN MODES The WM8734 contains power conservation modes in which various circuit blocks may be safely powered down in order to conserve power. This is software programmable as shown in the table below. REGISTER ADDRESS BIT LABEL DEFAULT 1 = Enable Power Down 0 = Disable Power Down ADCPD ADC Power Down 1 = Enable Power Down 0 = Disable Power Down DACPD DAC Power Down 1 = Enable Power Down 0 = Disable Power Down OUTPD Line Output Power Down 1 = Enable Power Down 0 = Disable Power Down 0000110 Power Down Control POWEROFF Power Off Device 1 = Device Power Off 0 = Device Power On Table 18 Power Conservation Modes Software Control When writing to the powerdown register bits 1,5 and 6 should be set to ‘1’. The power down control can be used to either a) permanently disable functions when not required in certain applications or b) to dynamically power up and down functions depending on the operating mode, e.g.: during playback or record. Please follow the special instructions below if dynamic implementations are being used. LINEINPD: Simultaneously powers down both the Line Inputs. This can be done dynamically without any audible effects either on the ADC or to the Line Outputs in Bypass mode. This is of use when the device enters Playback, Pause or Stop modes or the Microphone input has been selected. ADCPD: Powers down the ADC and ADC Filters. If this is done dynamically then audible pops will result if any signals were present through the ADC. To overcome this whenever the ADC is to be powered down, either mute the Microphone Input (MUTEIN) or MUTELINEIN, then change ADCPD. This is of use when the device enters Playback, Pause or Stop modes regardless of whether Microphone or Line Inputs are selected. DACPD: Powers down the DAC and DAC Digital Filters. If this is done dynamically then audible pops will result unless the following guidelines are followed. In order to prevent pops, the DAC should first be soft-muted (DACMU), the output should then be de-selected from the line and headphone output (DACSEL), then the DAC powered down (DACPD). This is of use when the device enters Record, Pause, Stop or Bypass modes. The device can be put into a standby mode (STANDBY) by powering down all the audio circuitry under software control as shown in Table 18. Provision has been made to independently power off these areas according to Table 19.

w PD Rev 4.1 November 2006 POWER OFF DACPD ADCPD LINEINPD OUTPD In STANDBY mode the Control Interface, a small portion of the digital and areas of the analogue circuitry remain active. The active analogue includes the analogue VMID reference so that the analogue line inputs, line outputs and headphone outputs remain biased to VMID. This reduces any audible effects caused by DC glitches when entering or leaving STANDBY mode. The device can be powered off by writing to the POWEROFF bit of the Power Down register. In POWEROFF mode the Control Interface and a small portion of the digital remain active. The analogue VMID reference is disabled. POWER OFF DACPD ADCPD LINEINPD OUTPD X X X X POWEROFF Table 20 Poweroff Mode

w PD Rev 4.1 November 2006 REGISTER MAP The complete register map is shown in Table 21. The detailed description can be found in the relevant text of the device description. There are 8 registers with 9 bits per register. These can be controlled using either the 2 wire or 3 wire MPU interface. REGISTER ADDRESS BIT LABEL DEFAULT 4:0 LINVOL[4:0] 10111 ( 0dB ) Left Channel Line Input Volume Control 11111 = +12dB . . 1.5dB steps down to 00000 = -34.5dB LINMUTE Left Channel Line Input Mute to ADC 1 = Enable Mute 0 = Disable Mute 0000000 Left Line In LRINBOTH Left to Right Channel Line Input Volume and Mute Data Load Control 1 = Enable Simultaneous Load of LINVOL[4:0] and LINMUTE to RINVOL[4:0] and RINMUTE 0 = Disable Simultaneous Load 4:0 RINVOL[4:0] 10111 ( 0dB ) Right Channel Line Input Volume Control 11111 = +12dB . .1.5dB steps down to 00000 = -34.5dB RINMUTE Right Channel Line Input Mute to ADC 1 = Enable Mute 0 = Disable Mute 0000001 Right Line In RLINBOTH Right to Left Channel Line Input Volume and Mute Data Load Control 1 = Enable Simultaneous Load of RINVOL[4:0] and RINMUTE to LINVOL[4:0] and LINMUTE 0 = Disable Simultaneous Load 0000100 Analogue Audio Path Control DACSEL DAC Select 1 =Select DAC 0 = Don’t select DAC ADCHPD ADC High Pass Filter Enable 1 = Enable High Pass Filter 0 = Disable High Pass Filter 2:1 DEEMP[1:0] De-emphasis Control 11 = 48kHz 10 = 44.1kHz 01 = 32kHz 00 = Disable DACMU DAC Soft Mute Control 1 = Enable soft mute 0 = Disable soft mute 0000101 Digital Audio Path Control HPOR Store dc offset when High Pass Filter disabled 1 = store offset 0 = clear offset

w PD Rev 4.1 November 2006 REGISTER ADDRESS BIT LABEL DEFAULT 1 = Enable Power Down 0 = Disable Power Down ADCPD ADC Power Down 1 = Enable Power Down 0 = Disable Power Down DACPD DAC Power Down 1 = Enable Power Down 0 = Disable Power Down OUTPD Line Output Power Down 1 = Enable Power Down 0 = Disable Power Down 0000110 Power Down Control POWEROFF POWEROFF mode 1 = Enable POWEROFF 0 = Disable POWEROFF 1:0 FORMAT[1:0] Audio Data Format Select 11 = DSP Mode, frame sync + 2 data packed words 10 = I2S Format, MSB-First left-1 justified 01 = MSB-First, left justified 00 = MSB-First, right justified 3:2 IWL[1:0] Input Audio Data Bit Length Select 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits LRP DACLRC phase control (in left, right or I2S modes) 1 = Right Channel DAC data when DACLRC high 0 = Right Channel DAC data when DACLRC low (opposite phasing in I2S mode) or DSP mode A/B select (in DSP mode only) 1 = MSB is available on 2nd BCLK rising edge after ADCLRC/DACLRC rising edge 0 = MSB is available on 1st BCLK rising edge after ADCLRC/DACLRC rising edge LRSWAP DAC Left Right Clock Swap 1 = Right Channel DAC Data Left 0 = Right Channel DAC Data Right MS Master Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode 0000111 Digital Audio Interface Format BCLKINV Bit Clock Invert 1 = Invert BCLK 0 = Don’t invert BCLK

w PD Rev 4.1 November 2006 REGISTER ADDRESS BIT LABEL DEFAULT 1 = USB mode (250/272fs) 0 = Normal mode (256/384fs) BOSR Base Over-Sampling Rate 0 = 256fs 1 = 384fs 5:2 SR[3:0] 0000 ADC and DAC sample rate control 0001000 Sampling Control CLKIDIV2 Core Clock divider select 1 = Core Clock is MCLK divided by 2 0 = Core Clock is MCLK 0001001 Active Control ACTIVE Activate Interface 1 = Active 0 = Inactive Table 21 Register Map Description Note: Unused register bits should be set to ‘0’ except when writing to Register 0000110, when bits 1,5 and 6 should be set to ‘1’. DIGITAL FILTER CHARACTERISTICS The ADC and DAC employ different digital filters. There are 4 types of digital filter, called Type 0, 1, 2 and 3. The performance of Types 0 and 1 is listed in the table below, the responses of all filters is shown in the proceeding pages. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC Filter Type 0 (USB Mode, 250fs operation) +/- 0.05dB 0.416fs Passband -6dB 0.5fs Passband Ripple +/- 0.05 dB Stopband 0.584fs Stopband Attenuation f > 0.584fs -60 dB ADC Filter Type 1 (USB mode, 272fs or Normal mode operation) +/- 0.05dB 0.4535fs Passband -6dB 0.5fs Passband Ripple +/- 0.05 dB Stopband 0.5465fs Stopband Attenuation f > 0.5465fs -60 dB High Pass Filter Corner Frequency -3dB -0.5dB -0.1dB 3.7 10.4 21.6 Hz DAC Filter Type 0 (USB mode, 250fs operation) +/- 0.03dB 0.416fs Passband -6dB 0.5fs Passband Ripple +/-0.03 dB Stopband 0.584fs Stopband Attenuation f > 0.584fs -50 dB DAC Filter Type 1 (USB mode, 272fs or Normal mode operation) +/- 0.03dB 0.4535fs Passband -6dB 0.5fs Passband Ripple +/- 0.03 dB Stopband 0.5465fs Stopband Attenuation f > 0.5465fs -50 dB Table 22 Digital Filter Characteristics

w PD Rev 4.1 November 2006 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 39 External Components Diagram Notes: Diagram above is for SSOP package. QFN external components are the same. Where possible, it is recommended that NPO or COG type capacitors should be used for best performance. For added strength and heat dissipation, it is recommended that the GND_PADDLE (Pin 33) is connected to AGND.

w PD Rev 4.1 November 2006 MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS To minimise any pop or click noise when the system is powered up or down, the following procedures are recommended. POWER UP SEQUENCE Switch on power supplies. By default the WM8734 is in Standby Mode, the DAC is digitally muted and the Audio Interface and Outputs are all OFF. Set all required bits in the Power Down register (0Ch) to ‘0’; EXCEPT the OUTPD bit, this should be set to ‘1’ (Default). Set required values in all other registers except 12h (Active). Set the ‘Active’ bit in register 12h. The last write of the sequence should be setting OUTPD to ‘0’ (active) in register 0Ch, enabling the DAC signal path, free of any significant power-up noise. POWER DOWN SEQUENCE Set the OUTPD bit to ‘1’ (power down). Remove the WM8734 supplies.

w PD Rev 4.1 November 2006 PACKAGE DIMENSIONS (SSOP) NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. DM0015.C DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm) Symbols Dimensions (mm) MIN NOM MAX A ----- ----- 2.0 0.05 ----- ----- 1.65 1.75 1.85 b 0.22 0.30 0.38 c 0.09 ----- 0.25 D 6.90 7.20 7.50 e

0.65 BSC

E 7.40 7.80 8.20 5.00 5.30 5.60 L 0.55 0.75 0.95 θθθθ REF: A A2 SEATING PLANE -C- 0.10 C D e b E JEDEC.95, MO 150

1.25 REF

ΘΘΘΘ c L GAUGE PLANE 0.25 L 1

w PD Rev 4.1 November 2006 PACKAGE DIMENSIONS (QFN) NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. DIMENSION L1 REPRESENTS TERMINAL PULL BACK FROM PACKAGE SIDE WALL. MAXIMUM OF 0.1mm IS ACCEPTABLE. WHERE TERMINAL PULL BACK EXISTS, ONLY UPPER HALF OF LEAD IS VISIBLE ON PACKAGE SIDE WALL DUE TO HALF ETCHING OF LEADFRAME. 2. FALLS WITHIN JEDEC, MO-220 WITH THE EXCEPTION OF D2, E2: D2,E2: LARGER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION 3. ALL DIMENSIONS ARE IN MILLIMETRES 4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 5. SHAPE AND SIZE OF CORNER TIE BAR MAY VARY WITH PACKAGE TERMINAL COUNT. CORNER TIE BAR IS CONNECTED TO EXPOSED PAD INTERNALLY 6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING. DM023.G FL: 28 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.9 mm BODY, 0.50 mm LEAD PITCH C aaa INDEX AREA (D/2 X E/2) C aaa 2 X 2 X TOP VIEW D E C 0.08 C ccc A C (A3) SEATING PLANE b L D2/2 E2/2 SEE DETAIL B B C ccc M A B B A A e CORNER TIE BAR DETAIL A B C bbb M A 28x b L 28x K R 0.566 mm CORNER TIE BAR 0.15 DETAIL B TERMINAL TIP R DATUM e e/2 SEE DETAIL A Symbols Dimensions (mm) MIN NOM MAX NOTE A b D E e L R 0.85 0.90 1.00 0.05 0.02

0.2 REF

0.30 0.23 0.18

5.00 BSC

3.4 3.3 3.2

0.5 BSC

3.3 3.4 3.2 0.35 0.4 0.45 0.1 b(min)/2 K 0.20 aaa bbb ccc REF: 0.15 0.10 0.10 JEDEC, MO-220, VARIATION VHHD-1 Tolerances of Form and Position EXPOSED GROUND PADDLE EXPOSED GROUND PADDLE BOTTOM VIEW SIDE VIEW 0.38mm 0.210mm

w PD Rev 4.1 November 2006 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc

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