Driver IC

WM8731SEFL/R

Wolfson Microelectronic...

Portable Internet Audio CODEC with Headphone Driver and Programmable Sample Rates

Manufacturer: Wolfson Microelectronic...

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Portable Internet Audio CODEC with Headphone Driver and Programmable Sample Rates WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ Production Data, April 2009, Rev 4.8 Copyright ©2009 Wolfson Microelectronics plc

DESCRIPTION

The WM8731 or WM8731L (WM8731/L) are low power stereo CODECs with an integrated headphone driver. The WM8731/L is designed specifically for portable MP3 audio and speech players and recorders. The WM8731 is also ideal for MD, CD-RW machines and DAT recorders. Stereo line and mono microphone level audio inputs are provided, along with a mute function, programmable line level volume control and a bias voltage output suitable for an electret type microphone. Stereo 24-bit multi-bit sigma delta ADCs and DACs are used with oversampling digital interpolation and decimation filters. Digital audio input word lengths from 16-32 bits and sampling rates from 8kHz to 96kHz are supported. Stereo audio outputs are buffered for driving headphones from a programmable volume control, line level outputs are also provided along with anti-thump mute and power up/down circuitry. The device is controlled via a 2 or 3 wire serial interface. The interface provides access to all features including volume controls, mutes, de-emphasis and extensive power management facilities. The device is available in a small 28- lead SSOP package or the smaller 28 lead quad flat leadless package (QFN).

FEATURES

Highly Efficient Headphone Driver
Audio Performance - ADC SNR 90dB (‘A’ weighted) at 3.3V, 85dB at 1.8V - DAC SNR 100dB (‘A’ weighted) at 3.3V, 95dB at 1.8V
Low Power - Playback only 22mW, 8mW (‘L’ Variant) - Analogue Pass Through 12mW, 3.5mW (‘L’ variant) - 1.42 – 3.6V Digital Supply Operation - 2.7 – 3.6V Analogue Supply Operation - 1.8 – 3.6V Analogue Supply Operation (‘L’ Variant)
ADC and DAC Sampling Frequency: 8kHz – 96kHz
Selectable ADC High Pass Filter
2 or 3-Wire MPU Serial Control Interface
Programmable Audio Data Interface Modes - I 2S, Left, Right Justified or DSP - 16/20/24/32 bit Word Lengths - Master or Slave Clocking Mode
Microphone Input and Electret Bias with Side Tone Mixer
Available in 28-lead SSOP or 28-lead QFN package

APPLICATIONS

Portable MP3 Players and Recorders
CD and Minidisc Recorders
PDAs / smartphones BLOCK DIAGRAM CSB SDIN SCLK DBVDD DGND CLKOUT DCVDD ADCLRC DACLRC BCLK DACDAT ADCDAT XTI/MCLK XTO MODE

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 TABLE OF CONTENTS

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 PIN CONFIGURATION - 28 PIN SSOP AVDD AGND MICBIAS VMID MICIN RLINEIN LLINEIN DCVDD MODE CSB SDIN SCLK XTO XTI/MCLK CLKOUT DGND ADCLRC ADCDAT DACDAT DACLRC BCLK DBVDD LHPOUT HPGND HPVDD RHPOUT LOUT ROUT

ORDERING INFORMATION

WM8731SEDS/V -40 to +85 oC 2.7 to 3.6V 28-lead SSOP (Pb-free) MSL3 260°C WM8731SEDS/RV -40 to +85 oC 2.7 to 3.6V 28-lead SSOP (Pb-free, tape and reel) MSL3 260°C Note: Reel quantity = 2,000

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 PIN CONFIGURATION – 28 PIN QFN TOP VIEW WM8731LSEFL -40 to +85 oC 1.8 to 3.6V 28-lead QFN (Pb-free) MSL1 260°C WM8731LSEFL/R -40 to +85 oC 1.8 to 3.6V 28-lead QFN (Pb-free, tape and reel) MSL1 260°C WM8731SEFL -40 to +85 oC 2.7 to 3.6V 28-lead QFN (Pb-free) MSL1 260°C WM8731SEFL/R -40 to +85 oC 2.7 to 3.6V 28-lead QFN (Pb-free, tape and reel) MSL1 260°C Note: Reel quantity = 3,500

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 PIN DESCRIPTION

28 PIN

1 5 DBVDD Supply Digital Buffers VDD 2 6 CLKOUT Digital Output Buffered Clock Output 3 7 BCLK Digital Input/Output Digital Audio Bit Clock, Pull Down, (see Note 1) 4 8 DACDAT Digital Input DAC Digital Audio Data Input 5 9 DACLRC Digital Input/Output DAC Sample Rate Left/Right Clock, Pull Down (see Note 1) 6 10 ADCDAT Digital Output ADC Digital Audio Data Output 7 11 ADCLRC Digital Input/Output ADC Sample Rate Left/Right Clock, Pull Down (see Note 1) 8 12 HPVDD Supply Headphone VDD 9 13 LHPOUT Analogue Output Left Channel Headphone Output 10 14 RHPOUT Analogue Output Right Channel Headphone Output 11 15 HPGND Ground Headphone GND 12 16 LOUT Analogue Output Left Channel Line Output 13 17 ROUT Analogue Output Right Channel Line Output 14 18 AVDD Supply Analogue VDD 15 19 AGND Ground Analogue GND 16 20 VMID Analogue Output Mid-rail reference decoupling point 17 21 MICBIAS Analogue Output Electret Microphone Bias 18 22 MICIN Analogue Input Microphone Input (AC coupled) 19 23 RLINEIN Analogue Input Right Channel Line Input (AC coupled) 20 24 LLINEIN Analogue Input Left Channel Line Input (AC coupled) 21 25 MODE Digital Input Control Interface Selection, Pull Up (see Note 1) 22 26 CSB Digital Input 3-Wire MPU Chip Select/ 2-Wire MPU interface address selection, active low, Pull up (see Note 1) 23 27 SDIN Digital Input/Output 3-Wire MPU Data Input / 2-Wire MPU Data Input 24 28 SCLK Digital Input 3-Wire MPU Clock Input / 2-Wire MPU Clock Input 25 1 XTI/MCLK Digital Input Crystal Input or Master Clock Input (MCLK) 26 2 XTO Digital Output Crystal Output 27 3 DCVDD Supply Digital Core VDD 28 4 DGND Ground Digital GND Note: 1. Pull Up/Down only present when Control Register Interface ACTIVE=0 to conserve power. 2. It is recommended that the QFN ground paddle is connected to analogue ground on the application PCB.

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. CONDITION MIN MAX Digital supply voltage -0.3V +3.63V Analogue supply voltage -0.3V +3.63V Voltage range digital inputs DGND -0.3V DVDD +0.3V Voltage range analogue inputs AGND -0.3V AVDD +0.3V Operating temperature range, TA -40 °C +85 °C Storage temperature after soldering -65°C +150 °C Notes: 1. Analogue and digital grounds must always be within 0.3V of each other. 2. The digital supply core voltage (DCVDD) must always be less than or equal to the analogue supply voltage (AVDD) RECOMMENDED OPERATING CONDITIONS – WM8731 PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital supply range (Core) DCVDD 1.42 3.6 V Digital supply range (Buffer) DBVDD 2.7 3.6 V Analogue supply range AVDD, HPVDD 2.7 3.6 V Ground DGND,AGND,HPGND 0 V Notes: 1. DCVDD must be lower than or equal to DBVDD. 2. USB Mode should not be used with DCVDD lower than 2V RECOMMENDED OPERATING CONDITIONS – WM8731L PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital supply range (Core) DCVDD 1.42 3.6 V Digital supply range (Buffer) DBVDD 1.8 3.6 V Analogue supply range AVDD, HPVDD 1.8 3.6 V Ground DGND,AGND,HPGND 0 V Notes: 1. If DBVDD is lower than 2.5V, DCVDD must be at least 0.225V lower than DBVDD. 2. If DBVDD is higher than or equal to 2.5V, DCVDD must be lower than or equal to DBVDD. 3. USB Mode should not be used with DCVDD lower than 2V

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 ELECTRICAL CHARACTERISTICS – WM8731 Test Conditions AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Logic Levels (CMOS Levels) Input LOW level V IL 0.3 x DBVDD V Input HIGH level V IH 0.7 x DBVDD V Output LOW V OL 0.10 x DBVDD V Output HIGH V OH 0.9 x DBVDD V Power On Reset Threshold (DCVDD) DCVDD Threshold On -> Off V th 0.9 V Hysteresis V IH 0.3 V DCVDD Threshold Off -> On V OL 0.6 V Analogue Reference Levels Reference voltage (VMID) V VMID AVDD/2 V Potential divider resistance R VMID 50k Ω Line Input to ADC Input Signal Level (0dB) V INLINE 1.0 AVDD/3.3 Vrms A-weighted, 0dB gain @ fs = 48kHz 85 90 A-weighted, 0dB gain @ fs = 96kHz Signal to Noise Ratio (Note 1,3) SNR A-weighted, 0dB gain @ fs = 48kHz, AVDD = 2.7V dB Dynamic Range (Note 3) DR A-weighted, -60dB full scale input 85 90 dB Total Harmonic Distortion THD -1dB input, 0dB gain -84 0.006 -74 0.02 dB 1kHz, 100mVpp 50 Power Supply Rejection Ratio PSRR 20Hz to 20kHz, 100mVpp dB ADC channel separation 1kHz input 90 dB Programmable Gain 1kHz input Rsource < 50Ω -34.5 0 +12 dB Programmable Gain Step Size Guaranteed Monotonic 1.5 dB Mute attenuation 0dB, 1kHz input 80 dB 0dB gain 20k 30k Input Resistance R INLINE 12dB gain 10k 15k Ω Input Capacitance C INLINE 10 pF

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 Test Conditions AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. Microphone Input to ADC @ 0dB Gain, fs = 48kHz (40kΩ Source Impedance. See Figure 12) Input Signal Level (0dB) V INMIC 1.0 AVDD/3.3 Vrms Signal to Noise Ratio (Note 1,3) SNR A-weighted, 0dB gain 85 dB Dynamic Range (Note 3) DR A-weighted, -60dB full scale input 85 dB Total Harmonic Distortion THD 0dB input, 0dB gain -60 -55 dB 1kHz 100mVpp 50 dB Power Supply Rejection Ratio PSRR 20Hz to 20kHz 100mVpp 45 dB Programmable Gain Boost MICBOOST bit set 1kHz input Rsource < 50Ω 34 dB Mic Path gain (MICBOOST gain is additional to this nominal gain) MICBOOST = 0 Rsource < 50Ω 14 dB Mute attenuation 0dB, 1kHz input 80 dB Input Resistance RINMIC 10k Ω Input Capacitance CINMIC 10 pF Microphone Bias Bias Voltage VMICBIAS 0.75*AVDD – 100mV 0.75*AVDD 0.75*AVDD + 100mV V Bias Current Source IMICBIAS 3 mA Output Noise Voltage Vn 1K to 20kHz 25 nV/ √Hz Line Output for DAC Playback Only (Load = 10kΩ. 50pF) 0dBfs Full scale output voltage At LINE outputs 1.0 x AVDD/3.3 Vrms A-weighted, @ fs = 48kHz 95 100 A-weighted @ fs = 96kHz Signal to Noise Ratio (Note 1,3) SNR A-weighted, fs = 48kHz, AVDD = 2.7V dB Dynamic Range (Note 3) DR A-weighted, -60dB full scale input 85 95 dB 1kHz, 0dBfs -88 -80 Total Harmonic Distortion THD 1kHz, -3dBfs -92 dB 1kHz 100mVpp 50 Power Supply Rejection Ratio PSRR 20Hz to 20kHz 100mVpp dB DAC channel separation 1kHz, 0dB 100 dB Analogue Line Input to Line Output (Load = 10kΩ. 50pF, No Gain on Input ) Bypass Mode 0dB Full scale output voltage 1.0 x AVDD/3.3 Vrms Signal to Noise Ratio (Note 1,3) SNR 90 95 dB 1kHz, 0dB -86 -80 Total Harmonic Distortion THD 1kHz, -3dB -92 dB 1kHz 100mVpp 50 Power Supply Rejection Ratio PSSR 20Hz to 20kHz 100mVpp dB Mute attenuation 1kHz, 0dB 80 dB

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 Test Conditions AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. Stereo Headphone Output 0dB Full scale output voltage 1.0 x AVDD/3.3 Vrms RL = 32Ω 30 Max Output Power P O RL = 16Ω 50 mW Signal to Noise Ratio (Note 1, 3) SNR A-weighted 90 97 dB 1kHz, RL = 32Ω PO = 10mW rms (-5dB) 0.056 -65 0.1 dB Total Harmonic Distortion THD 1kHz, RL = 32Ω PO = 20mW rms (-2dB) 0.56 -45 1.0 dB 1kHz 100mVpp 50 Power Supply Rejection Ratio PSRR 20Hz - 20kHz, 100mVpp 45 dB Programmable Gain 1kHz -73 0 6 dB Programmable Gain Step Size 1kHz 1 dB Mute attenuation 1kHz, 0dB 80 dB Microphone Input to Headphone Output Side Tone Mode 0dB Full scale output voltage 1.0 x AVDD/3.3 Vrms Signal to Noise Ratio (Note 1,3) SNR 90 95 dB 1kHz 100mVpp 50 Power Supply Rejection Ratio PSRR 20Hz to 20kHz 100mVpp dB Programmable Attenuation 1kHz 6 15 dB Programmable Attenuation Step Size 1kHz 3 dB Mute attenuation 1kHz, 0dB 80 dB Notes: 1. Ratio of output level with 1kHz full scale input, to the output level with the input short circuited, measured ‘A’ weighted over a 20Hz to 20kHz bandwidth using an Audio analyser. 2. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ we ighted over a 20Hz to 20kHz bandwidth. 3. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filt er will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 4. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance). TERMINOLOGY 1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). 2. Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). 3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. 4. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other.

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 POWER CONSUMPTION – WM8731 CURRENT CONSUMPTION TYPICAL MODE (3.3V) HP VDD (3.3V) DC VDD (1.5V) DB VDD (3.3V) UNIT Record and Playback Oscillator enabled 0 0 0 0 0 0 0 0 13.1 1.7 3.0 1.5 mA External MCLK 0 0 1 0 0 0 0 0 13.1 1.7 3.2 0.8 mA Oscillator and CLKOUT disabled, No microphone 0 1 1 0 0 0 1 0 12.2 1.7 3.2 0.07 mA Playback Only Oscillator enabled 0 0 0 0 0 1 1 1 3.4 1.7 2.1 1.5 mA External MCLK 0 1 1 0 0 1 1 1 3.3 1.7 2.3 0.07 mA Record Only Line Record, oscillator enabled 0 0 0 1 1 0 1 0 9.2 - 2.6 1.3 mA Line Record, using external MCLK 0 0 1 1 1 0 1 0 9.2 - 2.6 0.7 mA Mic Record, oscillator enabled 0 0 0 1 1 0 0 1 8.6 - 2.7 1.5 mA Mic Record, using external MCLK 0 0 1 1 1 0 0 1 8.6 - 2.6 0.7 mA Side Tone (Microphone Input to Headphone Output) External clock still running 0 0 1 0 1 1 0 1 1.6 1.7 0.08 0.7 mA Clock stopped 0 0 1 0 1 1 0 1 1.5 1.7 - - mA Analogue Bypass (Line-in to Line-out) External clock still running 0 0 1 0 1 1 1 0 2.1 1.7 0.08 0.7 mA Clock stopped 0 0 1 0 1 1 1 0 2.2 1.7 - - mA Standby External clock still running 0 1 1 1 1 1 1 1 16 0.3 77 65 μA Clock stopped 0 1 1 1 1 1 1 1 16 0.3 0.3 0.2 μA Power Down External clock still running 1 1 1 1 1 1 1 1 0.2 0.3 77 65 μA Clock stopped 1 1 1 1 1 1 1 1 0.3 0.3 0.3 0.3 μA Table 1 Powerdown Mode Current Consumption Examples Notes: 1. T A = +25oC. fs = 48kHz, XTI/MCLK = 256fs (12.288MHz). 2. The data presented here was measured with the audio interface in master mode whenever the internal clock oscillator was used, and in slave mode whenever an external clock was used (i.e. MS = 1 when OSCPD = 0 and vice versa). However, it is also possible to use the WM8731 with MS = OSCPD = 0 or MS = OSCPD = 1. 3. All figures are quiescent, with no signal. 4. The power dissipation in the headphone itself not included in the above table.

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 ELECTRICAL CHARACTERISTICS – WM8731L Test Conditions AVDD, HPVDD, DBVDD = 1.8V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Logic Levels (CMOS Levels) Input LOW level V IL 0.3 x DBVDD V Input HIGH level V IH 0.7 x DBVDD V Output LOW V OL 0.10 x DBVDD V Output HIGH V OH 0.9 x DBVDD V Power On Reset Threshold (DCVDD) DCVDD Threshold On -> Off V th 0.9 V Hysteresis V IH 0.3 V DCVDD Threshold Off -> On V OL 0.6 V Analogue Reference Levels Reference voltage (VMID) V VMID AVDD/2 V Potential divider resistance R VMID 50k Ω Line Input to ADC Input Signal Level (0dB) V INLINE 1.0 AVDD/3.3 Vrms A-weighted, 0dB gain @ fs = 48kHz 75 85 Signal to Noise Ratio (Note 1,3) SNR A-weighted, 0dB gain @ fs = 96kHz dB Dynamic Range (Note 3) DR A-weighted, -60dB full scale input 80 88 dB Total Harmonic Distortion THD -1dB input, 0dB gain -76 -60 dB 1kHz, 100mVpp 50 Power Supply Rejection Ratio PSRR 20Hz to 20kHz, 100mVpp dB ADC channel separation 1kHz input 90 dB Programmable Gain 1kHz input Rsource < 50Ω -34.5 0 +12 dB Programmable Gain Step Size Guaranteed Monotonic 1.5 dB Mute attenuation 0dB, 1kHz input 80 dB 0dB gain 20k 30k Input Resistance R INLINE 12dB gain 10k 15k Ω Input Capacitance C INLINE 10 pF

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 Test Conditions AVDD, HPVDD, DBVDD = 1.8V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. Microphone Input to ADC @ 0dB Gain, fs = 48kHz (40kΩ Source Impedance. See Figure 12) Input Signal Level (0dB) V INMIC 1.0 AVDD/3.3 Vrms Signal to Noise Ratio (Note 1,3) SNR A-weighted, 0dB gain 80 dB Dynamic Range (Note 3) DR A-weighted, -60dB full scale input 70 dB Total Harmonic Distortion THD 0dB input, 0dB gain -55 dB 1kHz 100mVpp 50 dB Power Supply Rejection Ratio PSRR 20Hz to 20kHz 100mVpp 45 dB Programmable Gain Boost MICBOOST bit set 1kHz input Rsource < 50Ω 34 dB Mic Path gain (MICBOOST gain is additional to this nominal gain) MICBOOST = 0 Rsource < 50Ω 14 dB Mute attenuation 0dB, 1kHz input 80 dB Input Resistance RINMIC 10k Ω Input Capacitance CINMIC 10 pF Microphone Bias Bias Voltage VMICBIAS 0.75*AVDD – 100mV 0.75*AVDD 0.75*AVDD + 100mV V Bias Current Source IMICBIAS 3 mA Output Noise Voltage Vn 1K to 20kHz 25 nV/ √Hz Line Output for DAC Playback Only (Load = 10k Ω. 50pF) 0dBfs Full scale output voltage At LINE outputs 1.0 x AVDD/3.3 Vrms A-weighted, @ fs = 48kHz 85 95 Signal to Noise Ratio (Note 1,3) SNR A-weighted @ fs = 96kHz dB Dynamic Range (Note 3) DR A-weighted, -60dB full scale input 85 90 dB 1kHz, 0dBfs -80 -75 Total Harmonic Distortion THD 1kHz, -3dBfs -90 dB 1kHz 100mVpp 50 Power Supply Rejection Ratio PSRR 20Hz to 20kHz 100mVpp dB DAC channel separation 1kHz, 0dB 100 dB Analogue Line Input to Line Output (Load = 10k Ω. 50pF, No Gain on Input ) Bypass Mode 0dB Full scale output voltage 1.0 x AVDD/3.3 Vrms Signal to Noise Ratio (Note 1,3) SNR 85 90 dB 1kHz, 0dB -83 -76 Total Harmonic Distortion THD 1kHz, -3dB -92 dB 1kHz 100mVpp 50 Power Supply Rejection Ratio PSSR 20Hz to 20kHz 100mVpp dB Mute attenuation 1kHz, 0dB 80 dB

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 Test Conditions AVDD, HPVDD, DBVDD = 1.8V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. Stereo Headphone Output 0dB Full scale output voltage 1.0 x AVDD/3.3 Vrms RL = 32 Ω 9 Max Output Power P O RL = 16 Ω 18 mW Signal to Noise Ratio (Note 1,3) SNR A-weighted 86 95 dB 1kHz, -5dB FS signal RL = 32Ω 0.08 -62 0.1 -60 Total Harmonic Distortion THD 1kHz, -2dB FS signal RL = 32Ω -40 dB 1kHz 100mVpp 50 Power Supply Rejection Ratio PSRR 20Hz - 20kHz, 100mVpp 45 dB Programmable Gain 1kHz -73 0 6 dB Programmable Gain Step Size 1kHz 1 dB Mute attenuation 1kHz, 0dB 80 dB Microphone Input to Headphone Output Side Tone Mode 0dB Full scale output voltage 1.0 x AVDD/3.3 Vrms Signal to Noise Ratio (Note 1,3) SNR 85 90 dB 1kHz 100mVpp 50 Power Supply Rejection Ratio PSRR 20Hz to 20kHz 100mVpp dB Programmable Attenuation 1kHz 6 15 dB Programmable Attenuation Step Size 1kHz 3 dB Mute attenuation 1kHz, 0dB 80 dB Notes: 1. Ratio of output level with 1kHz full scale input, to the output level with the input short circuited, measured ‘A’ weighted over a 20Hz to 20kHz bandwidth using an Audio analyser. 2. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ we ighted over a 20Hz to 20kHz bandwidth. 3. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filt er will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 4. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance). TERMINOLOGY 1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). 2. Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). 3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. 4. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other.

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 POWER CONSUMPTION – WM8731L CURRENT CONSUMPTION TYPICAL MODE (1.8V) HP VDD (1.8V) DC VDD (1.5V) DB VDD (1.8V) UNIT Record and Playback All active, oscillator enabled 0 0 0 0 0 0 0 0 6 0.6 2.7 0.9 mA Playback Only Oscillator enabled 0 0 0 0 0 1 1 1 1.7 0.6 1.8 0.9 mA Record Only Line Record, oscillator enabled 0 0 0 1 1 0 1 0 3.9 - 2.4 0.9 mA Mic Record, oscillator enabled 0 0 0 1 1 0 0 1 3.6 - 2.4 0.9 mA Side Tone (Microphone Input to Headphone Output) Clock stopped 0 0 1 0 1 1 0 1 0.8 0.6 - - mA Analogue Bypass (Line-in to Line-out) Clock stopped 0 0 1 0 1 1 1 0 1.1 0.6 - - mA Standby Clock stopped 0 1 1 1 1 1 1 1 8 - - - μA Power Down Clock stopped 1 1 1 1 1 1 1 1 0.2 0.2 0.3 0.2 μA Table 2 Powerdown Mode Current Consumption Examples Notes: 1. AVDD, HPVDD, DBVDD = 1.8V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T A = +25oC. Slave Mode, fs = 48kHz, XTI/MCLK = 256fs (12.288MHz). 2. All figures are quiescent, with no signal. 3. All figures are measured with the audio interface in master mode (MS = 1). 4. The power dissipation in the headphone itself is not included in the above table.

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 MPU INTERFACE TIMING CSB SCLK SDIN tCSL tDHOtDSU tCSH tSCY tSCH tSCL tSCS LSB tCSS Figure 7 Program Register Input Timing - 3-Wire MPU Serial Control Mode Test Conditions AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CSB rising edge tSCS 60 ns SCLK pulse cycle time tSCY 80 ns SCLK pulse width low tSCL 20 ns SCLK pulse width high tSCH 20 ns SDIN to SCLK set-up time tDSU 20 ns SCLK to SDIN hold time tDHO 20 ns CSB pulse width low tCSL 20 ns CSB pulse width high tCSH 20 ns CSB rising to SCLK rising tCSS 20 ns

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 SDIN SCLK t6 t2 t10 Figure 8 Program Register Input Timing – 2-Wire MPU Serial Control Mode Test Conditions AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Program Register Input Information SCLK Frequency 0 526 kHz SCLK Low Pulsewidth t1 1.3 us SCLK High Pulsewidth t2 600 ns Hold Time (Start Condition) t3 600 ns Setup Time (Start Condition) t 4 600 ns Data Setup Time t5 100 ns SDIN, SCLK Rise Time t6 300 ns SDIN, SCLK Fall Time t7 300 ns Setup Time (Stop Condition) t8 600 ns Data Hold Time t10 900 ns

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 DEVICE DESCRIPTION INTRODUCTION The WM8731/L is a low power audio CODEC designed specifically for portable audio products. It’s features, performance and low power consumption make it ideal for portable MP3 players and portable mini-disc players. The CODEC includes line and microphone inputs to the on-board ADC, line and headphone outputs from the on-board DAC, a crystal oscillator, configurable digital audio interface and a choice of 2 or 3 wire MPU control interface. It is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and DSPs. The CODEC includes three low noise inputs - mono microphone and stereo line. Line inputs have +12dB to -34dB logarithmic volume level adjustments and mute. The Microphone input has -6dB to 34dB volume level adjustment. An electret microphone bias level is also available. All the required input filtering is contained within the device with no external components required. The on-board stereo analogue to digital converter (ADC) is of a high quality using a multi-bit high- order oversampling architecture delivering optimum performance with low power consumption. The output from the ADC is available on the digital audio interface. The ADC includes an optional digital high pass filter to remove unwanted dc components from the audio signal. The on-board digital to analogue converter (DAC) accepts digital audio from the digital audio interface. Digital filter de-emphasis at 32kHz, 44.1kHz and 48kHz can be applied to the digital data under software control. The DAC employs a high quality multi-bit high-order oversampling architecture to again deliver optimum performance with low power consumption. The DAC outputs, Microphone (SIDETONE) and Line Inputs ( BYPASS) are available both at line level and through a headphone amplifier capable of efficiently driving low impedance headphones. The headphone output volume is adjustable in the analogue domain over a range of +6dB to –73dB and can be muted. The design of the WM8731/L has given much attention to power consumption without compromising performance. It includes the ability to power off selective parts of the circuitry under software control, thus conserving power. Nine separate power save modes be configured under software control including a standby and power off mode. Special techniques allow the audio to be muted and the device safely placed into standby, sections of the device powered off and volume levels adjusted without any audible clicks, pops or zipper noises. Therefore standby and power off modes maybe used dynamically under software control, whenever recording or playing is not required. The device caters for a number of different sampling rates including industry standard 8kHz, 32kHz, 44.1kHz, 48kHz, 88.2kHz and 96kHz. Additionally, the device has an ADC and DAC that can operate at different sample rates. There are two unique schemes featured within the programmable sample rates of the WM8731/L: Normal industry standard 256/384fs sampling mode may be used, with the added ability to mix different sampling rates. Also a special USB mode is included, whereby all audio sampling rates can be generated from a 12.00MHZ USB clock. Thus, for example, the ADC can record to the DSP at 44.1kHz and be played back from the CODEC at 8kHz with no external digital signal processing required. The digital filters used at for both record and playback are optimised for each sampling rate used. The digitised output is available in a number of audio data formats I 2S, DSP Mode (a burst mode in which frame sync plus 2 data packed words are transmitted), MSB-First, left justified and MSB-First, right justified. The digital audio interface can operate in both master or slave modes. The software control uses either 2 or 3-wire MPU interface. A crystal oscillator is included on board the device. The device can generate the system master clock or alternatively it can accept an external master clock from the audio system.

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 The gain between the line inputs and the ADC is logarithmically adjustable from +12dB to –34.5dB in voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with AVDD. The gain is independently adjustable on both Right and Left Line Inputs. However, by setting the INBOTH bit whilst programming the volume control, both channels are simultaneously updated with the same value. Use of INBOTH reduces the required number of software writes required. The line inputs to the ADC can be muted in the analogue domain under software control. The software control registers are shown Table 3. Note that the Line Input Mute only mutes the input to the ADC, this will still allow the Line Input signal to pass to the line output in Bypass Mode. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 4:0 LINVOL[4:0] 10111 ( 0dB ) Left Channel Line Input Volume Control 11111 = +12dB . . 1.5dB steps down to 00000 = -34.5dB

7 LINMUTE 1 Left Channel Line Input Mute to ADC

1 = Enable Mute 0 = Disable Mute 0000000 Left Line In

8 LRINBOTH 0 Left to Right Channel Line Input

Volume and Mute Data Load Control 1 = Enable Simultaneous Load of LINVOL[4:0] and LINMUTE to RINVOL[4:0] and RINMUTE 0 = Disable Simultaneous Load 4:0 RINVOL[4:0] 10111 ( 0dB ) Right Channel Line Input Volume Control 11111 = +12dB . .1.5dB steps down to 00000 = -34.5dB

7 RINMUTE 1 Right Channel Line Input Mute to

1 = Enable Mute 0 = Disable Mute 0000001 Right Line In

8 RLINBOTH 0 Right to Left Channel Line Input

Volume and Mute Data Load Control 1 = Enable Simultaneous Load of RINVOL[4:0] and RINMUTE to LINVOL[4:0] and LINMUTE 0 = Disable Simultaneous Load Table 3 Line Input Software Control The line inputs are biased internally through the operational amplifier to VMID. Whenever the line inputs are muted or the device placed into standby mode, the line inputs are kept biased to VMID using special anti-thump circuitry. This reduces any audible clicks that may otherwise be heard when re-activating the inputs. The external components required to complete the line input application is shown in the Figure 11.

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 Or alternatively to calculate the value of Rmic to achieve a given gain, G1. Rmic = (50k/G1) – 10k The internal 50k and 10k resistors have a tolerance of 15%. For Rmicext = 90k G = 0.5 (-6dB) and for Rmicext = 0 G = x10 (14dB). The 2 nd stage comprises a 0dB gain stage that can be software configured to provide a fixed 20dB of gain for low sensitivity microphones. The microphone input can therefore be configured with a variable gain of between -6dB and 14dB on the 1st stage, and an additional fixed 0dB or 20dB on the 2 nd stage. This allows for all gains to the input signal in the range –6dB to 34dB to be catered for. The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full scale input tra cks directly with AVDD. Stage 1 and Stage 2 gains should be configured so that the ADC receives a maximum signal equal to its full scale for maximising the signal to noise. The software control for the MICIN is shown in Table 4. Note that the Microphone Mute only mutes the input to the ADC, this will still allow the Microphone Input signal to pass to the line output in Sidetone Mode. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0 MICBOOST 0 Microphone Input Level Boost

1 = Enable Boost 0 = Disable Boost 0000100 Analogue Audio Path Control

1 MUTEMIC 1 Line Input Mute to ADC

1 = Enable Mute 0 = Disable Mute Table 4 Microphone Input Software Control The microphone input is biased internally through the operational amplifier to VMID. Whenever the line inputs are muted the MICIN input is kept biased to VMID using special anti-thump circuitry. This reduces any audible clicks that may otherwise be heard when re-activating the input. The application drawing for the microphone is shown in Figure 13. AGND AGND R2 C1 MICIN MICBIAS AGND FROM MICROPHONE Rmic Figure 13 Microphone Input and Bias Application Drawing Recommended component values are C1 = 220pF (npo ceramic), C2 = 1 μF, R1 = 680 Ω, R2 = 47k. Rmic values depends on gain setting (see above).

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with AVDD. The device employs a pair of ADCs. The input can be selected from either the Line Inputs or the Microphone input under software control. The two channels cannot be selected independently. The control is shown in Table 5. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0000100 Analogue Audio Path Control

2 INSEL 0 Microphone/Line Input Select to ADC

1 = Microphone Input Select to ADC 0 = Line Input Select to ADC Table 5 ADC Software Control The digital data from the ADC is fed for signal processing to the ADC Filters. ADC FILTERS The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. Figure 16 illustrates the digital filter path. FROM ADC DIGITAL HPF DIGITAL DECIMATION FILTER TO DIGITAL AUDIO INTERFACE DIGITAL DECIMATOR HPFEN Figure 16 ADC Digital Filter The ADC digital filters contain a digital high pass filter, selectable via software control. The high-pass filter response detailed in Digital Filter Characteristics. When the high-pass filter is enabled the dc offset is continuously calculated and subtracted from the input signal. By setting HPOR the last calculated dc offset value is stored when the high-pass filter is disabled and will continue to be subtracted from the input signal. If the dc offset changes, the stored and subtracted value will not change unless the high-pass filter is enabled. The software control is shown in Table 6. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0 ADCHPD 0 ADC High Pass Filter Enable

(Digital) 1 = Disable High Pass Filter 0 = Enable High Pass Filter 0000101 Digital Audio Path Control

4 HPOR 0 Store dc offset when High Pass

1 = store offset 0 = clear offset Table 6 ADC Software Control

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 There are several types of ADC filters, frequency and phase responses of these are shown in Digital Filter Characteristics. The filter types are automatically configured depending on the sample rate chosen. Refer to the sample rate section for more details. DAC FILTERS The DAC filters perform true 24 bit signal processing to convert the incoming digital audio data from the digital audio interface at the specified sample rate to multi-bit oversampled data for processing by the analogue DAC. Figure 17 illustrates the DAC digital filter path. FROM DIGITAL AUDIO INTERFACE MUTE DIGITAL INTERPOLATION FILTER TO LINE OUTPUTS DIGITAL DE_EMPHASIS DEEMP DACMU Figure 17 DAC Filter Schematic The DAC digital filter can apply digital de-emphasis under software control, as shown in Table 7.The DAC can also perform a soft mute where the audio data is digitally brought to a mute level. This removes any abrupt step changes in the audio that might otherwise result in audible clicks in the audio outputs. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 2:1 DEEMP[1:0] 00 De-emphasis Control (Digital) 11 = 48kHz 10 = 44.1kHz 01 = 32kHz 00 = Disable 0000101 Digital Audio Path Control

3 DACMU 1 DAC Soft Mute Control

(Digital) 1 = Enable soft mute 0 = Disable soft mute Table 7 DAC Software Control Notes: 1. Not valid when SR[3:0] = 1111 or 0111. 2. To ensure correct DACMU operation at fs = 88.2kHz, set SR[3:0] = 1000. 3. To ensure correct DACMU operation at fs = 96kHz, set SR[3:0] = 0000. DAC The WM8731/L employs a multi-bit sigma delta oversampling digital to analogue converter. The scheme for the converter is illustrated in Figure 18.

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 The software control for the line outputs is shown in Table 8. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

3 BYPASS 1 Bypass Switch

1 = Enable Bypass 0 = Disable Bypass

4 DACSEL 0 DAC Select

1 = Select DAC 0 = Don’t select DAC 0000100 Analogue Audio Path Control

5 SIDETONE 0 Side Tone Switch

1 = Enable SideTone 0 = Disable Side Tone Table 8 Output Software Control The recommended external components are shown in Figure 20. AGND AGND LINEOUT Figure 20 Line Outputs Application Drawing Recommended values are C1 = 10μF, R1 = 47k, R2 = 100 Ω. C1 forms a DC blocking capacitor to the line outputs. R1 prevents the output voltage from drifting so protecting equipment connected to the line output. R2 forms a de-coupling resistor preventing abnormal loads from disturbing the device. Note that poor choice of dielectric material for C1 can have dramatic effects on the measured signal distortion at the output HEADPHONE AMPLIFIER The WM8731/L has a stereo headphone output available on LHPOUT and RHPOUT. The output is designed specifically for driving 16 or 32 Ω headphones with maximum efficiency and low power consumption. The headphone output includes a high quality volume level adjustment and mute function.

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 The scheme of the circuit is shown in Figure 21. VMID HPOUT FROM DAC VIA LINEOUT Figure 21 Headphone Amplifier Schematic LHPOUT and RHPOUT volumes can be independently adjusted under software control using the LHPVOL[6:0] and RHPVOL[6:0] bits respectively of the headphone output control registers. The adjustment is logarithmic with an 80dB range in 1dB steps from +6dB to –73dB. The headphone outputs can be separately muted by writing codes less than 0110000 to LHPVOL[6:0] or RHPVO[6:0]L bits. Whenever the headphone outputs are muted or the device placed into standby mode, the DC voltage is maintained at the line outputs to prevent any audible clicks from being present. A zero cross detect circuit is provided at the input to the headphones under the control of the LZCEN and RZCEN bits of the headphone output control register. Using these controls the volume control values are only updated when the input signal to the gain stage is close to the analogue ground level. This minimises and audible clicks and zipper noise as the gain values are changed or the device muted. Note that this circuit has no time out so if only DC levels are being applied to the gain stage input of more than approximately 20mV, then the gain will not be updated. This zero cross function is enabled when the LZCEN and RZCEN bit is set high during a volume register write. If there is concern that a DC level may have blocked a volume change (one made with LZCEN or RZCEN set high) then a subsequent volume write of the same value, but with the LZCEN or RZCEN bit set low will force a volume update, regardless of the DC level. LHPOUT and RHPOUT volume and zero-cross setting can be changed independently. Alternatively, the user can lock the two channels together, allowing both to be updated simultaneously, halving the number of serial writes required, provided that the same gain is needed for both channels. This is achieved through writing to the HPBOTH bit of the control register. Setting LRHPBOTH whilst writing to LHPVOL and LZCEN will simultaneously update the Right Headphone controls similarly. The corresponding effect on updating RLHPBOTH is also achieved.

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 The software control is given in Table 9. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 6:0 LHPVOL[6:0] 1111001 ( 0dB ) Left Channel Headphone Output Volume Control 1111111 = +6dB . . 1dB steps down to 0110000 = -73dB 0000000 to 0101111 = MUTE

7 LZCEN 0 Left Channel Zero Cross detect

1 = Enable 0 = Disable 0000010 Left Headphone Out

8 LRHPBOTH 0 Left to Right Channel Headphone

Volume, Mute and Zero Cross Data Load Control 1 = Enable Simultaneous Load of LHPVOL[6:0] and LZCEN to RHPVOL[6:0] and RZCEN 0 = Disable Simultaneous Load 6:0 RHPVOL[6:0] 1111001 ( 0dB ) Right Channel Headphone Output Volume Control 1111111 = +6dB . . 1dB steps down to 0110000 = -73dB 0000000 to 0101111 = MUTE

7 RZCEN 0 Right Channel Zero Cross Detect

1 = Enable 0 = Disable 0000011 Right Headphone Out

8 RLHPBOTH 0 Right to Left Channel Headphone

Volume, Mute and Zero Cross Data Load Control 1 = Enable Simultaneous Load of RHPVOL[6:0] and RZCEN to LHPVOL[6:0] and LZCEN 0 = Disable Simultaneous Load Table 9 Headphone Output Software Control

Table 10. In true bypass mode, the output from the DAC (DACSEL) and (SIDETONE) should be de- 1Vrms line BYPASS signal, the resulting LINEOP signal will be clipped.

3 BYPASS 1 Bypass Switch (Anal ogue)

headphone outputs. The scheme for this is shown in Figure 24.

5 SIDETONE 0 Side Tone Switch (Analogue)

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 The side tone mode and attenuation is selected under software control using the SIDETONE bit as shown in Table 11. In true side tone the output from the DAC (DACSEL) and line inputs (BY PASS) should be deselected from the line output block. However, this can also be used to sum the DAC output, line inputs and microphone inputs together. The microphone boost gain control and headphone output volume control and mutes are still operational in side tone mode. The maximum signal at any point in the side tone path must be no greater than 1.0V rms at VDD = 3.3V, to avoid distortion. This amplitude tracks linearly with AVDD. DEVICE OPERATION DEVICE RESETTING The WM8731/L contains a power on reset circuit that resets the internal state of the device to a known condition. The power on reset is applied as DCVDD powers on and released only after the voltage level of DCVDD crosses a minimum turn off threshold. If DCVDD later falls below a minimum turn on threshold voltage then the power on reset is re-applied. The threshold voltages and associated hysteresis are shown in the Electrical Characteristics table. The user also has the ability to reset the device to a known state under software control as shown in the table below. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001111 Reset Register 8:0 RESET not reset Reset Register Writing 00000000 to register resets device Table 12 Software Control of Reset When using the software reset. In 3-wire mode the reset is applied on the rising edge of CSB and released on the next rising edge of SCLK. In 2-wire mode the reset is applied for the duration of the ACK signal (approximately 1 SCLK period, refer to Figure 34). CLOCKING SCHEMES In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s Master Clock. To allow WM8731/L to be used in a centrally clocked system, the WM8731/L is capable of either generating this system clock itself or receiving it from an external source as will be discussed. For applications where it is desirable that the WM8731/L is the system clock source, then clock generation is achieved through the use of a suitable crystal connected between the XTI/MCLK input and XTO output pins (see CRYSTAL OSCILLATOR section). For applications where a component other than the WM8731/L will generate the reference clock, the external system can be applied directly through the XTI/MCLK input pin with no software configuration necessary. Note that in this situation, the oscillator circuit of the WM8731/L can be safely powered down to conserve power (see POWER DOWN section). CORE CLOCK The WM8731/L DSP core can be clocked either by MCLK or MCLK divided by 2. This is controlled by software as shown in Table 13 below. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001000 Sampling Control

6 CLKIDIV2 0 Core Clock divider select

1 = Core Clock is MCLK divided by 2 0 = Core Clock is MCLK Table 13 Software Control of Core Clock Having a programmable MCLK divider allows the device to be used in applications where higher frequency master Clocks are available. For example the device can support 512fs master clocks whilst fundamentally operating in a 256fs mode.

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 CRYSTAL OSCILLATOR The WM8731/L includes a crystal oscillator circuit that allows the audio system’s reference clock to be generated on the device. This is available to the rest of the audio system in buffered form on CLKOUT. The crystal oscillator is a low radiation type, designed for low EMI. A typical application circuit is shown in Figure 25. XTI/MCLK XTO DGND DGND Cp Cp Figure 25 Crystal Oscillator Application Circuit The WM8731/L crystal oscillator provides an extremely low jitter clock source. Low jitter clocks are a requirement for high quality audio ADC and DACs, r egardless of the converter architecture. The WM8731/L architecture is less susceptible than most converter techniques but still requires clocks with less than approximately 1ns of jitter to maintain performance. In applications where there is more than one source for the master clock, it is recommended that the clock is generated by the WM8731/L to minimise such problems. CLOCKOUT The Core Clock is internally buffered and made available externally to the audio system on the CLKOUT output pin. CLKOUT provides a replication of the Core Clock, but buffered as suitable for driving external loads. There is no phase inversion between XTI/MCLK, the Core Clock and CLOCKOUT but there will inevitably be some delay. The delay will be dependent on the load that CLOCKOUT drives. Refer to Electrical Characteristics. CLKOUT can also be divided by 2 under software control, refer to Table 14. Note that if CLKOUT is not required then the CLKOUT buffer on the WM8731/L can be safely powered down to conserve power (see POWER DOWN section). If the system architect has the choice between using F CLKOUT = FMCLK or FCLKOUT = FMCLK/2 in the interface, the latter is recommended to conserve power. When the divide by two is selected CLKOUT changes on the rising edge of MCLK. Please refer to Electrical Characteristics for timing information. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001000 Sampling Control

7 CLKODIV2 0 CLKOUT divider select

1 = CLOCKOUT is Core Clock divided by 2 0 = CLOCKOUT is Core Clock Table 14 Programming CLKOUT CLKOUT is disabled and set low whenever the device is in reset.

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 DIGITAL AUDIO INTERFACES WM8731/L may be operated in either one of the 4 offered audio interface modes. These are:

Right justified
Left justified
I 2S
DSP mode All four of these modes are MSB first and operate with data 16 to 32 bits. Note that 32 bit data is not supported in right justified mode. The digital audio interface takes the data from the internal ADC digital filter and places it on the ADCDAT output. ADCDAT is the formatted digital audio data stream output from the ADC digital filters with left and right channels multiplexed together. ADCLRC is an alignment clock that controls whether Left or Right channel data is present on the ADCDAT lines. ADCDAT and ADCLRC are synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low transition. BCLK maybe an input or an output dependent on whether the device is in master or slave mode. Refer to the MASTER/SLAVE OPERATION section The digital audio interface also receives the digital audio data for the internal DAC digital filters on the DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters with left and right channels multiplexed together. DACLRC is an alignment clock that controls whether Left or Right channel data is present on DACDAT. DACDAT and DACLRC are synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low transition. DACDAT is always an input. BCLK and DACLRC are either outputs or inputs depending whether the device is in master or slave mode. Refer to the MASTER/SLAVE OPERATION section There are four digital audio interface formats accommodated by the WM8731/L. These are shown in the figures below. Refer to the Electrical Characteristic section for timing information. Left Justified mode is where the MSB is available on the first rising edge of BCLK following a ADCLR or DACLRC transition. LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC BCLK DACDAT/ ADCDAT 1/fs n321 n-2 n-1 LSBMSB n321 n-2 n-1 LSBMSB Figure 26 Left Justified Mode I2S mode is where the MSB is available on the 2nd rising edge of BCLK following a DACLRC or ADCLRC transition.

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC BCLK DACDAT/ ADCDAT 1/fs n321 n-2 n-1 LSBMSB n321 n-2 n-1 LSBMSB

1 BCLK1 BCLK

Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a DACLRC or ADCLRC transition, yet MSB is still transmitted first. LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC BCLK DACDAT/ ADCDAT 1/fs n321 n-2 n-1 LSBMSB n321 n-2 n-1 LSBMSB Figure 28 Right Justified Mode In DSP/PCM mode, the left channel MSB is available on either the 1 st (mode B) or 2 nd (mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. Figure 29 DSP/PCM Mode Audio Interface (mode A, LRP=1)

26, Figure 27, Figure 28, Figure 29 and Figure 30. number of BCLK cycles to suit the chosen word length. ratios need more careful consideration. In Slave mode, DACLRC and ADCLRC inputs are not required to have a 50:50 mark-space ratio. period. Therefore DACLRC and ADCLRC outputs will have a mark space ratio of 187:188. The ADC and DAC digital audio interface modes are software configurable as indicated in Table 14. interfaces and is therefore not recommended. bits. If the ADC is programmed to output 16 or 20 bit data then it strips the LSBs from the 24 bit data. programmed to receive 32 bit data, then it strips the LSBs. Table 15. Stereo samples are normally generated as a Left/Right sampled pair. LRSWAP reverses correct channel phase difference. controlled vias the software shown in Table 15. This is especially appropriate for DSP mode.

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 ADCDAT lines are always outputs. They power up and return from standby low. DACDAT is always an input. It is expected to be set low by the audio interface controller when the WM8731/L is powered off or in standby. ADCLRC, DACLRC and BCLK can be either outputs or inputs depending on whether the device is configured as a master or slave. If the device is a master then the DACLRC and BCLK signals are outputs that default low. If the device is a slave then the DACLRC and BCLK are inputs. It is expected that these are set low by the audio interface controller when the WM8731/L is powered off or in standby. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 1:0 FORMAT[1:0] 10 Audio Data Format Select 11 = DSP Mode, frame sync + 2 data packed words 10 = I2S Format, MSB-First left-1 justified 01 = MSB-First, left justified 00 = MSB-First, right justified 3:2 IWL[1:0] 10 Input Audio Data Bit Length Select 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits

4 LRP 0 DACLRC phase control (in left, right

or I2S modes) 1 = Right Channel DAC data when DACLRC high 0 = Right Channel DAC data when DACLRC low (opposite phasing in I2S mode) or DSP mode A/B select (in DSP mode only) 1 = MSB is available on 2nd BCLK rising edge after DACLRC rising edge 0 = MSB is available on 1st BCLK rising edge after DACLRC rising edge

5 LRSWAP 0 DAC Left Right Clock Swap

1 = Right Channel DAC Data Left 0 = Right Channel DAC Data Right

6 MS 0 Master Slave Mode Control

1 = Enable Master Mode 0 = Enable Slave Mode 0000111 Digital Audio Interface Format

7 BCLKINV 0 Bit Clock Invert

1 = Invert BCLK 0 = Don’t invert BCLK Table 15 Digital Audio Interface Control Note: If right justified 32 bit mode is selected then the WM8731/L defaults to 24 bits.

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 MASTER AND SLAVE MODE OPERATION The WM8731/L can be configured as either a master or slave mode device. As a master mode device the WM8731/L controls sequencing of the data and clocks on the digital audio interface. As a slave device the WM8731/L responds with data to the clocks it receives over the digital audio interface. The mode is set with the MS bit of the control register as shown in Table 16. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0000111 Digital Audio Interface Format 1 = Enable Master Mode 0 = Enable Slave Mode Table 16 Programming Master/Slave Modes As a master mode device the WM8731/L controls the sequencing of data transfer (ADCDAT, DACDAT) and output of clocks (BCLK, ADCLRC, DACLRC) over the digital audio interface. It uses the timing generated from either its on-board crystal or the MCLK input as the reference for the clock and data transitions. This is illustrated in Figure 31. ADCDAT is always an output from and DACDAT is always an input to the WM8731/L independent of master or slave mode. BCLK ADCDAT ADCLRC DACDAT DACLRCWM8731 CODEC DSP ENCODER/ DECODER Note: ADC and DAC can run at different rates Figure 31 Master Mode As a slave device the WM8731/L sequences the data transfer (ADCDAT, DACDAT) over the digital audio interface in response to the external applied clocks (BCLK, ADCLRC, DACLRC). This is illustrated in Figure 32. BCLK ADCDAT ADCLRC DACDAT DACLRCWM8731 CODEC DSP ENCODER/ DECODER Note: The ADC and DAC can run at different rates Figure 32 Slave Mode Note that the WM8731/L relies on controlled phase relationships between audio interface BCLK, DACLRC and the master MCLK or CLKOUT. To avoid any timing hazards, refer to the timing section for detailed information.

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 AUDIO DATA SAMPLING RATES The WM8731/L provides for two modes of operation (normal and USB) to generate the required DAC and ADC sampling rates. Normal and USB modes are programmed under software control according to the table below. In Normal mode, the user controls the sample rate by using an appropriate MCLK or crystal frequency and the sample rate control register setting. The WM8731/L can support sample rates from 8ks/s up to 96ks/s. In USB mode, the user must use a fixed MLCK or crystal frequency of 12MHz to generate sample rates from 8ks/s to 96ks/s. It is called USB mode since the common USB (Universal Serial Bus) clock is at 12MHz and the WM8731/L can be directly used within such systems. WM8731/L can generate all the normal audio sample rates from this one Master Clock frequency, removing the need for different master clocks or PLL circuits. Uniquely, the WM8731/L offers the user the ability to sample the ADC and DAC at different rates under software control in both Normal and USB modes. This reduces the burden on any controlling DSP. However, the signal processing in the ADC and DAC over-sampling filters is tightly coupled together in order to minimise power consumption. To this end, only the combinations of sample rates listed in the following sections are supported. Note that these rates supported are anticipated to be the likely combinations used in typical audio systems. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION

0 USB/

0 Mode Select

1 = USB mode (250/272fs) 0 = Normal mode (256/384fs)

1 BOSR 0 Base Over-Sampling Rate

0 = 250fs 1 = 272fs Normal Mode 96/88.2kHz 0 = 256fs 0 = 128fs 1 = 384fs 1 = 192fs 0001000 Sampling Control 5:2 SR[3:0] 0000 ADC and DAC sample rate control; See USB Mode and Normal Mode Sample Rate sections for operation Table 17 Sample Rate Control NORMAL MODE SAMPLE RATES In normal mode MCLK/crystal oscillator is set up according to the desired sample rates of the ADC and DAC. For ADC or DAC sampling rates of 8, 32, 48 or 96kHz, MCLK frequencies of either 12.288MHz (256fs) or 18.432MHz (384fs) can be used. For ADC or DAC sampling rates of 8, 44.1 or 88.2kHz from MCLK frequencies of either 11.2896MHz (256fs) or 16.9344MHz (384fs) can be used. Table 18 should be used to set up the device to work with the various sample rate combinations. For example if the user wishes to use the WM8731/L in normal mode with the ADC and DAC sample rates at 48kHz and 48kHz respectively then the device should be programmed with BOSR = 0, SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0 with a 12.288MHz MCLK or with BOSR = 1, SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0 with a 18.432MHz MCLK. The ADC and DAC will then operate with a Digital Filter of type 1, refer to Digital Filter Characteristics section for an explanation of the different filter types.

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 SAMPLING RATE ADC DAC MCLK FREQUENCY SAMPLE RATE REGISTER SETTINGS DIGITAL FILTER TYPE kHz kHz MHz BOSR SR3 SR2 SR1 SR0 12.288 0 (256fs) 0 0 0 0 48 48 18.432 1 (384fs) 0 0 0 0 12.288 0 (256fs) 0 0 0 1 48 8 18.432 1 (384fs) 0 0 0 1 12.288 0 (256fs) 0 0 1 0 8 48 18.432 1 (384fs) 0 0 1 0 12.288 0 (256fs) 0 0 1 1 8 8 18.432 1 (384fs) 0 0 1 1 12.288 0 (256fs) 0 1 1 0 32 32 18.432 1 (384fs) 0 1 1 0 12.288 0 (128fs) 0 1 1 1 96 96 18.432 1 (192fs) 0 1 1 1 11.2896 0 (256fs) 1 0 0 0 44.1 44.1 16.9344 1 (384fs) 1 0 0 0 11.2896 0 (256fs) 1 0 0 1 44.1 8 (Note 1) 16.9344 1 (384fs) 1 0 0 1 11.2896 0 (256fs) 1 0 1 0 8 (Note 1) 44.1 16.9344 1 (384fs) 1 0 1 0 11.2896 0 (256fs) 1 0 1 1 8 (Note 1) (Note 1) 16.9344 1 (384fs) 1 0 1 1 11.2896 0 (128fs) 1 1 1 1 88.2 88.2 16.9344 1 (192fs) 1 1 1 1 Table 18 Normal Mode Sample Rate Look-up Table Notes: 1. 8k not exact, actual = 8.018kHz 2. All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid The BOSR bit represents the base over-sampling rate. This is the rate that the WM8731/L digital signal processing is carried out at. In Normal mode, with BOSR = 0, the base over-sampling rate is at 256fs, with BOSR = 1, the base over-sampling rate is at 384fs. This can be used to determine the actual audio data rate produced by the ADC and required by the DAC. Example scenarios are: 1. with a requirement that the ADC data rate is 8kHz and DAC data rate is 48kHz, then choosing MCLK = 12.288MHz the device is programmed with BOSR = 0 (256fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 = 0.The ADC output data rate will then be exactly 8kHz (derived from 12.288MHz/256 x1/6) and the DAC expects data at exactly 48kHz (derived from 12.288MHz/256) 2. with a requirement that ADC data rate is 8kHz and DAC data rate is 44.1kHz, then choosing MCLK = 16.9344MHz the device is programmed with BOSR = 1 (384fs), SR3 = 1, SR2 = 0, SR1 = 1, SR0 = 0. The ADC will no longer output data at exactly 8.000kHz, instead it will be 8.018kHz (derived from 16.9344MHz/384 x 2/11), the DAC still is at exactly 44.1kHz (derived from 16.9344MHz/384). A slight (sub 0.5%) pitch shift will therefore result in the 8kHz audio data and (importantly) the user must ensure that the data across the digital interface is correctly synchronised at the 8.018kHz rate.

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 The exact sample rates achieved are defined by the relationships in Table 19 below. ACTUAL SAMPLING RATE BOSR=0 BOSR=1 TARGET SAMPLING RATE MCLK=12.288 MCLK=11.2896 MCLK=18.432 MCLK=16.9344 kHz kHz kHz kHz kHz 8 8.018 8 8.018 8 (12.288MHz/256) x 1/6 (11.2896MHz/256) x 2/11 (18.432MHz/384) x 1/6 (16.9344MHz/384) x 2/11 32 32 32 (12.288MHz/256) x 2/3 not available (18.432MHz/384) x 2/3 not available 44.1 44.1 44.1 not available 11.2896MHz/256 not available 16.9344MHz /384 48 48 48 12.288MHz/256 not available 18.432MHz/384 not available 88.2 88.2 88.2 not available (11.2896MHz/256) x 2 not available (16.9344MHz /384) x 2 96 96 96 (12.288MHz/256) x 2 not available (18.432MHz/384) x 2 not available Table 19 Normal Mode Actual Sample Rates 128/192fs NORMAL MODE The Normal Mode sample rates are designed for standard 256fs and 384fs MCLK rates. However the WM8731/L is also capable of being clocked from a 128 or 192fs MCLK for application over limited sampling rates as shown in the table below. SAMPLING RATE ADC DAC MCLK FREQUENCY SAMPLE RATE REGISTER SETTINGS DIGITAL FILTER TYPE kHz kHz MHz BOSR SR3 SR2 SR1 SR0 6.144 0 0 1 1 1 48 48 9.216 1 0 1 1 1 5.6448 0 1 1 1 1 44.1 44.1 8.4672 1 1 1 1 1 Table 20 128fs Normal Mode Sample Rate Look-up Table 512/768fs NORMAL MODE 512 fs and 768 fs MCLK rates can be accommodated by using the CLKIDIV2 bit (Register 8, bit 6). The core clock to the DSP will be divided by 2 so an external 512/768 fs MCLK will become 256/384 fs internally and the device otherwise operates as in Table 18 but with MCLK at twice the specified rate. See Table 17 for software control.

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 USB MODE SAMPLE RATES In USB mode the MCLK/crystal oscillator input is 12MHz only. SAMPLING RATE ADC DAC MCLK FREQUENCY SAMPLE RATE REGISTER SETTINGS DIGITAL FILTER TYPE kHz kHz MHz BOSR SR3 SR2 SR1 SR0 48 48 12.000 0 0 0 0 0 0 44.1 (Note 2) 44.1 (Note 2) 12.000 1 1 0 0 0 1 48 8 12.000 0 0 0 0 1 0 44.1 (Note 2) (Note 1) 12.000 1 1 0 0 1 1 8 48 12.000 0 0 0 1 0 0 ((Note 1) 44.1 (Note 2) 12.000 1 1 0 1 0 1 8 8 12.000 0 0 0 1 1 0 (Note 1) (Note 1) 12.000 1 1 0 1 1 1 32 32 12.000 0 0 1 1 0 0 96 96 12.000 0 0 1 1 1 3 88.2 (Note 3) 88.2 (Note 3) 12.000 1 1 1 1 1 2 Table 21 USB Mode Sample Rate Look-up Table Notes: 1. 8k not exact, actual = 8.021kHz 2. 44.1k not exact, actual = 44.118kHz 3. 88.2k not exact, actual = 88.235kHz 4. All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid The table above can be used to set up the device to work with various sample rate combinations. For example if the user wishes to use the WM8731/L in USB mode with the ADC and DAC sample rates at 48kHz and 48kHz respectively then the device should be programmed with BOSR = 0, SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0. The ADC and DAC will then operate with a Digital Filter of type 0, refer to Digital Filter Characteristics section for an explanation of the different filter types. The BOSR bit represents the base over-sampling rate. This is the rate that the WM8731/L digital signal processing is carried out at and the sampling rate will always be a sub-multiple of this. In USB mode, with BOSR = 0, the base over-sampling rate is defined at 250fs, with BOSR = 1, the base over-sampling rate is defined at 272fs. This can be used to determine the actual audio sampling rate produced by the ADC and required by the DAC. Example scenarios are, :- 1. with a requirement that the ADC data sampling rate is 8kHz and DAC data sampling rate is 48kHz the device is programmed with BOSR = 0 (250fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 = 0.The ADC will then be exactly 8kHz ( derived from 12MHz/250 x 1/6 ) and the DAC expects data at exactly 48kHz ( derived from 12MHz/250 ). 2. with a requirement that ADC data rate is 8kHz and DAC data rate is 44.1kHz the device is programmed with BOSR = 1 (272fs), SR3 = 1, SR2 = 0, SR1 = 1, SR0 = 0. The ADC will not output data at exactly 8kHz, instead it will be 8.021kHz ( derived from 12MHz/272 x 2/11 ) and the DAC at 44.118kHz ( derived from 12MHz/272 ). A slight (sub 0.5%) pitch shift will therefore results in the 8kHz and 44.1kHz audio data and (more importantly) the user must ensure that the data across the digital interface is correctly synchronised at the 8.021kHz and 44.117kHz rates.

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 The exact sample rates supported for all combinations are defined by the relationships in Table 22 below. ACTUAL SAMPLING RATE TARGET SAMPLING RATE BOSR=0 ( 250fs) BOSR=1 (272fs) kHz kHz kHz 8 8.021 8 12MHz/(250 x 48/8) 12MHz/(272 x 11/2) 32 32 12MHz/(250 x 48/32) not available 44.117 44.1 not available 12MHz/272 48 48 12MHz/250 not available 88.235 88.2 not available 12MHz/136 96 96 12MHz/125 not available Table 22 USB Mode Actual Sample Rates ACTIVATING DSP AND DIGITAL AUDIO INTERFACE To prevent any communication problems from arising across the Digital Audio Interface the Audio Interface is disabled (tristate with weak 100k pulldown). Once the Audio Interface and the Sampling Control has been programmed it is activated by setting the ACTIVE bit under Software Control. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0001001 Active Control

0 ACTIVE 0 Activate Interface

1 = Active 0 = Inactive Table 23 Activating DSP and Digital Audio Interface It is recommended that between changing any content of Digital Audio Interface or Sampling Control Register that the active bit is reset then set. SOFTWARE CONTROL INTERFACE The software control interface may be operated using either a 3-wire (SPI-compatible) or 2-wire MPU interface. Selection of interface format is achieved by setting the state of the MODE pin. In 3-wire mode, SDIN is used for the program data, SCLK is used to clock in the program data and CSB is used to latch in the program data. In 2-wire mode, SDIN is used for serial data and SCLK is used for the serial clock. In 2-wire mode, the state of CSB pin allows the user to select one of two addresses. SELECTION OF SERIAL CONTROL MODE The serial control interface may be selected to operate in either 2 or 3-wire modes. This is achieved by setting the state of the MODE pin. MODE INTERFACE FORMAT 0 2 wire 1 3 wire Table 24 Control Interface Mode Selection

WM8731 / WM8731L Production Data w PD, Rev 4.8, April 2009 Once the WM8731/L has acknowledged a correct address, the controller will send eight data bits (bits B15-B8). WM8731/L will then acknowledge the sent data by pulling SDIN low for one clock pulse. The controller will then send the remaining eight data bits (bits B7-B0) and the WM8731/L will then acknowledge again by pulling SDIN low. A stop condition is defined when there is a low to high transition on SDIN while SCLK is high. If a start or stop condition is detected out of sequence at any point in the data transfer then the device will jump to the idle condition. After receiving a complete address and data sequence the WM8731/L returns to the idle state and waits for another start condition. Each write to a register requires the complete sequence of start condition, device address and R/W bit followed by the 16 register address and data bits. POWER DOWN MODES The WM8731/L contains power conservation modes in which various circuit blocks may be safely powered down in order to conserve power. This is software programmable as shown in the table below. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION