WM8725 WOLFSON | Alldatasheet

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Production Data, July 2000, Rev 2.0 WOLFSON MICROELECTRONICS LTD Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk http://www.wolfson.co.uk Production Data datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics’ Terms and Conditions.  2000 Wolfson Microelectronics Ltd.

DESCRIPTION

WM8725 is a high-performance stereo DAC designed for use in portable audio equipment, video CD players and similar applications. It comprises selectable normal or I compatible serial data interfaces for 16 to 24-bit digital inputs, high performance digital filters, and sigma-delta output DACs, achieving an excellent 99dB signal-to-noise performance. The device is available in a 14-pin SO package that offers selectable mute and de-emphasis functions using a minimum of external components.

FEATURES

  • Compatible with PCM1725
  • 99dB SNR performance
  • Stereo DAC with input sampling from 8kHz to 96kHz
  • Additional mute feature
  • Normal or I2S compatible data format
  • Sigma-delta design with 64x oversampling
  • System clock 256fs or 384fs
  • Supply range 3V to 5V
  • 14-pin SOIC package

APPLICATIONS

  • Portable audio equipment
  • Video CD players BLOCK DIAGRAM (5) CAP DIGITAL SIGMA-DELTA MODULATOR DIGITAL SIGMA-DELTA MODULATOR LRCIN (1) SERIAL INTERFACE DIGITAL FILTERS (12) DEEMPH (10) MUTE SWITCHED CAPACITOR DAC SWITCHED CAPACITOR DAC (8) VDD (7) GND (9) VOUTL (6) VOUTR BCKIN (3) FORMAT (13) SCKI (14) DIN (2) WM8725

WOLFSON MICROELECTRONICS LTD PD Rev 2.0 July 2000 ORDERING INFORMATIONPIN CONFIGURATION DEVICE TEMP. RANGE PACKAGE WM8725ED -25 to +85 oC 14-pin SOIC WM8725 VDD VOUTL MUTE NC DEEMPH SCKI FORMAT GND VOUTR CAP NC BCKIN LRCIN DIN ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION MIN MAX Supply voltage -0.3V +7.0V Reference input VCC+0.3V Operating temperature range, TA -25 o C+ 8 5 o C Storage temperature -65 o C +150 o C Lead temperature (soldering, 10 seconds) +260 o C Lead temperature (soldering, 2 minutes) +183 o C RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Supply Range VDD -10% 3.0 to 5.0 +10% V Ground GND 0 V VDD = 5V 15 25 mASupply Current VDD = 3V 7.5 mA

WOLFSON MICROELECTRONICS LTD PD Rev 2.0 July 2000

ELECTRICAL CHARACTERISTICS

VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Logic Levels Input LOW level VIL 0.8 V Input HIGH level VIH 2.0 V Analogue Output Levels To midrail or AC coupled (5V supply) 1 kohmsMinimum resistance load To midrail or AC coupled (3V supply) 1 kohms Maximum capacitance load 5V or 3V 100 pF Output DC level VDD /2 V Reference Levels Potential divider resistance VDD to CAP and CAP to GND 80 100 120 kohms Voltage at CAP VDD = 5V 2.3 2.5 2.7 V DAC Circuit Specifications SNR (Note 1) VDD = 5V 90 99 dB VDD = 3V 97 dB Full scale output voltage Into 10kohm VDD = 5V, 0dB 0.9 1.0 1.1 V RMS Into 10kohm VDD = 3V, 0dB 0.6 V RMS THD (Full scale) 0dB 0.01 0.02 % THD+N (Dynamic range) -60dB 92 dB Frequency response 0 20,000 Hz Transition band 20,000 Hz Out of band rejection -40 dB Channel Separation 90 dB Gain mismatch channel-to-channel ±1 ±5 %FSR Audio Data Input and System Clock Timing Information BCKIN pulse cycle time tBCY 100 ns BCKIN pulse width high tBCH 50 ns BCKIN pulse width low tBCL 50 ns BCKIN rising edge to LRCIN edge tBL 30 ns LRCIN rising edge to BCKIN rising edge tLB 30 ns DIN setup time tDS 30 ns DIN hold time tDH 30 ns System clock pulse width high tSCKIH 13 ns System clock pulse width low tSCKIL 13 ns Notes: 1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured “A” weighted over a 20Hz to 20kHz bandwidth. 2. All performance measurements done with 20kHz low pass filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible, it may affect dynamic specification values.

WOLFSON MICROELECTRONICS LTD PD Rev 2.0 July 2000 PIN DESCRIPTION PIN NAME TYPE DESCRIPTION

1 LRCIN Digital input Sample rate clock input

2 DIN Digital input Serial data input

3 BCKIN Digital input Bit clock input

4 NC No connect No internal connection

5 CAP Analogue output Analogue internal reference

6 VOUTR Analogue output Right channel DAC output

7 GND Supply 0V supply

8 VDD Supply Positive supply

9 VOUTL Analogue output Left channel DAC output

10 MUTE Digital input Mute control, high = muted. Internal pull-down

11 NC No connect No internal connection

12 DEEMPH Digital input De-emphasis select, high = de-emphasis ON. Internal pull-up 13 FORMAT Digital input Data input format select, low = normal, high = I 2S. Internal pull-up

14 SCKI Digital input System clock input (256fs or 384fs)

WOLFSON MICROELECTRONICS LTD PD Rev 2.0 July 2000 DEVICE DESCRIPTION INTRODUCTION WM8725 is a complete stereo audio 16-bit digital-to-analogue converter, including digital interpolation filter, multibit sigma-delta with dither, and switched capacitor multibit stereo DAC and output smoothing filters. Special functions of mute and de-emphasis are provided, and operation using system clock of 256fs or 384fs is provided, selection between either clock rate being automatically controlled. Sample rates (fs) from less than 8ks/s to 96ks/s are allowed, provided the appropriate system clock is input. MUTE DESCRIPTION

0 Mute is OFF

1 Mute is ON

A novel multi bit sigma-delta DAC design is used, utilising a 64x oversampling rate, to optimise signal to noise performance and offer increased clock jitter tolerance. Internally generated midrail references are used to DC bias output signals, requiring only a single external capacitor for decoupling purposes. The device is packaged in a small 14-pin SOIC package, offering pin compatibility with Burr Brown PCM1725, but with added functionality of a mute input pin, which may be left floating if unused, or held ‘low’ leaving the device operational. Single 3V to 5V supplies may be used, the output amplitude scaling with absolute supply level. Low supply voltage operation and low current consumption, and the low pin count small package, make the WM8725 attractive for many consumer type applications. DAC CIRCUITS The WM8725 DACs are designed to allow playback of 16-bit PCM audio or similar data with high resolution and low noise and distortion. Sample rates up to 96ks/s may be used, with much lower sample rates acceptable provided that the ratio of sample rate (LRCIN) to system clock is maintained at the required 256fs or 384fs times. The DACs on WM8725 are implemented using sigma-delta oversampled conversion techniques. These require that the PCM samples are digitally filtered and interpolated to generate a set of samples at a much higher rate than the 96ks/s input rate. This sample stream is then digitally modulated to generate a digital pulse stream that is then converted to analogue signals in a switched capacitor DAC. The advantage of this technique is that the DAC is linearised using noise shaping techniques, allowing the 16 bit resolution to be met using non-critical analogue components. A further advantage is that the high sample rate at the DAC output means that smoothing filters on the output of the DAC need only have fairly crude characteristics in order to remove the characteristic steps, or images, on the output of the DAC. To ensure that generation of tones characteristic to sigma-delta convertors is not a problem, dithering is used in the digital modulator and a higher order modulator is used. The switched capacitor technique used in the DAC reduces sensitivity to clock jitter compared to switched current techniques used in other implementations. De-emphasis of 44.1kHz signals may be applied if required. DEEMPH DESCRIPTION

0 De-emphasis is OFF

1 De-emphasis is ON

Table 2 De-emphasis Control The voltage on the CAP pin is used as the reference for the DACs, therefore the amplitude of the signals at the DAC outputs will scale with the amplitude of the voltage at the CAP. An external reference could be used to drive into the CAP pin if desired, but a value typically of about midrail should be used for optimum performance.

WOLFSON MICROELECTRONICS LTD PD Rev 2.0 July 2000 The outputs of the 2 DACs are buffered out of the device by buffer amplifiers. These amplifiers will source load current of several mA and sink current up to 1.5mA, so allowing significant loads to be driven. The output source is active and the sink is Class A, i.e. fixed value, so greater loads might be driven if an external ‘pull-down’ resistor is connected at the output. Typically an external low pass filter circuit will be used to remove residual sampling noise of the 64x oversampling used and if desired adjust the signal amplitude and device strength. SERIAL DATA INTERFACE WM8725 has serial interface formats that are fully compatible with both normal (MSB first, right-justified) and I 2S interfaces. The data format is selected with the FORMAT pin. When FORMAT is LOW, normal data format is selected. When the format is HIGH, I2S format is selected. It must be noted that in “packed” mode operation (exactly 32 BCLKs per LRCIN period), the data word must align exactly with LRCIN clock edges (effectively both left and right justified at the same time). This is true in both normal and I 2S modes. FORMAT DESCRIPTION

0 Normal format

(MSB-first, right justified)

1 I2S format

(Philips serial data protocol) Table 3 Serial Interface Formats MSB MSB LSB LSB LEFT CHANNEL RIGHT CHANNEL LRCIN BCKIN DIN Audio Data Word = 16-Bit 1/fs 123 1 4 1 5 16 123 1 4 1 5 16 Figure 1 ‘Normal’ Data Input Timing MSB MSB LSBLSB LEFT CHANNEL RIGHT CHANNEL LRCIN BCKIN DIN Audio Data Word = 16-Bit 1/fs 123 1 4 1 5 1 6 1 2 31 4 15 16 Figure 2 I2S Data Input Timing

WOLFSON MICROELECTRONICS LTD PD Rev 2.0 July 2000 PACKAGE DIMENSIONS NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-012, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. Symbols Dimensions (MM) Dimensions (Inches) MIN MAX MIN MAX A 1.35 1.75 0.0532 0.0688 A1 0.10 0.25 0.0040 0.0098 B 0.33 0.51 0.0130 0.0200 C 0.19 0.25 0.0075 0.0098 D 8.55 8.75 0.3367 0.3444 E 3.80 4.00 0.1497 0.1574 e 1.27 BSC 0.05 BSC H 5.80 6.20 0.2284 0.2440 h 0.25 0.50 0.0099 0.0196 L 0.40 1.27 0.0160 0.0500 α 0o 8o 0o 8o REF: JEDEC.95, MS-012 0.10 (0.004) SEATING PLANE DM001.C E D: 14 PIN SOIC 3.9mm Wide Body H B D A C h x 45o -C- α L e