WM8591GEDS/RV

WM8591 WOLFSON | Alldatasheet

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w WM8591 24-bit, 192kHz Stereo CODEC WOLFSON MICROELECTRONICS plc w :: www.wolfsonmicro.com Product Preview, May 2005, Rev 1.0 Copyright 2005 Wolfson Microelectronics plc

DESCRIPTION

The WM8591 is a high performance, stereo audio CODEC with single-ended inputs and differential outputs. It is ideal for surround sound processing applications for home hi-fi, DVD- RW and other audio visual equipment. The stereo 24-bit multi-bit sigma delta ADC has programmable gain with limiting control. Digital audio output word lengths from 16-32 bits and sampling rates from 32kHz to 96kHz are supported. A stereo multi-bit sigma delta DAC is used with digital audio input word lengths from 16-32 bits and sampling rates from 32kHz to 192kHz. The WM8591 supports fully independent sample rates for the ADC and DAC. The audio data interface supports I2S, left justified, right justified and DSP formats. The device is controlled in software via a 2-wire serial interface which provides access to all features including volume controls, mutes, and de-emphasis facilities. The device is available in a 28-pin SSOP package.

FEATURES

110dB SNR (‘A’ weighted @ 48kHz) DAC 102dB SNR (‘A’ weighted @ 48kHz) ADC DAC Sampling Frequency: 32kHz – 192kHz ADC Sampling Frequency: 32kHz – 96kHz Stereo ADC input analogue gain adjust from +24dB to –21dB in 0.5dB steps ADC digital gain from -21.5dB to -103dB in 0.5dB steps Programmable Limiter on ADC input. Stereo DAC with differential analogue line outputs. 2-wire Serial Control Interface Master or Slave Clocking Mode Programmable Audio Data Interface Modes I2S, Left, Right Justified or DSP 16/20/24/32 bit Word Lengths 4.5V to 5.5V Analogue, 2.7V to 3.6V Digital supply Operation 28-pin SSOP Package

APPLICATIONS

Surround Sound AV Processors and Hi-Fi systems DVD-RW

w PP Rev 1.0 May 2005 TABLE OF CONTENTS

w PP Rev 1.0 May 2005 PIN CONFIGURATION

ORDERING INFORMATION

-25 to +85oC 28-pin SSOP (lead free) MSL2 260°C WM8591GEDS/RV -25 to +85oC 28-pin SSOP (lead free, tape and reel) MSL2 260°C Note: Reel quantity = 2,000

w PP Rev 1.0 May 2005 PIN DESCRIPTION PIN NAME TYPE (open drain) Right channel zero flag output (external pull-up required) ZFLAGL Digital Output (open drain) Left channel zero flag output (external pull-up required) ADCLRC Digital Input/Output ADC left/right word clock ADCBCLK Digital Input/Output ADC audio interface bit clock ADCMCLK Digital Input Master ADC clock; 256, 384, 512 or 768fs (fs = word clock frequency) DOUT Digital Output ADC data output DACLRC Digital Input/Output DAC left/right word clock DACBCLK Digital Input/Output DAC audio interface bit clock DACMCLK Digital Input Master DAC clock; 256, 384, 512, 768fs or 1152fs (fs = word clock frequency) DIN Digital Input DAC data input DVDD Supply Digital positive supply DGND Supply Digital negative supply VOUTRP Analogue Output DAC right channel positive output VOUTRN Analogue Output DAC right channel negative output VOUTLP Analogue Output DAC left channel positive output VOUTLN Analogue Output DAC left channel negative output AGND Supply Analogue negative supply and substrate connection REFN Analogue Input Negative reference input VMID Analogue Output Midrail divider decoupling pin; must be externally decoupled REFP Analogue Input Positive reference input AVDD Supply Analogue positive supply NC No Connection AINL Analogue Input Left channel input NC No Connection AINR Analogue Input Right channel input CE Digital Input 2-wire address select Notes: Digital input pins have Schmitt trigger input buffers.

w PP Rev 1.0 May 2005 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION MIN MAX Digital supply voltage, DVDD -0.3V +3.63V Analogue supply voltage, AVDD -0.3V +7V Voltage range digital inputs DGND -0.3V DVDD + 0.3V Voltage range analogue inputs AGND -0.3V AVDD +0.3V Master Clock Frequency 37MHz Operating temperature range, TA -25°C +85°C Storage temperature -65°C +150°C Notes: Analogue and digital grounds must always be within 0.3V of each other.

w PP Rev 1.0 May 2005 RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital supply range DVDD 2.7 3.3 3.6 V Analogue supply range AVDD, DACREFP 4.5 5.5 V Ground AGND, DGND, DACREFN, ADCREFGND V Difference DGND to AGND -0.3 +0.3 V Note: Digital supply DVDD must never be more than 0.3V greater than AVDD.

ELECTRICAL CHARACTERISTICS

AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Logic Levels (CMOS Levels) Input LOW level VIL 0.3 x DVDD V Input HIGH level VIH 0.7 x DVDD V Output LOW VOL IOL=1mA 0.1 x DVDD V Output HIGH VOH IOH=1mA 0.9 x DVDD V Digital Input Leakage Current 0.9 µA Digital Input Leakage Capacitance TBD pF Analogue Reference Levels Reference voltage VVMID AVDD/2 V Potential divider resistance RVMID kΩ DAC Performance (Load = 10kΩ, 50pF) 0dBFs Full scale output voltage 2.0 x AVDD/5 Vrms SNR (Note 1,2) SNR A-weighted, @ fs = 48kHz 105 110 dB SNR (Note 1,2) SNR A-weighted @ fs = 96kHz 109 dB Dynamic Range (Note 2) DNR A-weighted, -60dB full scale input 100 110 dB Total Harmonic Distortion THD 1kHz, 0dBFs -97 -90 dB DAC channel separation 130 dB Channel Level Matching 1kHz signal 0.1 dB Channel Phase Deviation 1kHz signal 0.04 Degree 1kHz 100mVpp dB Power Supply Rejection Ratio PSRR 20Hz to 20kHz 100mVpp dB ADC Performance Input Signal Level (0dB) 1.0 x AVDD/5 Vrms SNR (Note 1,2) SNR A-weighted, 0dB gain @ fs = 48kHz 102 dB SNR (Note 1,2) SNR A-weighted, 0dB gain @ fs = 96kHz 64 x OSR dB Dynamic Range (note 2) DNR A-weighted, -60dB full scale input 102 dB 1kHz, 0dBFs -90 dB Total Harmonic Distortion THD 1kHz, -3dBFs -95 -85 dB

w PP Rev 1.0 May 2005 Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. ADC Channel Separation 1kHz Input dB Channel Level Matching 1kHz signal 0.1 dB Channel Phase Deviation 1kHz signal 0.06 Degree Programmable Gain Step Size 0.25 0.5 0.75 dB Programmable Gain Range (Analogue) 1kHz Input -21 +24 dB Programmable Gain Range (Digital) 1kHz Input -103 -21.5 dB Mute Attenuation (Note 4) 1kHz Input, 0dB gain dB 1kHz 100mVpp dB Power Supply Rejection Ratio PSRR 20Hz to 20kHz 100mVpp dB PGA Gain = +24dB 4.5 kΩ PGA Gain = 0dB 37.4 kΩ Input Resistance PGA Gain = -21dB 69.0 kΩ Input Capacitance pF Supply Current Analogue supply current AVDD = 5V mA Digital supply current DVDD = 3.3V 7.4 mA Analogue Powerdown Current AVDD = 5V 132 µA Digital Powerdown Current DVDD = 3.3V 2.7 µA Crosstalk 1kHz signal, ADC fs = 48kHz, DAC fs = 44.1kHz 115 dB DAC to ADC 20kHz signal, ADC fs = 48kHz, DAC fs = 44.1kHz 130 dB 1kHz signal, ADC fs = 48kHz, DAC fs = 44.1kHz 131 dB ADC to DAC 20kHz signal, ADC fs = 48kHz, DAC fs = 44.1kHz 138 dB Notes: Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. All performance measurement done using certain timings conditions (Please refer to section ‘Digital Audio Interface’). A better MUTE Attenuation can be achieved if the ADC gain is set to minimum.

w PP Rev 1.0 May 2005 TERMINOLOGY Signal-to-noise ratio (dB) – SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) – DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) – THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Stop band attenuation (dB) – Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) – Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. Pass-Band Ripple – Any variation of the frequency response in the pass-band region.

w PP Rev 1.0 May 2005 ADCBCLK/ DACBCLK DACLRC/ ADCLRC tBCH tBCL tBCY DIN DOUT tLRSU tDS tLRH tDH tDD Figure 5 Digital Audio Data Timing – Slave Mode Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, ADC/DACMCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information ADC/DACBCLK cycle time tBCY ns ADC/DACBCLK pulse width high tBCH ns ADC/DACBCLK pulse width low tBCL ns DACLRC/ADCLRC set-up time to ADC/DACBCLK rising edge tLRSU ns DACLRC/ADCLRC hold time from ADC/DACBCLK rising edge tLRH ns DIN set-up time to DACBCLK rising edge tDS ns DIN hold time from DACBCLK rising edge tDH ns DOUT propagation delay from ADCBCLK falling edge tDD ns Table 3 Digital Audio Data Timing – Slave Mode Note: ADCLRC and DACLRC should be synchronous with MCLK, although the WM8591 interface is tolerant of phase variations or jitter on these signals.

w PP Rev 1.0 May 2005 CONTROL INTERFACE TIMING – 2-WIRE SERIALCONTROL DI CL Figure 6 Control Interface Timing – 2-Wire Serial Control Mode (MODE=0) Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information CL Frequency 526 kHz CL Low Pulse-Width 1.3 us CL High Pulse-Width 600 ns Hold Time (Start Condition) 600 ns Setup Time (Start Condition) 600 ns Data Setup Time 100 ns DI, CL Rise Time 300 ns DI, CL Fall Time 300 ns Setup Time (Stop Condition) 600 ns Data Hold Time 900 ns Pulse width of spikes that will be suppressed tps ns Table 4 2-wire Control Interface Timing Information

w PP Rev 1.0 May 2005 DEVICE DESCRIPTION INTRODUCTION WM8591 is a complete differential 2-channel DAC, single-ended 2-channel ADC audio CODEC, including digital interpolation and decimation filters, multi-bit sigma delta stereo ADC, and switched capacitor multi-bit sigma delta DACs with output smoothing filters. It is available in a single package and controlled by a 2-wire serial interface. The DAC and ADC have separate left/right clocks, bit clocks, master clocks and data I/Os. The Audio Interfaces may be independently configured to operate in either master or slave mode. In Slave mode ADCLRC, DACLRC, ADCBCLK and DACBCLK are all inputs. In Master mode ADCLRC, DACLRC, ADCBCLK and DACBCLK are outputs. The ADC has an analogue input PGA and a digital gain control, accessed by one register write. The input PGA allows input signals to be gained up to +24dB and attenuated down to -21dB in 0.5dB steps. The digital gain control allows attenuation from -21.5dB to -103dB in 0.5dB steps. This allows the user maximum flexibility in the use of the ADC. The DAC has its own digital volume control, which is adjustable between 0dB and -127.5dB in 0.5dB steps. In addition a zero cross detect circuit is provided for digital volume controls. The digital volume control detects a transition through the zero point before updating the volume. This minimises audible clicks and ‘zipper’ noise as the gain values change. Control of internal functionality of the device is by 2-wire serial control interface. The interface may be asynchronous to the audio data interface as control data will be re-synchronised to the audio processing internally. Operation using system clock of 128fs, 192fs, 256fs, 384fs, 512fs, 768fs or 1152fs (DAC only) is provided. ADC and DAC may run at different rates. Master clock sample rates (fs) from less than 32kHz up to 192kHz are allowed, provided the appropriate system clock is input. The audio data interface supports right, left and I2S interface formats along with a highly flexible DSP serial port interface. AUDIO DATA SAMPLING RATES In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s Master Clock. The WM8591 uses separate master clocks for the ADC and DAC. The external master system clocks can be applied directly through the ADCMCLK and DACMCLK input pins with no software configuration necessary. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the ADC and DAC. In Slave mode the WM8591 has a master detection circuit that automatically determines the relationship between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If there is a greater than 32 clocks error the interface is disabled and maintains the output level at the last sample. The master clock must be synchronised with ADCLRC/DACLRC, although the WM8591 is tolerant of phase variations or jitter on this clock. The ADC supports system clock to sampling clock ratios of 256fs to 768fs. The DACs support ratios of 256fs to 1152fs when the DAC signal processing of the WM8591 is programmed to operate at 128 times oversampling rate (DACOSR=0). The DACs support system clock to sampling clock ratios of 128fs and 192fs when the WM8591 is programmed to operate at 64 times oversampling rate (DACOSR=1). The ADC signal processing in the WM8591 can operate at either 128 times oversampling rate (ADCOSR=0) or 64 times oversampling rate (ADCOSR=1). It is recommended that ADCOSR is set to 1 for ADC operation at 96kHz.

w PP Rev 1.0 May 2005 Table 5 shows the typical system clock frequencies for ADC operation at both 128 times oversampling rate (ADCOSR=0) and 64 times oversampling rate (ADCOSR=1), and DAC operation at 128 times oversampling rate (DACOSR=0). Table 6 shows typical system clock frequencies for DAC operation at 64 times oversampling rate (DACOSR =1). System Clock Frequency (MHz) SAMPLING RATE (ADCLRC/ DACLRC) 256fs 384fs 512fs 768fs 1152fs (DAC only) 32kHz 8.192 12.288 16.384 24.576 36.864 44.1kHz 11.2896 16.9340 22.5792 33.8688 Unavailable 48kHz 12.288 18.432 24.576 36.864 Unavailable 96kHz 24.576 36.864 Unavailable Unavailable Unavailable Table 5 ADC and DAC System Clock Frequencies Versus Sampling Rate (ADC operation at either 128 times oversampling rate (ADCOSR=0) or 64 times oversampling rate (ADCOSR=1), DAC operation at 128 times oversampling rate, DACOSR=0) System Clock Frequency (MHz) SAMPLING RATE (DACLRC) 128fs 192fs 96kHz 12.288 18.432 192kHz 24.576 36.864 Table 6 DAC System Clock Frequencies Versus Sampling Rate at 64 Times Oversampling Rate (DACOSR=1) In Master mode DACBCLK, ADCBCLK, DACLRC and ADCLRC are generated by the WM8591. The frequencies of ADCLRC and DACLRC are set by setting the required ratio of DACMCLK to DACLRC and ADCMCLK to ADCLRC using the DACRATE and ADCRATE control bits (Table 7). ADCRATE[2:0]/ DACRATE[2:0] ADCMCLK/DACMCLK: ADCLRC/DACLRC RATIO 000 128fs (DAC Only) 001 192fs (DAC Only) 010 256fs 011 384fs 100 512fs 101 768fs Table 7 Master Mode MCLK: ADCLRC/DACLRC Ratio Select Table 8 shows the settings for ADCRATE and DACRATE for common sample rates and ADCMCLK/DACMCLK frequencies. System Clock Frequency (MHz) 128fs 192fs 256fs 384fs 512fs 768fs SAMPLING RATE (DACLRC/ ADCLRC) DACRATE =000 DACRATE =001 ADCRATE/ DACRATE =010 ADCRATE/ DACRATE =011 ADCRATE/ DACRATE =100 ADCRATE/ DACRATE =101 32kHz 4.096 6.144 8.192 12.288 16.384 24.576 44.1kHz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688 48kHz 6.144 9.216 12.288 18.432 24.576 36.864 96kHz 12.288 18.432 24.576 36.864 Unavailable Unavailable 192kHz 24.576 36.864 Unavailable Unavailable Unavailable Unavailable Table 8 Master Mode ADC/DACLRC Frequency Selection

w PP Rev 1.0 May 2005 ADCBCLK and DACBCLK are also generated by the WM8591. The frequency of ADCBCLK and DACBCLK can be set in software. BCLK can be set to MCLK/4, 64fs or 128fs. If DSP mode is selected as the audio interface mode then BCLK can be set to MCLK, 64fs or 128fs. Note that DSP mode cannot be used in 128fs mode for word lengths greater than 16 bits or in 192fs mode for word lengths greater than 24 bits. ZERO DETECT The WM8591 has a zero detect circuit for each DAC channel, which detects when 1024 consecutive zero samples have been input. The two zero flag outputs (ZFLAGL and ZFLAGR) may be programmed to output the zero detect signals (see Table 9) that may then be used to control external muting circuits. The ZFLAGL and ZFLAGR pins require a pull-up resistor to be connected (see external components diagram). The ZFLAGL and ZFLAGR pads will pull low to indicate that the zero condition has been detected. The polarity of the zero flag signals can be changed by setting the ZFLAGPOL bit. When this bit is set, the ZFLAGL and ZFLAGR pins will pull low when the zero condition is not found and will go to high impedance when the zero condition is detected. The zero detect may also be used to automatically enable the mute by setting IZD. The zero flag output may be disabled by setting DZFM to 00. Table 9 Zero Flag Control POWERDOWN MODES The WM8591 has powerdown control bits allowing specific parts of the WM8591 to be powered off when not being used. Control bit ADCPD powers off the ADC. The stereo DAC has a separate powerdown control bit, DACPD allowing the DAC to be powered off when not in use. Setting ADCPD and DACPD will powerdown everything except the references VMID, REFN and REFP. Setting PDWN will override all other powerdown control bits. It is recommended that ADCPD and DACPD are set before setting PDWN. The default is for all blocks to be enabled. REGISTER ADDRESS BIT LABEL DEFAULT Sets ADCBCLK and DACBCLK rate in master mode BCLK_RATE BCLK Output Frequency MCLK/4 (MCLK in DSP Mode) MCLK/4 (MCLK in DSP Mode) 64fs R28 (1Ch) 0011100 ADC/DAC Synchronization 3:2 BCLK_RATE 128fs REGISTER ADDRESS BIT LABEL DEFAULT 2:1 DZFM Either channels zero Either channel zero ZFLAG polarity ZFLAGPOL ZFLAGL ZFLAGR Pin pulls low to indicate zero conidition, high impedance otherwise R9 (09h) 0001001 DAC Mute ZFLAGPOL Pin is high impedance when zero condition detected, pulls low otherwise

w PP Rev 1.0 May 2005 Figure 11 Master Mode AUDIO INTERFACE FORMATS Audio data is applied to the internal DAC filters or output from the ADC filters, via the Digital Audio Interface. 5 popular interface formats are supported: Left Justified mode Right Justified mode I2S mode DSP Early mode DSP Late mode All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit right justified mode, which is not supported. In left justified, right justified and I2S modes, the digital audio interface receives DAC data on the DIN input and outputs ADC data on DOUT. Audio Data for each stereo channel is time multiplexed with ADCLRC/DACLRC indicating whether the left or right channel is present. ADCLRC/DACLRC is also used as a timing reference to indicate the beginning or end of the data words. In left justified, right justified and I2S modes; the minimum number of BCLKs per DACLRC/ADCLRC period is 2 times the selected word length. ADCLRC/DACLRC must be high for a minimum of word length BCLKs and low for a minimum of word length BCLKs. Any mark to space ratio on ADCLRC/DACLRC is acceptable provided the above requirements are met. In DSP early or DSP late mode, DACLRC is used as a frame sync signal to identify the MSB of the first word. The minimum number of DACBCLKs per DACLRC period is 2 times the selected word length. Any mark to space ratio is acceptable on DACLRC provided the rising edge is correctly positioned. The ADC data may also be output in DSP early or late modes, with ADCLRC used as a frame sync to identify the MSB of the first word. The minimum number of ADCBCLKs per ADCLRC period is 2 times the selected word length. LEFT JUSTIFIED MODE In left justified mode, the MSB of DIN is sampled by the WM8591 on the first rising edge of DACBCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the same falling edge of ADCBCLK as ADCLRC and may be sampled on the rising edge of ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right samples (Figure 12). ADCBCLK DOUT ADCLRC DIN DACLRC WM8591 CODEC DVD Controller DACBCLK

w PP Rev 1.0 May 2005 LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK DIN/ DOUT 1/fs n n-2 n-1 LSB MSB n n-2 n-1 LSB MSB Figure 12 Left Justified Mode Timing Diagram RIGHT JUSTIFIED MODE In right justified mode, the LSB of DIN is sampled by the WM8591 on the rising edge of DACBCLK preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and changes on the falling edge of ADCBCLK preceding a ADCLRC transition and may be sampled on the rising edge of ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right samples (Figure 13). LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK DIN/ DOUT 1/fs n n-2 n-1 LSB MSB n n-2 n-1 LSB MSB Figure 13 Right Justified Mode Timing Diagram I2S MODE In I2S mode, the MSB of DIN is sampled by the WM8591 on the second rising edge of DACBCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the first falling edge of ADCBCLK following an ADCLRC transition and may be sampled on the rising edge of ADCBCLK. ADCLRC and DACLRC are low during the left samples and high during the right samples. LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK DIN/ DOUT 1/fs n n-2 n-1 LSB MSB n n-2 n-1 LSB MSB

1 BCLK

Figure 14 I2S Mode Timing Diagram

w PP Rev 1.0 May 2005 REGISTER ADDRESS BIT LABEL DEFAULT R10 (0Ah) 0001010 DAC Interface Control DACBCP R11 (0Bh) 0001011 ADC Interface Control ADCBCP BCLK Polarity (DSP modes) 0 : normal BCLK polarity 1: inverted BCLK polarity The WL[1:0] bits are used to control the input word length. REGISTER ADDRESS BIT LABEL DEFAULT R10 (0Ah) 0001010 DAC Interface Control 5:4 DACWL [1:0] R11 (0Bh) 0001011 ADC Interface Control 5:4 ADCWL [1:0] Word Length 00 : 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data Note: If 32-bit mode is selected in right justified mode, the WM8591 defaults to 24 bits. In all modes, the data is signed 2’s complement. The digital filters always input 24-bit data. If the DAC is programmed to receive 16 or 20 bit data, the WM8591 pads the unused LSBs with zeros. If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored. Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that ADCLRC/DACLRC is high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs. A number of options are available to control how data from the Digital Audio Interface is applied to the DAC. MASTER MODES Control bit ADCMS selects between audio interface Master and Slave Modes for ADC. In ADC Master mode ADCLRC and ADCBCLK are outputs and are generated by the WM8591. In Slave mode ADCLRC and ADCBCLK are inputs to WM8591. REGISTER ADDRESS BIT LABEL DEFAULT R12 (0Ch) 0001100 Interface Control ADCMS Audio Interface Master/Slave Mode select for ADC: 0 : Slave Mode 1: Master Mode Control bit DACMS selects between audio interface Master and Slave Modes for the DAC. In DAC Master mode DACLRC and DACBCLK are outputs and are generated by the WM8591. In Slave mode DACLRC and DACBCLK are inputs to WM8591. REGISTER ADDRESS BIT LABEL DEFAULT R12 (0Ch) 0001100 Interface Control DACMS Audio Interface Master/Slave Mode select for DAC: 0 : Slave Mode 1: Master Mode MASTER MODE ADCLRC/DACLRC FREQUENCY SELECT In ADC Master mode the WM8591 generates ADCLRC and ADCBCLK, in DAC master mode the WM8591 generates DACLRC and DACBCLK. These clocks are derived from the master clock (ADCMCLK or DACMCLK). The ratios of ADCMCLK to ADCLRC and DACMCLK to DACLRC are set by ADCRATE and DACRATE respectively.

w PP Rev 1.0 May 2005 REGISTER ADDRESS BIT LABEL DEFAULT 2:0 ADCRATE[2:0] 010 Master Mode MCLK:ADCLRC Ratio Select: 010: 256fs 011: 384fs 100: 512fs 101: 768fs R12 (0Ch) 0001100 ADCLRC and DACLRC Frequency Select 6:4 DACRATE[2:0] 010 Master Mode MCLK:DACLRC Ratio Select: 000: 128fs 001: 192fs 010: 256fs 011: 384fs 100: 512fs 101: 768fs ADC OVERSAMPLING RATE SELECT For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate to 64fs. Operation is explained further in Table 5. REGISTER ADDRESS BIT LABEL DEFAULT R12 (0Ch) 0001100 ADC Oversampling Rate ADCOSR ADC Oversampling Rate Select 0: 128x oversampling 1: 64x oversampling DAC OVERSAMPLING RATE SELECT Control bit DACOSR allows the user to select the DAC internal signal processing oversampling rate. Operation is described in Table 5 and Table 6. REGISTER ADDRESS BIT LABEL DEFAULT R10 (0Ah) 0001010 DAC Oversampling Rate DACOSR DAC Oversampling Rate Select 0: 128x oversampling 1: 64x oversampling MUTE MODES Setting MUTE for the DAC will apply a ‘soft’ mute to the input of the digital filters of the channel muted. REGISTER ADDRESS BIT LABEL DEFAULT R9 (09h) 0001001 DAC Mute DMUTE DAC Soft Mute Select 0 : Normal Operation 1: Soft mute enabled

w PP Rev 1.0 May 2005 ADC MUTE Each ADC channel also has an individual mute control bit, which mutes the input to the ADC PGA. By setting the LRBOTH bit (reg22, bit 8) both channels can be muted simultaneously. REGISTER ADDRESS BIT LABEL DEFAULT R21 (15h) 0010101 ADC Mute Left MUTELA ADC Mute Select 0 : Normal Operation 1: mute ADC left R21 (15h) 0001111 ADC Mute Right MUTERA ADC Mute Select 0 : Normal Operation 1: mute ADC right DE-EMPHASIS MODE The De-emphasis filter for the DAC is enabled under the control of DEEMP. REGISTER ADDRESS BIT LABEL DEFAULT R9 (09h) 0001001 DAC De-emphasis Control DEEMPH De-emphasis Mode Select: 0 : Normal Mode 1: De-emphasis Mode Refer to Figure 30, Figure 31, Figure 32, Figure 33, Figure 34 and Figure 35 for details of the De- Emphasis modes at different sample rates. POWERDOWN MODE AND ADC/DAC DISABLE Setting the PDWN register bit immediately powers down the WM8591, including the references, overriding all other powerdown control bits. All trace of the previous input samples is removed, but all control register settings are preserved. When PDWN is cleared, the digital filters will be re-initialised. It is recommended that the buffer, ADC and DAC are powered down before setting PDWN. REGISTER ADDRESS BIT LABEL DEFAULT R13 (0Dh) 0001101 Powerdown Control PDWN Power Down Mode Select: 0 : Normal Mode 1: Power Down Mode The ADC and DAC may also be powered down by setting the ADCPD and DACPD disable bits. Setting ADCPD will disable the ADC and select a low power mode. The ADC digital filters will be reset and will reinitialise when ADCPD is reset. The DAC has a separate disable DACPD. Setting DACPD will disable the DAC, mixer and output PGAs. Resetting DACPD will reinitialise the digital filters. REGISTER ADDRESS BIT LABEL DEFAULT ADC Powerdown: 0 : Normal Mode 1: Power Down Mode R13 (0Dh) 0001101 Powerdown Control DACPD DAC Powerdown: 0 : Normal Mode 1: Power Down Mode

w PP Rev 1.0 May 2005 DIGITAL ATTENUATOR CONTROL MODE Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and right channel DACs from the next audio input sample. No update to the attenuation registers is required for ATC to take effect. REGISTER ADDRESS BIT LABEL DEFAULT R7 (07h) 0000111 DAC Channel Control ATC Attenuator Control Mode: 0 : Right channel use Right attenuation 1: Right Channel use Left Attenuation INFINITE ZERO DETECT ENABLE Setting the IZD register bit will enable the internal infinite zero detect function: REGISTER ADDRESS BIT LABEL DEFAULT R7 (07h) 0000111 DAC Channel Control IZD Infinite Zero Mute Enable 0 : disable infinite zero mute 1: enable infinite zero Mute With IZD enabled, applying 1024 consecutive zero input samples to the DAC will cause both DAC outputs to be muted. Mute will be removed as soon as any channel receives a non-zero input. DAC OUTPUT CONTROL The DAC output control word determines how the left and right inputs to the audio Interface are applied to the left and right DACs: REGISTER ADDRESS BIT LABEL DEFAULT PL[3:0] Left Output Right Output 0000 Mute Mute 0001 Left Mute 0010 Right Mute 0011 (L+R)/2 Mute 0100 Mute Left 0101 Left Left 0110 Right Left 0111 (L+R)/2 Left 1000 Mute Right 1001 Left Right 1010 Right Right 1011 (L+R)/2 Right 1100 Mute (L+R)/2 1101 Left (L+R)/2 1110 Right (L+R)/2 R7 (07h) 0000111 DAC Control 7:4 PL[3:0] 1001 1111 (L+R)/2 (L+R)/2

w PP Rev 1.0 May 2005 DAC DIGITAL VOLUME CONTROL The DAC volume may also be adjusted in the digital domain using independent digital attenuation control registers REGISTER ADDRESS BIT LABEL DEFAULT 7:0 LDA[7:0] 11111111 (0dB) Digital Attenuation data for Left channel DACL in 0.5dB steps. See Table 11 R3 (03h) 0000011 Digital Attenuation DACL UPDATED Not latched Controls simultaneous update of Attenuation Latches 0: Store LDA in intermediate latch (no change to output) 1: Store LDA and update attenuation on both channels 7:0 RDA[6:0] 11111111 (0dB) Digital Attenuation data for Right channel DACR in 0.5dB steps. See Table 11 R4 (04h) 0000100 Digital Attenuation DACR UPDATED Not latched Controls simultaneous update of Attenuation Latches 0: Store RDA in intermediate latch (no change to output) 1: Store RDA and update attenuation on both channels. 7:0 MDA[7:0] 11111111 (0dB) Digital Attenuation data for DAC channels in 0.5dB steps. See Table R5 (05h) 0000101 Master Digital Attenuation (both channels) UPDATED Not latched Controls simultaneous update of Attenuation Latches 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on channels. L/RDA[7:0] ATTENUATION LEVEL 00(hex) -∞ dB (mute) 01(hex) -127dB FE(hex) -0.5dB FF(hex) 0dB Table 11 Digital Volume Control Attenuation Levels The digital volume control also incorporates a zero cross detect circuit which detects a transition through the zero point before updating the digital volume control with the new volume. This is enabled by control bit DZCEN. REGISTER ADDRESS BIT LABEL DEFAULT R7 (07h) 0000111 DAC Control DZCEN DAC Digital Volume Zero Cross Enable: 0: Zero cross detect disabled 1: Zero cross detect enabled DAC OUTPUT PHASE The DAC Phase control word determines whether the output of the DAC is non-inverted or inverted REGISTER ADDRESS BIT LABEL DEFAULT 1 = invert R6 (06h) 0000110 DAC Phase 1:0 PHASE [1:0] DACR 1 = invert

w PP Rev 1.0 May 2005 ADC GAIN CONTROL The ADC has an analogue input PGA and digital gain control for each stereo channel. Both the analogue and digital gains are adjusted by the same register, LAG for the left and RAG for the right. The analogue PGA has a range of +24dB to -21dB in 0.5dB steps. The digital gain control allows further attenuation (after the ADC) from -21.5dB to -103dB in 0.5dB steps. Table 12 shows how the register maps the analogue and digital gains. LAG/RAG[7:0] ATTENUATION LEVEL (AT OUTPUT) ANALOGUE PGA DIGITAL ATTENUATION 00(hex) -∞ dB (mute) -21dB Digital mute 01(hex) -103dB -21dB -82dB A4(hex) -21.5dB -21dB -0.5dB A5(hex) -21dB -21dB 0dB CF(hex) 0dB 0dB 0dB FE(hex) +23.5dB +23.5dB 0dB FF(hex) +24dB +24dB 0dB Table 12 Analogue and Digital Gain Mapping for ADC In addition a zero cross detect circuit is provided for the input PGA. When ZCLA/ZCRA is set with a write, the gain will update only when the input signal approaches zero (midrail). This minimises audible clicks and ‘zipper’ noise as the gain values change. A timeout clock is also provided which will generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of 12.288MHz). The timeout clock may be disabled by setting TOD. REGISTER ADDRESS BIT LABEL DEFAULT R7 (07h) 0000111 Timeout Clock Disable TOD Analogue PGA Zero Cross Detect Timeout Disable 0 : Timeout enabled 1: Timeout disabled

w PP Rev 1.0 May 2005 Left and right inputs may also be independently muted. The LRBOTH control bit allows the user to write the same attenuation value to both left and right volume control registers, saving on software writes. The ADC volume and mute also applies to the bypass signal path. REGISTER ADDRESS BIT LABEL DEFAULT 7:0 LAG[7:0] 11001111 (0dB) Attenuation Data for Left Channel ADC Gain in 0.5dB steps. See Table 12. R14 (0Eh) 0001110 Attenuation ADCL ZCLA Left Channel ADC Zero Cross Enable: 0: Zero cross disabled 1: Zero cross enabled 7:0 RAG[7:0] 11001111 (0dB) Attenuation data for right channel ADC gain in 0.5dB steps. See Table 12. R15 (0Fh) 0001111 Attenuation ADCR ZCRA Right Channel ADC Zero Cross Enable: 0: Zero cross disabled 1: Zero cross enabled MUTERA Mute for Right Channel ADC 0: Mute Off 1: Mute on MUTELA Mute for Left Channel ADC 0: Mute Off 1: Mute on R21 (15h) 0010101 ADC Input Mux LRBOTH Right Channel Input PGA Controlled by Left Channel Register 0: Right channel uses RAG and MUTERA 1: Right channel uses LAG and MUTELA

w PP Rev 1.0 May 2005 ADC/DAC SYNCHRONIZATION The WM8591 has a range of features which can be configured to enhance the performance of the ADC and DAC when operated simultaneously. REGISTER ADDRESS BIT LABEL DEFAULT ADCMCLK Polarity: 0: non-inverted 1: inverted R11 (0Bh) ADC Interface Control DACSYNCEN Enable the DAC Synchronizer: 0: Disabled 1: Enabled ADCSYNCEN Enable the ADC Synchronizer: 0: Disabled 1: Enabled ADCMCLK2DAC Set both ADC and DAC to use ADCMCLK: 0: DAC uses DACMCLK 1: DAC uses ADCMCLK ADCMCLKX2 Allows DAC synchronizer to synchronize to ADC operating at 2x DAC rate: 0: Disabled 1: Enabled DACMCLKINV DACMCLK Polarity: 0: non-inverted 1: inverted DACMCLKX2 Allows ADC synchronizer to synchronize to DAC operating at 2x ADC rate: 0: Disabled 1: Enabled R28 (1Ch) 0011100 ADC/DAC Synchronization DACMCLK2ADC Set both DAC and ADC to use DACMCLK: 0: ADC uses ADCMCLK 1: ADC uses DACMCLK

w PP Rev 1.0 May 2005 LIMITER / AUTOMATIC LEVEL CONTROL (ALC) The WM8591 has an automatic pga gain control circuit, which can function as a peak limiter or as an automatic level control (ALC). In peak limiter mode, a digital peak detector detects when the input signal goes above a predefined level and will ramp the pga gain down to prevent the signal becoming too large for the input range of the ADC. When the signal returns to a level below the threshold, the pga gain is slowly returned to its starting level. The peak limiter cannot increase the pga gain above its static level. Figure 21 Limiter Operation In ALC mode, the circuit aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary. input signal signal after PGA PGA gain Limiter threshold attack time decay time

w PP Rev 1.0 May 2005 Figure 22 ALC Operation The gain control circuit is enabled by setting the LCMODE control bit. The user can select between Limiter mode and three different ALC modes using the LCSEL control bits. REGISTER ADDRESS BIT LABEL DEFAULT R17 (11h) 0010001 ALC Control 2 LCMODE ALC/Limiter Select 0 = ALC Mode 1 = Limiter Mode R16 (10h) 0010000 ALC Control 1 8:7 LCSEL LC Function Select 00 = Disabled 01 = Right channel only 10 = Left channel only 11 = Stereo Both the ALC and Limiter functions can operate in stereo or single channel modes. In stereo mode, the ALC/Limiter operates on both PGAs. In single channel mode, only one PGA is controlled by the ALC/Limiter mechanism, while the other channel runs independently with its PGA gain set through the control register. When enabled, the threshold for the limiter or target level for the ALC is programmed using the LCT control bits. This allows the threshold/target level to be programmed between -1dB and -16dB in 1dB steps. Note that for the ALC, target levels of -1dB and -2dB give a threshold of -3dB. This is because the ALC can give erroneous operation if the target level is set too high. REGISTER ADDRESS BIT LABEL DEFAULT R16 (10h) 0010000 ALC Control 1 3:0 LCT[3:0] 1110 (-1.5dB) Limiter Threshold/ALC Target Level in 1.5dB Steps: 0000: -22.5dB FS 0001: -21dB FS 1101: -3dB FS 1110: -1.5dB FS 1111: 0dB FS hold time decay time attack time input signal signal after ALC PGA gain ALC target level

w PP Rev 1.0 May 2005 ATTACK AND DECAY TIMES The limiter and ALC have different attack and decay times which determine their operation. However, the attack and decay times are defined slightly differently for the limiter and for the ALC. DCY and ATK control the decay and attack times, respectively. Decay time (Gain Ramp-Up). When in ALC mode, this is defined as the time that it takes for the PGA gain to ramp up across 90% of its range (e.g. from –21dB up to +20 dB). When in limiter mode, it is defined as the time it takes for the gain to ramp up by 6dB. The decay time can be programmed in power-of-two (2n) steps. For the ALC this gives times from to 1.2288s. Attack time (Gain Ramp-Down) When in ALC mode, this is defined as the time that it takes for the PGA gain to ramp down across 90% of its range (e.g. from +20dB down to -21dB gain). When in limiter mode, it is defined as the time it takes for the gain to ramp down by 6dB. The attack time can be programmed in power-of-two (2n) steps, from 8.4ms, 16.8ms, 33.6ms etc. to 8.6s for the ALC and from 250us, 500us, etc. up to 256ms. The time it takes for the recording level to return to its target value or static gain value therefore depends on both the attack/decay time and on the gain adjustment required. If the gain adjustment is small, it will be shorter than the attack/decay time. REGISTER ADDRESS BIT LABEL DEFAULT LC Attack (Gain Ramp-down) Time 3:0 ATK[3:0] 0010 ALC mode 0000: 8.4ms 0001: 16.8ms 0010: 33.6ms… (time doubles with every step) 1010 or higher: 8.6s Limiter Mode 0000: 250us 0001: 500us… 0010: 1ms (time doubles with every step) 1010 or higher: 256ms LC Decay (Gain Ramp-up) Time R18 (12h) 0010010 ALC Control 3 7:4 DCY [3:0] 1001 ALC mode 0000: 33.5ms 0001: 67.2ms 0010: 134.4ms ….(time doubles for every step) 1001: 17.15s 1010 or higher: 34.3s Limiter mode 0000: 1.2ms 0001: 2.4ms 0010: 4.8ms ….(time doubles for every step) 1001: 614.4ms 1010 or higher: 1.2288s ZERO CROSS The PGA has a zero cross detector to prevent gain changes introducing noise to the signal. In ALC mode the register bit ALCZC allows this to be turned off if desired. REGISTER ADDRESS BIT LABEL DEFAULT R17 (11h) 0010001 ALC Control 2 ALCZC (enabled) PGA Zero Cross Enable: 0 : disabled 1: enabled

w PP Rev 1.0 May 2005 MAXIMUM GAIN (ALC ONLY) AND MAXIMUM ATTENUATION To prevent low level signals being amplified too much by the ALC, the MAXGAIN register sets the upper limit for the gain. This prevents low level noise being over-amplified. The MAXGAIN register has no effect on the limiter operation. The MAXATTEN register sets a limit for the amount of attenuation below the static gain level that the limiter can apply. The MAXATTEN register has no effect in ALC mode. REGISTER ADDRESS BIT LABEL DEFAULT R16 (10h) 0010000 ALC Control 1 6:4 MAXGAIN 111 (+24dB) Set Maximum Gain for the PGA (ALC only): 111 : +24dB 110 : +20dB …..(-4dB steps) 010 : +4dB 001 : 0dB 000 : 0dB Maximum Attenuation of PGA (Limiter only) Limiter (attenuation below static) 0000 to 0011 -3dB 0100 -4dB (-1dB steps) 1110 -14dB R20 (14h) 0010100 Limiter Control 3:0 MAXATTEN 0110 (-6dB) 1111 -15dB SOFTWARE REGISTER RESET Writing any value to register 0010111 will cause a register reset, resetting all register bits to their default values.

w PP Rev 1.0 May 2005 REGISTER MAP The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8591 can be configured using the Control Interface. All unused bits should be set to ‘0’. REGISTER B B B B B B B DEFAULT (HEX) R3 (03h)

1 UPDATED

LDA[7:0] 0FF R4 (04h)

0 UPDATED

RDA[7:0] 0FF R5 (05h) MDA[7:0] 0FF R6 (06h) PHASE[1:0] 000 R7 (07h) PL[3:0] TOD IZD ATC DZCEN 090 R9 (09h) ZFLAG POL DMUTE DZFM [1:0] DEEMPH 004 R10 (0Ah) DACOSR DACWL[1:0] DACBCP DACLRP DACFMT[1:0] 022 R11 (0Bh) ADCHPD DACSYNCEN ADCMCLKINV ADCWL[1:0] ADCBCP ADCLRP ADCFMT[1:0] 022 R12 (0Ch) ADCMS DACMS DACRATE[2:0] ADCOSR ADCRATE[2:0] 122 R13 (Odh) DACPD ADCPD PDWN 000 R14 (0Eh) ZCLA LAG[7:0] 0CF R15 (0Fh) ZCRA RAG[7:0] 0CF R16 (10h) LCSEL[1:0] MAXGAIN[2:0] LCT[3:0] 1FE R17 (11h) LCMODE ALCZC 180 R18 (12h) DCY[3:0] ATK[3:0] 092 R20 (14h) MAXATTEN[3:0] 006 R21 (15h) LRBOTH MUTELA MUTERA 000 R23 (17h) SOFTWARE RESET not reset R28 (1Ch)

0 DACMCLK2ADCDACMCLKX2 DACMCLKINV ADCMCLKX2 ADCMCLK2DAC

BCLK_RATE ADCSYNCEN 000

w PP Rev 1.0 May 2005 REGISTER ADDRESS BIT LABEL DEFAULT 7:0 LDA[7:0] 11111111 (0dB) Digital Attenuation Data for Left Channel DACL in 0.5dB Steps R3 (03h) 0000011 Digital Attenuation DACL UPDATED Not latched Controls Simultaneous Update of all Attenuation Latches: 0: Store LDA1 in intermediate latch (no change to output) 1: Store LDA1 and update attenuation on all channels 7:0 RDA[6:0] 11111111 (0dB) Digital Attenuation Data for Right Channel DACR in 0.5dB Steps R4 (04h) 0000100 Digital Attenuation DACR UPDATED Not latched Controls Simultaneous Update of all Attenuation Latches: 0: Store RDA1 in intermediate latch (no change to output) 1: Store RDA1 and update attenuation on all channels 7:0 MDA[7:0] 11111111 (0dB) Digital Attenuation Data for all DAC Channels in 0.5dB Steps R5 (05h) 0000101 Master Digital Attenuation (All Channels) UPDATED Not latched Controls Simultaneous Update of all Attenuation Latches: 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on all channels R6 (06h) 0000110 Phase Swaps 1:0 PHASE Controls Phase of DAC Outputs (LEFT, RIGHT Channel): 0: Sets non inverted output phase 1: inverts phase of DAC output DZCEN DAC Digital Volume Zero Cross Enable: 0: Zero Cross detect disabled 1: Zero Cross detect enabled ATC Attenuator Control: 0: All DACs use attenuations as programmed 1: Right DAC uses left DAC attenuations IZD Infinite Zero Detection Circuit Control and Automute Control: 0: Infinite zero detect automute disabled 1: Infinite zero detect automute enabled TOD DAC and ADC Analogue Zero Cross Detect Timeout Disable: 0 : Timeout enabled 1: Timeout disabled DAC Output Control PL[3:0] Left Output Right Output PL[3:0] Left Output Right Output 0000 Mute Mute 1000 Mute Right 0001 Left Mute 1001 Left Right 0010 Right Mute 1010 Right Right 0011 (L+R)/2 Mute 1011 (L+R)/2 Right 0100 Mute Left 1100 Mute (L+R)/2 0101 Left Left 1101 Left (L+R)/2 0110 Right Left 1110 Right (L+R)/2 R7 (07h) 0000111 DAC Control 7:4 PL[3:0] 1001 0111 (L+R)/2 Left 1111 (L+R)/2 (L+R)/2

w PP Rev 1.0 May 2005 REGISTER ADDRESS BIT LABEL DEFAULT De-emphasis Mode Select: 0 : Normal mode 1: De-emphasis mode DZFM ZFLAG1 ZFLAG2 2:1 DZFM Disabled Left channels zero Both channels zero Either channel zero Disabled Right channels zero Both channels zero Either channel zero DMUTE DAC Channel Soft Mute Enables: 0: Mute disabled 1: Mute enabled ZFLAG polarity ZFLAGPOL ZFLAGL ZFLAGR Pin pulls low to indicate zero condition, high impedance otherwise R9 (09h) 0001001 DAC Control ZFLAGPOL Pin is high impedance when zero condition detected, pulls low otherwise 1:0 DACFMT[1:0] DAC Interface Format Select: 00: Right justified mode 01: Left justified mode 10: I2S mode 11: DSP mode DACLRC Polarity or DSP Early/Late Mode Select DACLRP Left Justified / Right Justified / I2S: 0: Standard DACLRC Polarity 1: Inverted DACLRC Polarity DSP Mode: 0: Early Mode 1: Late Mode DACBCP DAC BITCLK Polarity: 0: Normal – DIN and DACLRC sampled on rising edge of DACBCLK 1: Inverted - DIN and DACLRC sampled on falling edge of DACBCLK 5:4 DACWL[1:0] DAC Input Word Length: 00: 16-bit Mode 01: 20-bit Mode 10: 24-bit Mode 11: 32-bit Mode (not supported in right justified mode) R10 (0Ah) 0001010 DAC Interface Control DACOSR DAC Oversample Rate Select: 0: 128x oversampling 1: 64x oversapmling 1:0 ADCFMT[1:0] ADC Interface Format Select: 00: Right justified mode 01: Left justified mode 10: I2S mode 11: DSP mode ADCLRC Polarity or DSP Early/Late Mode Select R11 (0Bh) 0001011 ADC Interface Control ADCLRP Left Justified / Right Justified / I2S: 0: Standard ADCLRC polarity 1: Inverted ADCLRC polarity DSP Mode: 0: Early mode 1: Late mode

w PP Rev 1.0 May 2005 REGISTER ADDRESS BIT LABEL DEFAULT ADC BITCLK Polarity: 0: Normal – ADCLRC sampled on rising edge of ADCBCLK; DOUT changes on falling edge of ADCBCLK 1: Inverted - ADCLRC sampled on falling edge of ADCBCLK; DOUT changes on rising edge of ADCBCLK 5:4 ADCWL[1:0] ADC Input Word Length: 00: 16-bit mode 01: 20-bit mode 10: 24-bit mode 11: 32-bit mode (not supported in right justified mode) ADCMCLKINV ADCMCLK Polarity: 0: non-inverted 1: inverted DACSYNCEN Enable the DAC Synchronizer: 0: Disabled 1: Enabled ADCHPD ADC High Pass Filter Powerdown: 0: HP Filter Enabled 1: HP Filter Disabled 2:0 ADCRATE[2:0] 010 Master Mode ADCMCLK:ADCLRC Ratio Select: 010: 256fs 011: 384fs 100: 512fs 101: 768fs ADCOSR ADC Oversample Rate Select: 0: 128x oversampling 1: 64x oversampling 6:4 DACRATE[2:0] 010 Master Mode DACMCLK:DACLRC Ratio Select: 000: 128fs 001: 192fs 010: 256fs 011: 384fs 100: 512fs 101: 768fs DACMS DAC Master/Slave Interface Mode Select: 0: Slave Mode – DACLRC and DACBCLK are inputs 1: Master Mode –DACLRC and DACBCLK are outputs R12 (0Ch) 0001100 Master Mode Control ADCMS ADC Master/Slave Interface Mode Select: 0: Slave Mode – ADCLRC and ADCBCLK are inputs 1: Master Mode – ADCLRC and ADCBCLK are outputs PDWN Chip Powerdown Control (works in tandem with ADCPD and DACPD): 0: All circuits running, outputs are active 1: All circuits in power save mode, outputs muted ADCPD ADC Powerdown: 0: ADC enabled 1: ADC disabled R13 (0Dh) 0001101 PWR Down Control DACPD DAC Powerdown: 0: DAC enabled 1: DAC disabled

w PP Rev 1.0 May 2005 REGISTER ADDRESS BIT LABEL DEFAULT 7:0 LAG[7:0] 11001111 (0dB) Attenuation Data for Left Channel ADC Gain in 0.5dB Steps: 00000000 : digital mute 00000001 : -103dB ……….. 11001111 : 0dB ………… 11111110 : +23.5dB 11111111 : +24dB R14 (0Eh) 0001110 Attenuation ADCL ZCLA Left ADC Zero Cross Enable: 0: Zero cross disabled 1: Zero cross enabled 7:0 RAG[7:0] 11001111 (0dB) Attenuation Data for Right Channel ADC Gain in 0.5dB Steps: 00000000 : digital mute 00000001 : -103dB ……….. 11001111 : 0dB ………… 11111110 : +23.5dB 11111111 : +24dB R15 (0Fh) 0001111 Attenuation ADCR ZCRA Right ADC Zero Cross Enable: 0: Zero cross disabled 1: Zero cross enabled 3:0 LCT[3:0] 1110 (-1.5dB) Limiter Threshold/ALC Target Level in 1.5dB Steps: 0000: -22.5dB FS 0001: -21dB FS 1101: -3dB FS 1110: -1.5dB FS 1111: 0dB FS 6:4 MAXGAIN[2:0] 111 (+24dB) Set Maximum Gain of PGA: 111 : +24dB 110 : +20dB ….(-4dB steps) 010 : +4dB 001 : 0dB 000 : 0dB R16 (10h) 0010000 ALC Control 1 8:7 LCSEL[1:0] (Stereo) LC Function Select 00 = Disabled 01 = Right channel only 10 = Left channel only 11 = Stereo ALCZC (zero cross on) ALC Uses Zero Cross Detection Circuit. R17 (11h) 0010001 ALC Control 2 LCMODE ALC/Limiter Select: 0 = ALC Mode 1 = Limiter Mode

w PP Rev 1.0 May 2005 REGISTER ADDRESS BIT LABEL DEFAULT ALC/Limiter Attack (gain ramp-down) Time 3:0 ATK[3:0] 0010 (33.6ms/ 1ms) ALC Mode: 0000: 8.4ms 0001: 16.8ms 0010: 33.6ms… (time doubles with every step) 1010 or higher: 8.6s Limiter Mode: 0000: 250us 0001: 500us… 0010: 1ms (time doubles with every step) 1010 or higher: 256ms ALC/Limiter Decay (gain ramp up) Time R18 (12h) 0011000 ALC Control 3 7:4 DCY[3:0] 1001 (17.15s/ 614.4ms) ALC Mode: 0000: 33.5ms 0001: 67.2ms 0010: 134.4ms ….(time doubles for every step) 1001: 17.15s 1010 or higher: 34.3s Limiter Mode: 0000: 1.2ms 0001: 2.4ms 0010: 4.8ms ….(time doubles for every step) 1001: 614.4ms 1010 or higher: 1.2288s Maximum Attenuation of PGA (Limiter only) Limiter (attenuation below static) 0000 to 0011 -3dB 0100 -4dB (-1dB steps) 1110 -14dB R20 (14h) 0010100 Limiter Control 3:0 MAXATTEN [3:0] 0110 (-6dB) 1111 -15dB MUTERA Mute for Right Channel ADC: 0: Mute off 1: Mute on MUTELA Mute for Left Channel ADC: 0: Mute off 1: Mute on R21 (15h) 0010101 ADC Mux Control LRBOTH Right Channel Input PGA Controlled by Left Channel Register: 0: Right channel uses RAG and MUTERA 1: Right channel uses LAG and MUTELA R23 (17h) 0010111 Software Reset [8:0] RESET Not reset Writing any value to this register will apply a reset to the device registers. ADCSYNCEN Enable the ADC Synchronizer: 0: Disabled 1: Enabled 3:2 BCLK_RATE Set ADCBCLK and DACBCLK output rate in Master Mode: 00: BCLK = MCLK/4 (MCLK in DSP Mode) 01: BCLK = MCLK/4 (MCLK in DSP Mode) 10: BCLK = 64fs 11: BCLK = 128fs ADCMCLK2DAC Set both ADC and DAC to use ADCMCLK: 0: DAC uses DACMCLK 1: DAC uses ADCMCLK R28 (1Ch) 0011100 ADC/DAC Synchronization ADCMCLKX2 Allows DAC synchronizer to synchronize to ADC operating at 2x DAC rate: 0: Disabled 1: Enabled

w PP Rev 1.0 May 2005 REGISTER ADDRESS BIT LABEL DEFAULT DACMCLK Polarity: 0: non-inverted 1: inverted DACMCLKX2 Allows ADC synchronizer to synchronize to DAC operating at 2x ADC rate: 0: Disabled 1: Enabled DACMCLK2ADC Set both DAC and ADC to use DACMCLK: 0: ADC uses ADCMCLK 1: ADC uses DACMCLK

w PP Rev 1.0 May 2005 DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC Filter ±0.01 dB 0.4535fs Passband -6dB 0.5fs Passband ripple ±0.01 dB Stopband 0.5465fs Stopband Attenuation f > 0.5465fs -65 dB Group Delay fs DAC Filter ±0.05 dB 0.454fs Passband -3dB 0.487 fs Passband ripple f < 0.444fs ±0.05 dB Stopband 0.555fs Stopband Attenuation f > 0.555fs -60 dB Group Delay fs Table 13 Digital Filter Characteristics

w PP Rev 1.0 May 2005 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 36 Recommended External Components

w PP Rev 1.0 May 2005 PACKAGE DIMENSIONS NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. DM007.D DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm) Symbols Dimensions (mm) MIN NOM MAX A ----- ----- 2.0 0.05 ----- 0.25 1.65 1.75 1.85 b 0.22 0.30 0.38 c 0.09 ----- 0.25 D 9.90 10.20 10.50 e E 7.40 7.80 8.20 5.00 5.30 5.60 L 0.55 0.75 0.95 θθθθ A A2 E ΘΘΘΘ c L GAUGE PLANE 0.25 e b D SEATING PLANE -C- 0.10 C REF: JEDEC.95, MO-150

0.125 REF

0.65 BSC

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w PP Rev 1.0 May 2005 IMPORTANT NOTICE Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s approval, license, warranty or endorsement thereof. Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. ADDRESS: Wolfson Microelectronics plc Westfield House

26 Westfield Road

Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com