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w WM8533 24-bit 192kHz Stereo DAC with 2Vrms Ground Referenced Line Output WOLFSON MICROELECTRONICS plc Production Data, July 2012, Rev 4.0 To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews Copyright 2012 Wolfson Microelectronics plc
DESCRIPTION
The WM8533 is a stereo DAC with integral charge pump and software control interface. Th is provides 2Vrms line driver outputs using a 3.3V power supply rail. The device features ground-referenced outputs and the use of a DC servo to eliminate t he need for line driving coupling capacitors and effectively eliminate power on pops and clicks. The device is controlled and configured either via the I2C/SPI compliant serial control interface or a hardware control interface. The device supports all common audio sampling rates between 8kHz and 192kHz using all common MCLK / fs ratios. Master and slave modes are available and de- emphasis is also supported. The WM8533 has a 1.8 to 3.3V tolerant digital interface, allowing logic up to 3.3V to be connected. The device is available in a 1.842 x 1.772mm 20-ball WCSP.
FEATURES
High performance stereo DAC with ground referenced line driver Audio performance 106dB SNR (‘A-weighted’) -89dB THD @ -1dBFS Digital volume control ranging from -100dB to +12dB 120dB mute attenuation All common sample rates from 8kHz to 192kHz supported I C/SPI compatible and hardware control modes Data formats: LJ, RJ, I S, DSP De-emphasis supported Maximum 1mV DC offset on line outputs Pop/click suppressed power up/down sequencer AVDD and LINEVDD +3.3V ±10% allowing single supply DBVDD supply supports +1.8V or +3.3V digital I/O 1.842 x 1.772mm 20-ball WCSP
APPLICATIONS
Consumer digital audio applic ations requiring 2Vrms output Set Top Box Digital TV DVD Players Games Consoles A/V Receivers BLOCK DIAGRAM LRCLK DACDAT LINEOUTL LINEOUTR DIGITAL AUDIO INTERFACE DIGITAL FILTERS CONTROL INTERFACE LEFT DAC RIGHT DAC WM8533 BCLK MCLK CHARGE PUMP W LINEREF
w PD, July 2012, Rev 4.0 TABLE OF CONTENTS
w PD, July 2012, Rev 4.0 PIN CONFIGURATION DACDAT DBVDDBCLKMCLK LINEGND CPCA LINEVDD CS/MUTE LINEOUTR AGND AVDD CPCBLINEOUTL CPVOUTN VMID A B C D 1234 5 LINEREF SCLK/ AIFMODE1 CIFMODESDA/ AIFMODE0 LRCLK
ORDERING INFORMATION
o C 20-ball W-CSP (Pb-free, tape and reel) MSL1 260 o C Note: Reel quantity = 5000
w PD, July 2012, Rev 4.0 PIN DESCRIPTION PIN NO NAME TYPE DESCRIPTION A1 AVDD Supply Analogue supply A2 LINEOUTR Analogue Out Right line output A3 LINEOUTL Analogue Out Left line output A4 CPVOUTN Analogue Out Charge pump negative rail decoupling pin A5 CPCB Analogue Out Charge pump fly back capacitor pin B1 AGND Supply Analogue ground B2 LINEREF Analogue Input Ground feedback from output jack B3 VMID Analogue Out Analogue midrail decoupling pin B4 LINEGND Supply Charge pump ground B5 CPCA Analogue Out Charge pump fly back capacitor pin I2C SOFTWARE MODE SPI SOFTWARE MODE HARDWARE MODE C1 SCLK/ AIFMODE1 Digital I/O I C control interface clock input pin SPI control interface clock input pin AIFMODE [1:0] 00 = 24-bit LJ 01 = 24-bit I2S 10 = 16-bit RJ 11 = 24-bit RJ C2 SDA/ AIFMODE0 Digital I/O I C interface data input pin SPI control interface data input pin C3 CIFMODE Digital In Tri-Level 0 = select I C control interface mode 1 = select SPI control interface mode Z = select hardware mode C4 DACDAT Digital In Digital audio interface data input C5 LINEVDD Supply Charge pump supply I C address select: 0 = 0x34 1 = 0x36 SPI control interface chip select 0 = Mute enabled 1 = Mute disabled D2 MCLK Digital In Master clock D3 BCLK Digital I/O Digital audio interface bit clock D4 LRCLK Digital I/O Digital audio interface left/right clock D5 DBVDD Supply Digital interface supply (for digital audio and I2C interfaces) Note: Tri-level pins which require the ‘Z’ state to be selected should be left floating (open)
w PD, July 2012, Rev 4.0 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactur ed on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD- 020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION MIN MAX AVDD, LINEVDD, DBVDD -0.3V +4.5V Voltage range digital inputs AGND -0.3V DBVDD +0.3V Voltage range analogue inputs AGND -0.3V AVDD +0.3V Temperature range, TA -40°C +85°C Storage temperature after soldering -65°C +150°C RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue supply range AVDD, LINEVDD 2.97 3.3 3.63 V Digital buffer supply range DBVDD 1.62 3.63 V Ground AGND, LINEGND 0 V Notes 1. Analogue grounds must always be within 0.3V of each other. 2. LINEVDD and AVDD must always be within 0.3V of each other.
w PD, July 2012, Rev 4.0
ELECTRICAL CHARACTERISTICS
LINEVDD=AVDD=3.3V, DBVDD=1.8V, LINEGND=AGND=0V, TA=+25ºC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue Output Output Level 0dBFS 1.89 2.1 2.31 Vrms Load Impedance 1 k Ω Load Capacitance No external RC filter 300 pF With filter shown in Figure 36 1 µF DAC Performance Signal to Noise Ratio SNR R L = 10kΩ A-weighted 100 106 dB RL = 10kΩ Un-weighted 104 dB Dynamic Range DNR R L = 10kΩ A-weighted 106 Total Harmonic Distortion THD R L = 10kΩ -1dBFS -89 dB RL = 10kΩ 0dBFS -86 -78 Power Supply Rejection Ratio (AVDD or LINEVDD) PSRR 100Hz 54 dB 1kHz 54 20kHz 50 Channel Separation 1kHz 95 dB 20Hz to 20kHz 72 System Absolute Phase 1kHz 0 Degrees Channel Level Matching 0.1 dB Hardware Mute Attenuation 120 dB Digital Soft Mute Attenuation 100 dB DC Offset at LINEOUTL and LINEOUTR 0 +/-1 mV LINEREF Rejection 1kHz 55 dB 20kHz 37 dB Digital Logic Levels Input HIGH Level VIH 0.7 DBVDD V Input LOW Level VIL 0.3 DBVDD V Output HIGH Level VOH IOH = 1mA 0.9 DBVDD V Output LOW Level VOL IOL = -1mA 0.1 DBVDD V Input Capacitance 10 pF Input Leakage 0 +/-0.9 A
w PD, July 2012, Rev 4.0 TERMINOLOGY 1. Signal-to-Noise Ratio (dB) – SNR is a measure of the difference in level between the maximum theoretical full scale output signal and the output with no input signal applied. 2. Total Harmonic Distortion (dB) – THD is the level of the rms value of the sum of harmonic distortion products relative to the amplitude of the measured output signal. 3. All performance measurements carried out with 20kHz low pa ss filter, and where noted an A-weighted filter. Failure to use such a filter will result in higher THD and lower SNR readi ngs than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 4. Mute Attenuation – This is a measure of the difference in level between the full scale output signal and the output with mute applied. TYPICAL PERFORMANCE TYPICAL POWER CONSUMPTION Test Conditions LINEVDD=AVDD=3.3V, DBVDD=1.8V, LINEGND=AGND=0V, TA=+25°C, Slave Mode, quiescent (no signal) TEST CONDITIONS IAVDD ILINEVDD IDBVDD TOTAL (mA) (mW) (mA) (mW) (mA) (mW) (mA) (mW) Off No clocks applied fs=48kHz, MCLK=256fs fs=96kHz, MCLK=256fs fs=192kHz, MCLK=128fs
w PD, July 2012, Rev 4.0 SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING Figure 1 System Clock Timing Requirements Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT Master Clock Timing Information MCLK cycle time tMCLKY 27 500 ns MCLK high time tMCLKH 11 ns MCLK low time tMCLKL 11 ns MCLK duty cycle (tMCLKH/tMCLKL) 40:60 60:40 %
w PD, July 2012, Rev 4.0 AUDIO INTERFACE TIMING – MASTER MODE Figure 2 Master Mode Digital Audio Data Timing Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information LRCLK propagation delay from BCLK falling edge tDL 4 16 ns DACDAT setup time to BCLK rising edge tDST 22 ns DACDAT hold time from BCLK rising edge tDHT 25 ns Table 1 Master Mode Audio Interface Timing
w PD, July 2012, Rev 4.0 AUDIO INTERFACE TIMING – SLAVE MODE Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 27 ns BCLK pulse width high tBCH 11 ns BCLK pulse width low tBCL 11 ns LRCLK set-up time to BCLK rising edge tLRSU 7 ns LRCLK hold time from BCLK rising edge tLRH 5 ns DACDAT hold time from BCLK rising edge tDH 5 ns DACDAT set-up time to BCLK rising edge tDS 7 ns Table 2 Slave Mode Audio Interface Timing Note: BCLK period should always be greater than or equal to MCLK period.
w PD, July 2012, Rev 4.0 CONTROL INTERFACE TIMING – I2C MODE I C mode is selected by driving the CIFMODE pin low. Figure 4 Control Interface Timing – I C Control Mode Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK Frequency 400 kHz SCLK Low Pulse-Width t1 100 ns SCLK High Pulse-Width t2 100 ns Hold Time (Start Condition) t3 600 ns Setup Time (Start Condition) t4 600 ns Data Setup Time t5 100 ns SDA, SCLK Rise Time (see Note) t6 300 ns SDA, SCLK Fall Time t7 300 ns Setup Time (Stop Condition) t8 600 ns Data Hold Time t9 900 ns Pulse width of spikes that will be suppressed 2 8 ns Table 3 Control Interface Timing – I C Control Mode Note: When SCLK frequency ≤ 100kHz, the maximum rise time for SDA and SCLK is increased to 1000ns.
w PD, July 2012, Rev 4.0 CONTROL INTERFACE TIMING – SPI MODE SPI mode is selected by connecting the CIFMODE pin high. Figure 5 Control Interface Timing – SPI Control Mode Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CS¯¯ falling edge tCSU 40 ns SCLK falling edge to CS¯¯ rising edge tCHO 40 ns SCLK pulse cycle time tSCY 160 ns SCLK pulse width low tSCL 64 ns SCLK pulse width high tSCH 64 ns SDA to SCLK set-up time tDSU 20 ns SDA to SCLK hold time tDHO 40 ns Pulse width of spikes that will be suppressed tps 2 8 ns Table 4 Control Interface Timing –SPI Control Mode
w PD, July 2012, Rev 4.0 Test Conditions LINEVDD = AVDD = 3.3V, DBVDD = 1.8V, AGND = LINEGND = 0V, TA = +25ºC PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Power Supply Input Timing Information VDD level to POR defined (LINEVDD/AVDD rising) Vpora Measured from LINEGND 158 mV VDD level to POR rising edge (VMID rising) Vpord_hi Measured from LINEGND 0.63 0.8 1 V VDD level to POR rising edge (LINEVDD/AVDD rising) Vpora_hi Measured from LINEGND 1.44 1.8 2.18 V VDD level to POR falling edge (LINEVDD/AVDD falling) Vpora_lo Measured from LINEGND 0.96 1.46 1.97 V Table 5 Power on Reset Note: All values are simulated results
w PD, July 2012, Rev 4.0 DEVICE DESCRIPTION INTRODUCTION The WM8533 provides high fidelity, 2V rms ground referenced stereo line output from a single supply line with minimal external components. The int egrated DC servo eliminates the requirement for external mute circuitry by mini mising DC transients at the output during power up/down. The device is well-suited to both stereo and multi-channel systems. The device supports all common audio sampli ng rates between 8kHz and 192kHz using common MCLK / fs ratios. Master and slave modes are available. The WM8533 supports both hardware and software control modes. In hardware control mode, the digital audio interface format is switchable between 16 to 24bits LJ, RJ and I S, and a mute control pin is also available. In software control modes, the digital audio interface is fully programmable, with two control interface addresses to allow multiple WM8533 devices to be configured independently. SOFTWARE CONTROL INTERFACE Software control mode is selected by logic 1 or 0 on the CIFMODE pin. The logic level is referenced to the DBVDD power domain. When software mode is selected, the associated multi-function control pins are defined as described in Table 6. PIN NAME PIN REF CS¯¯ D1 I C Mode - Device Address SPI Mode - Chip Select CIFMODE C3 Control Interface Mode 0 = I C Mode 1 = SPI Mode Z = Hardware Mode Table 6 Software Control Pin Configuration In software control mode, the WM8533 is controlled by writing to its control registers. Readback is available for all registers, including device ID and power management status bits, in I C control mode only. The control interface can operate as an I C or SPI control interface: register read-back is provided on the bi-directional pin SDA in I C mode. Note that Readback is not available in SPI mode. The WM8533 software control interface is supplied by the DBVDD power domain. The available software control interface modes are summarised as follows: I C mode uses pins SCLK and SDA. SPI mode uses pins CS ¯¯ , SCLK and SDA. I C mode is selected by setting the CIFMODE pin to logic 0. SPI mode is selected by setting the CIFMODE pin to logic 1.
w PD, July 2012, Rev 4.0 REGISTER RESET Any write to register R0 (00h) will reset the WM8533. All register bits are reset to their default values. CHIP ID AND REVISION Reading from register R0 (00h) returns the Chip ID. Reading from register R1 returns the Chip revision number. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R0 (00h) DEVICE_ID 15:0 CHIP_ID [15:0] 8523h Chip ID Writing to this register resets all registers to their default state. Reading from this register will indicate the Chip ID 8523h. R1 (01h) REVISION 2:0 CHIP_REV [2:0]
001 Chip Revision
Indicates the Chip Revision number Table 8 Chip ID and Revision Number
w PD, July 2012, Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3 (03h) AIF_CTRL1
7 AIF_MSTR 0 Master/Slave Select
0 = Slave 1 = Master R4 (04h) AIF_CTRL2 5:3 AIF_BCLKD IV [2:0]
000 BCLK Divider Control (Master Mode)
000 = MCLK/4 001 = MCLK/8 010 = 32fs 011 = 64fs 100 = 128fs 101 to 111 = Reserved 2:0 AIF_SR [2:0]
000 MCLK:LRCLK Ratio
000 = Auto detect 001 = 128fs 010 = 192fs 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = 1152fs Table 9 DAC Clocking Mode Control Interface timing is such that the input data and left/right clock are sampled on the rising edge of BCLK. By setting the appropriate BCLK and LRCLK polarity bits, the WM8533 DAC can sample data on the opposite clock edges. The control of audio interface formats and clock polarities is summarised in Table 10. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3 (03h) AIF_CTRL1
6 AIF_LRCLK
_INV
0 LRCLK Inversion Control
0 = Normal polarity 1 = Inverted polarity When AIF_FMT [1:0]=11 (DSP Mode): 0 = Mode A (2nd clock) 1 = Mode B (1st clock)
5 AIF_BCLK_
0 BCLK Inversion Control
Slave mode: 0 = use rising edge 1 = use falling edge Master mode: 0 = BCLK normal 1 = BCLK inverted 4:3 AIF_WL [1:0]
10 Audio Data Word Length
00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits 1:0 AIF_FMT [1:0]
10 Audio Data Interface Format
00 = Right justified 01 = Left justified 10 = I2S format 11 = DSP mode Table 10 Audio Interface Control
w PD, July 2012, Rev 4.0 DIGITAL AUDIO DATA SAMPLING RATES The external master clock is applied directly to the MCLK input pin. In a system where there are a number of possible sources for the reference clock, it is recommended that the clock source with the lowest jitter be used for the master clock to optimise the performance of the WM8533. In slave mode the WM8533 has a det ection circuit that automatica lly determines the relationship between the master clock frequency (MCLK) and the sampling rate (LRCLK), to within ±32 system clock periods. The MCLK must be synchronised with the LRCLK, although the device is tolerant of phase variations or jitter on the MCLK. If the device is configured in slav e mode using auto-detect or in hardware mode, and during sample rate change the ratio between MCLK and LRCLK vari es more than once within 1026 LRCLK periods, then it is recommended that the device be taken into the standby state or the off state before the sample rate change and held in standby until the sample rate change is complete. This will ensure correct operation of the detection circuit on the retu rn to the enabled state. For details on the standby state, please refer to the “Software Control Interface” (software mode, page 15) and “Power Up and Down Control In Hardware Mode” sections of the datasheet (hardware mode, on page 29). The DAC supports MCLK to LRCLK ratios of 128fs to 1152fs and sampling rates of 8kHz to 192kHz, provided the internal signal processing of the DAC is programmed to operate at the correct rate. Table 11 shows typical master clock frequencies and sampling rates supported by the WM8533 DAC. SAMPLE RATE (LRCLK) MASTER CLOCK (MCLK) FREQUENCY (MHz) 128fs 192fs 256fs 384fs 512fs 768fs 1152fs 48kHz Unavailable Unavailable 12.288 18.432 24.576 36.864 Unavailable 96kHz 12.288 18.432 24.576 36.864 Unava ilable Unavailable Unavailable 176.4kHz 22.5792 33.8688 Unavailable Unavailable Unavailable Unava ilable Unavailable 192kHz 24.576 36.864 Unavailable Unavailable Unavailable Unava ilable Unavailable Table 11 MCLK Frequencies and Audio Sample Rates
w PD, July 2012, Rev 4.0 DAC FEATURES SYSTEM ENABLE The WM8533 includes a number of enable and dis able mechanisms to allow the device to be powered on and off in a pop-free manner. The SYS_ENA [1:0] control bits enable the DAC and analogue paths. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R2 (02h) PSCTRL1 1:0 SYS_ENA [1:0]
00 System Power Control
00 = Off 01 = Power down 10 = Power up (Digital Soft Mute) 11 = Power up (un-muted) Table 12 System Enable Control Note: MCLK must be present at all times when using the SYS_ENA [1:0] bits. If MCLK is stopped at any point the device will power down to the ‘off’ state, but all register settings will remain. Restarting MCLK will start the device internal power sequence and the device will return to the power state set by the SYS_ENA [1:0] bits. The power up and power down sequences are summaris ed in Figure 22. There is no requirement to manually cycle the device through the sequence via register writes, as the device will always automatically step through each stage in the sequence. Power Up When SYS_ENA [1:0]=00, the internal clocks are stopped and all analogue and digital blocks are disabled for maximum power saving. The device star ts up in this state in software mode. Setting SYS_ENA [1:0]=01 enables the internal charge pump and required control circ uitry, but the signal path remains powered down. When SYS_ENA [1:0]=10 all blocks are powered up sequentially and full system configuration is achieved. Once this is complete, the device is ready to pass audio but is muted with a digital soft mute. Setting SYS_ENA [1:0]=11 releases the digital soft mute and audio playback begins. Power Down When SYS_ENA [1:0]=11 the device is power ed up and passing audio. Changing SYS_ENA [1:0]=10 applies a digital soft mute to the output, with attenuation of 100dB on the input signal. Setting SYS_ENA [1:0]=01 sequentially powers down all circuit blocks but leaves the charge pump and required control circuitry enabled. This state is equivalent to the Hardware Mode mute state, and will give 120dB attenuation on the input signal. This can be considered the low-power standby state. Finally, setting SYS_ENA [1:0]=00 will disable al l circuit blocks including the charge pump, and full system initialisation will be required to restart the device. Figure 22 SYS_ENA [1:0] Power Up and Down Sequences
w PD, July 2012, Rev 4.0 DIGITAL VOLUME CONTROL The WM8533 DAC includes digital volume control, allowing the digital gain to be adjusted between −100dB and +12dB in 0.25dB steps. Volume update bits allow the user to write both left and right channel volume changes before the volume is updated. Note that digital volume control is only available in I C mode. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R6 (06h) DAC_GAINL
9 DACL_VU 0 DAC Digital Volume Update
0 = Latch DAC volume setting into Register Map but do not update volume 1 = Latch DAC volume setting into Register Map and update left and right channels simultaneously R7 (07h) DAC_GAINR
9 DACR_VU 0
R6 (06h) DAC_GAINL 8:0 DACL_VOL [8:0] 190h DAC Digital Volume 000h = −100dB 001h = −99.75dB 002h = −99.5dB …0.25dB steps 190h = 0dB …0.25dB steps 1BEh = +11.75dB 1BFh to 1FFh = +12dB R7 (07h) DAC_GAINR 8:0 DACR_VOL [8:0] 190h Table 13 DAC Digital Volume Control VOLUME CHANGE MODES Volume can be adjusted by step change (either using zero cross or not) or by soft ramp. The volume change mode is controlled by the DAC_VOL_DOWN_RAMP and DAC_VOL_UP_RAMP bits in R5: REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R5 (05h) DAC_CTRL3
1 DAC_VOL
_UP_RAM P
0 DAC Digital Volume Increase Control
0 = Apply volume increases instantly (step) 1 = Ramp volume increases
0 DAC_VOL
_DOWN_ RAMP
1 DAC Digital Volume Decrease Control
0 = Apply volume decreases instantly (step) 1 = Ramp volume decreases Table 14 Volume Ramp Control
w PD, July 2012, Rev 4.0 The effect of the volume ramp is illustrated in Figure 23. Figure 23 Volume Ramp Functionality Ramp Volume Changes If ramp volume changes are selected, the ramp rate is dependent upon the sampling rate. The ramp rates for common audio sample rates are shown in Table 15. SAMPLE RATE FOR DAC (kHz) GAIN RAMP RATE (ms/dB) 8 1 32 0.25 44.1 0.18 48 0.17 88.2 0.1 96 0.08 176.4 0.05 192 0.04 Table 15 Volume Ramp Rate For example, when using a sample rate of 48kHz, the time taken for a volume change from an initial setting of 0dB to -20dB is calculated as follows: Volume Change (dB) x Volume Ramp Rate (ms/dB) = 20 x 0.17 = 3.4ms Zero cross is not used when ramping. The volume level in the DAC is set by the user in 0.25dB increments, but during the volume ramp increments of 0.125dB are actually used. This step size is inaudible and means there is no requirement to wait until a zero crossing occurs. Another benefit of not using zero cross when ramping is that predi ctable ramp times are produced – there is no signal dependency on the ramp time.
w PD, July 2012, Rev 4.0 Step Volume Changes and Zero Cross The step volume control includes optional zero cro ss functionality. When zero cross is enabled, by setting DAC_ZC=1, volume changes are not applied unt il the signal crosses zero so no discontinuity is seen in the output signal. Zero cross helps to prevent pop and click noise when changing volume settings and is therefore recommended if using step volume changes. The zero cross function includes a timeout which fo rces volume changes if a zero cross event does not occur. The timeout period is 14400 samples, equivalent to 300ms at 48kHz sample rate. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R5 (05h) DAC_CTRL3
4 DAC_ZC 0 Zero Cross Enable
0 = Do not use zero cross 1 = Use zero cross Table 16 Zero Cross Control Table 17 gives a summary of the volume mode settings and their effect. DAC_VOL_ UP_RAMP DAC_VOL_ DOWN_RAMP DAC_ZC VOLUME CHANGE UP VOLUME CHANGE DOWN 0 0 0 Step, no zero cross Step, no zero cross 0 1 0 Step, no zero cross Ramp 1 0 0 Ramp Step, no zero cross 1 1 0 Ramp Ramp 0 0 1 Step, use zero cross Step, use zero cross 0 1 1 Step, use zero cross Ramp 1 0 1 Ramp Step, use zero cross 1 1 1 Ramp Ramp Table 17 Volume Change Summary MUTE A digital mute can be applied to left and right channels independently. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R5 (05h) DAC_CTRL3
3 DACR_MU
0 Right DAC Mute
0 = Normal operation 1 = Mute
2 DACL_MUT
E
0 Left DAC Mute
0 = Normal operation 1 = Mute Table 18 DAC Mute Control The DAC mute function in software mode is controlled by the register settings DAC_VOL_UP_RAMP, DAC_VOL_DOWN_RAMP and DAC_ZC as described in Table 17.
w PD, July 2012, Rev 4.0 DIGITAL MONOMIX CONTROL The DAC can be set to output a range of mono and stereo options using DAC_OP_MUX [1:0]. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4 (04h) AIF_CTRL2 7:6 DAC_OP_ MUX [1:0]
00 DAC Digital Monomix
00 = Stereo (Normal Operation) 01 = Mono (Left data to DACR) 10 = Mono (Right data to DACL) 11 = Digital Monomix, (L+R)/2 Table 19 Digital Monomix Control DE-EMPHASIS A digital de-emphasis filter may be applied to the DAC output when the sampling frequency is 44.1kHz. Operation at 48kHz and 32k Hz is also possible, but with an increase in the error from the ideal response. Details of the de-emphasis filter characteristic for 32kHz, 44.1kHz and 48kHz can be seen in Figure 29 to Figure 34. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3 (03h) AIF_CTRL1
8 DAC_DEE
0 DAC De-emphasis
0 = No de-emphasis 1 = Apply de-emphasis Table 20 De-emphasis Control HARDWARE CONTROL INTERFACE The WM8533 can be controlled in hardware mode or in software modes. In hardware mode, the device is configured according to logic levels applied to hardware pins. Hardware control mode is selected by leaving CIFMODE pin open-circuit (high-impedance). When hardware mode is selected, the associated multi-f unction control pins are defined as described in Table 21. PIN NAME DESCRIPTION AIFMODE0 / AIFMODE1 AIFMODE1 AIFMODE0 FORMAT 24-bit Left Justified 24-bit I S 16-bit Right Justified 24-bit Right Justified 0 = Mute 1 = Normal operation CIFMODE Control Interface Mode 0 = I C Mode 1 = SPI Mode Z = Hardware Mode Table 21 Hardware Control Pin Configuration MUTE In hardware mode, the MUTE¯¯¯¯¯ pin controls the DAC mute to both left and right channels. When the mute is asserted a softmute is applied to ramp the signal down, with the ramp rate related to the sample rate as defined in Table 15 on page 26. When the mute is de-asserted the DAC output returns to normal in one step.
w PD, July 2012, Rev 4.0 POWER UP AND DOWN CONTROL IN HARDWARE MODE In hardware mode the MCLK, BCLK and MUTE¯¯¯¯¯ pins are monitored to control how the device powers up or down, and this is summarised in Figure 24 below. Figure 24 Hardware Power Sequence Diagram Off to Enable To power up the device to enabled, start MCLK and BCLK and set MUTE¯¯¯¯¯ = 1. Off to Standby To power up the device to standby, start MCLK and BCLK and set MUTE¯¯¯¯¯ = 0. Once the device is in standby mode, BCLK can be disabled and the device will remain in standby mode. Standby to Enable To transition from the standby state to the enabled state, set the MUTE¯¯¯¯¯ pin to logic 1 and start BCLK. Enable to Standby To power down to a standby state leaving the charge pump running, either set the MUTE¯¯¯¯¯ pin to logic 0 or stop BCLK. MCLK must continue to run in th ese situations. The device will automatically mute and power down quietly in either case. Note: It is recommended that the device is placed in standby mode before sample rate change if the sample rate changes more than once in 1026 LRCLK periods, as detailed in “Digital Audio Data Sampling Rates” on page 23. Enable to Off To power down the device completely, stop MCLK at any time. It is recommended that the device is placed into standby mode as described above before stopping MCLK to allow a quiet shutdown. For the timing of the off state to enabled state transition (power on to audio out timing), and the enabled state to standby state transition (the shutdown timing), please refer to WTN0302.
w PD, July 2012, Rev 4.0 REGISTER MAP The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8533 can be configured using the Control Interface. All unused bits should be set to '0' and access to unlisted registers should be avoided. REG NAME 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEFAULT R0 (0h) DEVICE_ID / SW RESET CHIP_ID [15:0] 8523h R1 (1h) REVISION 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIP_REV [2:0] 0001h R2 (2h) PSCTRL1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYS_ENA [1:0] 0000h R3 (3h) AIF_CTRL1 0 0 0 0 0 0 0 DAC_ DEEM P AIF_M STR AIF_L RCLK_ INV AIF_B CLK_I NV AIF_WL [1:0] 0 AIF_FMT [1:0] 1812h R4 (4h) AIF_CTRL2 0 0 0 0 0 0 0 0 DAC_OP_MUX [1:0] AIF_BCLKDIV [2:0] AIF_SR [2:0] 0000h R5 (5h) DAC_CTRL3 0 0 0 0 0 0 0 0 0 0 0 DAC_ ZC DACR _MUT E DACL_ MUTE DAC_ VOL_ UP_R AMP DAC_ VOL_D OWN_ RAMP 0001h R6 (6h) DAC_GAINL 0 0 0 0 0 0 DACL_ VU DACL_VOL [8:0] 0190h R7 (7h) DAC_GAINR 0 0 0 0 0 0 DACR _VU DACR_VOL [8:0] 0190h Table 22 Register Map
w PD, July 2012, Rev 4.0 REGISTER BITS BY ADDRESS REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R0 (00h) DEVICE_ID/ SW RESET 15:0 CHIP_ID [15:0] 1000_0101_0010_0011 Chip ID Writing to this register resets all registers to their default state. Reading from this register will indicate the Chip ID 8523h. Page 18 Register 00h DEVICE_ID / SW RESET REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R1 (01h) REVISION 2:0 CHIP_REV [2:0] 001 Chip Revision Indicates the Chip Revision number Page 18 Register 01h REVISION REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R2 (02h) PSCTRL1 1:0 SYS_ENA [1:0] 00 System Power Control 00 = Off 01 = Power down 10 = Power up (muted) 11 = Power up (unmuted) Page 24 Register 02h PSCTRL1
w PD, July 2012, Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R3 (03h) AIF_CTRL1
8 DAC_DEEMP 0 DAC De-emphasis Control
0 = No de-emphasis 1 = De-emphasis enabled Page 28 0 = Slave mode 1 = Master mode Page 21
6 AIF_LRCLK_INV 0 LRCLK Inversion Control
0 = Normal polarity 1 = Inverted polarity When AIF_FMT [1:0]=11 (DSP Mode): 0 = Mode A (2nd clock) 1 = Mode B (1st clock) Page 21
5 AIF_BCLK_INV 0 BCLK Inversion Control
Slave mode: 0 = Use rising edge 1 = Use falling edge Master mode: 0 = BCLK normal 1 = BCLK inverted Page 21 4:3 AIF_WL [1:0] 10 Audio Data Word Length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits Page 21
2 Reserved 0 Reserved
2:0 AIF_FMT [1:0] 10 Audio Data Interface Format 00 = Right justified 01 = Left justified 10 = I S format 11 = DSP mode Page 21 Register 03h AIF_CTRL1
w PD, July 2012, Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R4 (04h) AIF_CTRL2 7:6 DAC_OP_MUX [1:0]
00 Digital Monomix Control
00 = Stereo (Normal operation) 01 = Mono (Left data to DACR) 10 = Mono (Right data to DACL) 11 = Digital Monomix, (L+R)/2 Page 28 5:3 AIF_BCLKDIV [2:0] 000 = MCLK/4 001 = MCLK/8 010 = 32fs 011 = 64fs 100 = 128fs 101 to 111 = Reserved Page 21 2:0 AIF_SR [2:0] 000 MCLK:LRCLK Ratio 000 = Auto detect 001 = 128fs 010 = 192fs 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = 1152fs Page 21 Register 04h AIF_CTRL2 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R5 (05h) DAC_CTRL3 0 = Do not use zero cross 1 = Use zero cross Page 25
3 DACR_MUTE 0 Right DAC Mute
0 = Normal operation 1 = Mute Page 27
2 DACL_MUTE 0 Left DAC Mute
0 = Normal operation 1 = Mute Page 27
1 DAC_VOL_
UP_RAMP 0 = Apply volume increases instantly (step) 1 = Ramp volume increases Page 25
0 DAC_VOL_
DOWN_RAMP 0 = Apply volume decreases instantly (step) 1 = Ramp volume decreases Page 25 Register 05h DAC_CTRL3
w PD, July 2012, Rev 4.0 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R6 (06h) DAC_GAINL
9 DACL_VU 0 Left DAC Digital Volume Update
0 = Latch Left DAC volume setting into register map but do not update volume 1 = Latch Left DAC volume setting into register map and update left and right channels simultaneously Page 25 8:0 DACL_VOL [8:0] 1_1001_0000 Left DAC Digital Volume Control 000h = -100dB 001h = -99.75dB 002h = -99.5dB …0.25dB steps 190h = 0dB …0.25dB steps 1BEh = +11.75dB 1BFh to 1FFh = +12dB Page 25 Register 06h DAC_GAINL REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO R7 (07h) DAC_GAINR
9 DACR_VU 0 Right DAC Digital Volume Update
0 = Latch Right DAC volume setting into register map but do not update volume 1 = Latch Right DAC volume setting into register map and update left and right channels simultaneously Page 25 8:0 DACR_VOL [8:0] 1_1001_0000 Right DAC Digital Volume Control 000h = -100dB 001h = -99.75dB 002h = -99.5dB …0.25dB steps 190h = 0dB …0.25dB steps 1BEh = +11.75dB 1BFh to 1FFh = +12dB Page 25 Register 07h DAC_GAINR
w PD, July 2012, Rev 4.0 DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC Filter – 256fs to 1152fs Passband 0.1dB 0.454fs Passband Ripple 0.1 dB Stopband 0.546fs Stopband attenuation f > 0.546fs -50 dB Group Delay 14.5fs DAC Filter – 128fs and 192fs Passband 0.1dB 0.247fs Passband Ripple 0.1 dB Stopband 0.753fs Stopband attenuation f > 0.753fs -50 dB Group Delay 6.5fs TERMINOLOGY 1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band) 2. Pass-band Ripple – any variation of the frequency response in the pass-band region
w PD, July 2012, Rev 4.0 RECOMMENDED EXTERNAL COMPONENTS Figure 35 Recommended External Components Notes: 1. Wolfson recommend using a single, common ground plane. Where this is not possible, care should be taken to optimise split ground configuration for audio performance. 2. Charge Pump fly-back capacitor C5 should be placed as close to WM8533 as possible, followed by Charge Pump decoupling capacitor C1, then LINEVDD and VMID decoupling capacitors. 3. Capacitor types should be chosen carefully. Capa citors with very low ESR are recommended for optimum performance.
w PD, July 2012, Rev 4.0 RECOMMENDED ANALOGUE LOW PASS FILTER Figure 36 Recommended Analogue Low Pass Filter (one channel shown) An external single-pole RC filter is recommended if the device is driving a wideband amplifier. Other filter architectures may provide equally good results. The filter shown in Figure 36 has a -3dB cut-off at 105.26kHz and a droop of 0.15dB at 20kHz. The typical output from the WM8533 is 2.1Vrms – when a 10k Ω load is placed at the output of this recommended filter the amplitude across this load is 1.99Vrms. RELEVANT APPLICATION NOTES The following application notes, available from www.wolfsonmicro.com, may provide additional guidance for use of the WM8533. DEVICE PERFORMANCE: WAN0129 – Decoupling and Layout Methodology for Wolfson DACs, ADCs and CODECs WAN0144 – Using Wolfson Audio DACs and CODECs with Noisy Supplies WTN0302 - WM8524 Recommended Power Sequence and Timing (for hardware mode) GENERAL: WAN0108 – Moisture Sensitivity Classification and Plastic IC Packaging WAN0109 – ESD Damage in Integrated Circuits: Causes and Prevention WAN0158 – Lead-Free Solder Profiles for Lead-Free Components WAN0161 – Electronic End-Product Design for ESD
w PD, July 2012, Rev 4.0 PACKAGE DIMENSIONS B: 20 BALL W-CSP PACKAGE 1.842 X 1.772 X 0.451mm BODY, 0.35 mm BALL PITCH CORNER TOP VIEW E D DETAIL 2 DETAIL 2 A Zbbb Z SOLDER BALL A DETAIL 1 D C B e e 15 4 32 h NOTES: 1. PRIMARY DATUM -Z- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 2. THIS DIMENSION INCLUDES STAND-OFF HEIGHT ‘A1’. 3. A1 CORNER IS IDENTIFIED BY INK/LASER MARK ON TOP PACKAGE. 4. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY. 5. ‘e’ REPRESENTS THE BASIC SOLDER BALL GRID PITCH. 6. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 7. FOLLOWS JEDEC DESIGN GUIDE MO-211-C. A1 0.146 D E e
1.400 BSC
1.772 0.2085
1.050 BSC
0.350 BSC
1.842 Dimensions (mm)Symbols MIN NOM MAX NOTE A 0.451 A2 0.266 0.279 0.292 0.4810.421 0.172 0.198 h 0.205 BOTTOM VIEW 0.3485f2 DETAIL 1 DM107.A 1.867 1.797 1.817 1.747 0.221 0.361 0.175 0.235 aaa bbb ccc ddd 0.025 0.060 0.030 0.015 Zccc Zddd M A B Aaaa2 X Baaa2 X A B
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