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w WM8524 24-bit 192kHz Stereo DAC with 2Vrms Ground Referenced Line Output WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews Production Data, October 2011, Rev 4.1 Copyright 2011 Wolfson Microelectronics plc
DESCRIPTION
The WM8524 is a stereo DAC with integral charge pump and hardware control interface. This provides 2Vrms line driver outputs using a single 3.3V power supply rail. The device features ground-referenced outputs and the use of a DC servo to eliminate the need for line driving coupling capacitors and effectively eliminate power on pops and clicks. The device is controlled and configured via a hardware control interface. The device supports all common audio sampling rates between 8kHz and 192kHz using all common MCLK fs rates. The audio interface operates in slave mode. The WM8524 has a 3.3V tolerant digital interface, allowing logic up to 3.3V to be connected. The device is available in a 16-pin TSSOP.
FEATURES
High performance stereo DAC with ground referenced line driver Audio Performance 106dB SNR (‘A-weighted’) -89dB THD @ -1dBFS 120dB mute attenuation All common sample rates from 8kHz to 192kHz supported Hardware control mode Data formats: LJ, RJ, I S Maximum 1mV DC offset on Line Outputs Pop/Click suppressed Power Up/Down Sequencer AVDD and LINEVDD +3.3V ±10% allowing single supply 16-lead TSSOP package Operating temperature range: -40°C to 85°C
APPLICATIONS
Consumer digital audio applications requiring 2Vrms output Games Consoles Set Top Box A/V Receivers DVD Players Digital TV BLOCK DIAGRAM
w PD, Rev 4.1, October 2011 TABLE OF CONTENTS
w PD, Rev 4.1, October 2011 PIN CONFIGURATION
ORDERING INFORMATION
WM8524CGEDT −40°C to +85°C 16 lead TSSOP (Pb-free) MSL1 260 o C WM8524CGEDT/R −40°C to +85°C 16-lead TSSOP (Pb-free, tape and reel) MSL1 260 o C Note: Reel quantity = 2000
w PD, Rev 4.1, October 2011 PIN DESCRIPTION PIN NO NAME TYPE DESCRIPTION
1 LINEVOUTL Analogue Out Left line output
2 CPVOUTN Analogue Out Charge Pump negative rail decoupling pin
3 CPCB Analogue Out Charge Pump fly back capacitor pin
4 LINEGND Supply Charge Pump ground
5 CPCA Analogue Out Charge Pump fly back capacitor pin
6 LINEVDD Supply Charge Pump supply
7 DACDAT Digital In Digital audio interface data input
8 LRCLK Digital In Digital audio interface left/right clock
9 BCLK Digital In Digital audio interface bit clock
10 MCLK Digital In Master clock
11 MUTE ¯¯¯¯¯ Digital In 0 = Mute enabled
1 = Mute disabled
12 AIFMODE
0 = 24-bit Left Justified 1 = 24-bit I S Z = 24-bit Right Justified
13 AGND Supply Analogue ground
14 VMID Analogue Out Analogue midrail decoupling pin
15 AVDD Supply Analogue supply
16 LINEVOUTR Analogue Out Right line output
Note: Tri-level pins which require the ‘Z’ state to be selected should be left floating (open)
w PD, Rev 4.1, October 2011 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION MIN MAX AVDD, LINEVDD -0.3V +4.5V Voltage range digital inputs LINEGND -0.3V LINEVDD +0.3V Voltage range analogue inputs AGND -0.3V AVDD +0.3V Temperature range, TA -40°C +125°C Storage temperature after soldering -65°C +150°C Notes: 1. Analogue grounds must always be within 0.3V of each other. 2. LINEVDD and AVDD must always be within 0.3V of each other. RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue supply range AVDD, LINEVDD 2.97 3.3 3.63 V Ground AGND, LINEGND 0 V
w PD, Rev 4.1, October 2011
ELECTRICAL CHARACTERISTICS
LINEVDD=AVDD=3.3V, LINEGND=AGND=0V, TA=+25 C, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue Output Levels Output Level 0dBFS 1.89 2.1 2.31 Vrms Load Impedance 1 k Ω Load Capacitance No external RC filter 300 pF With filter shown in Figure 16 1 µF DAC Performance Signal to Noise Ratio SNR RL = 10kΩ A-weighted 106 dB RL = 10kΩ Un-weighted 104 dB Dynamic Range DNR RL = 10kΩ A-weighted 104 dB Total Harmonic Distortion THD -1dBFS -89 dB 0dBFS -86 dB AVDD + LINEVDD Power Supply Rejection Ratio PSRR 100Hz 54 dB 1kHz 54 dB 20kHz 50 dB Channel Separation 1kHz 100 dB 20Hz to 20kHz 95 dB System Absolute Phase 0 degrees Channel Level Matching 0.1 dB Mute Attenuation -120 dB DC Offset at LINEVOUTL and LINEVOUTR -1 0 1 mV Digital Logic Levels Input HIGH Level VIH 0.7 LINEVDD V Input LOW Level VIL 0.3 LINEVDD V Input Capacitance 10 pF Input Leakage -0.9 0.9 A TERMINOLOGY 1. Signal-to-Noise Ratio (dB) – SNR is a measure of the difference in level between the maximum theoretical full scale output signal and the output with no input signal applied. 2. Total Harmonic Distortion (dB) – THD is the level of the rm s value of the sum of harmonic distortion products relative to the amplitude of the measured output signal. 3. All performance measurements carried out with 20kHz low pass filter, and where noted an A-weighted filter. Failure to use such a filter will result in higher THD and lower SN R readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 4. Mute Attenuation – This is a measure of the difference in level between the full scale output signal and the output with mute applied.
w PD, Rev 4.1, October 2011 POWER CONSUMPTION MEASUREMENTS Test Conditions LINEVDD=AVDD=3.3V, LINEGND=AGND=0V, TA=+25°C, Slave Mode, quiescent (no signal) TEST CONDITIONS IAVDD (mA) ILINEVDD (mA) TOTAL (mA) Off No clocks applied 0.8 1.1 1.9 fs=48kHz, MCLK=256fs Standby MUTE ¯¯¯¯¯ = 0 0.2 2.2 2.4 Playback MUTE ¯¯¯¯¯ = 1 4.8 6.0 10.8 fs=96kHz, MCLK=256fs Standby MUTE ¯¯¯¯¯ = 0 0.2 2.9 3.1 Playback MUTE ¯¯¯¯¯ = 1 5.5 8.5 14.0 fs=192kHz, MCLK=128fs Standby MUTE ¯¯¯¯¯ = 0 0.2 2.9 3.1 Playback MUTE ¯¯¯¯¯ = 1 5.5 8.5 14.0
w PD, Rev 4.1, October 2011 SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING Figure 1 System Clock Timing Requirements Test Conditions LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, TA=+25°C PARAMETER SYMBOL MIN TYP MAX UNIT Master Clock Timing Information MCLK cycle time tMCLKY 27 500 ns MCLK high time tMCLKH 11 ns MCLK low time tMCLKL 11 ns MCLK duty cycle (tMCLKH/tMCLKL) 40:60 60:40 %
w PD, Rev 4.1, October 2011 AUDIO INTERFACE TIMING – SLAVE MODE BCLK (input) LRCLK (input) DACDAT (input) tDS tDH tLRH tLRSU tBCH tBCL tBCY VIH VIL VIH VIL VIH VIL Figure 2 Digital Audio Data Timing – Slave Mode Test Conditions LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, TA=+25 C, Slave Mode PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 27 ns BCLK pulse width high tBCH 11 ns BCLK pulse width low tBCL 11 ns LRCLK set-up time to BCLK rising edge tLRSU 7 ns LRCLK hold time from BCLK rising edge tLRH 5 ns DACDAT hold time from LRCLK rising edge tDH 5 ns DACDAT set-up time to BCLK rising edge tDS 7 ns Table 1 Slave Mode Audio Interface Timing Note: BCLK period should always be greater than or equal to MCLK period.
w PD, Rev 4.1, October 2011 Test Conditions LINEVDD = AVDD = 3.3V AGND = LINEGND = 0V, TA = +25 o C PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Power Supply Input Timing Information VDD level to POR defined (LINEVDD/AVDD rising) Vpora Measured from LINEGND 158 mV VDD level to POR rising edge (VMID rising) Vpord_hi Measured from LINEGND 0.63 0.8 1 V VDD level to POR rising edge (LINEVDD/AVDD rising) Vpora_hi Measured from LINEGND 1.44 1.8 2.18 V VDD level to POR falling edge (LINEVDD/AVDD falling) Vpora_lo Measured from LINEGND 0.96 1.46 1.97 V Table 2 Power on Reset Note: All values are simulated results
w PD, Rev 4.1, October 2011 DEVICE DESCRIPTION INTRODUCTION The WM8524 provides high fidelity, 2Vrms ground referenced stereo line output from a single supply line with minimal external components. The integrated DC servo eliminates the requirement for external mute circuitry by minimising DC transients at the output during power up/down. The device is well-suited to both stereo and multi-channel systems. The device supports all common audio sampling rates between 8kHz and 192kHz using common MCLK fs rates, with a slave mode audio interface. The WM8524 supports a simple hardware control mode, allowing access to 24-bit LJ, RJ and I2S audio interface formats, as well as a mute contro l. An internal audio interface clock monitor automatically mutes the DAC output if the BCLK is interrupted. DIGITAL AUDIO INTERFACE The digital audio interface is used for inputting audio data to the WM8524. The digital audio interface uses three pins: DACDAT: DAC data input LRCLK: Left/Right data alignment clock BCLK: Bit clock, for synchronisation The WM8524 digital audio interface operates as a slave as shown in Figure 5. Figure 5 Slave Mode INTERFACE FORMATS The WM8524 supports three different audio data formats: Left justified Right justified I S All three of these modes are MSB first. They are described in Audio Data Formats on page 13. Refer to the “Electrical Characteristics” section for timing information.
w PD, Rev 4.1, October 2011 Figure 8 I S Justified Audio Interface (assuming n-bit word length) DIGITAL AUDIO DATA SAMPLING RATES The external master clock is applied directly to the MCLK input pin. In a system where there are a number of possible sources for the reference clock, it is recommended that the clock source with the lowest jitter be used for the master clock to optimise the performance of the WM8524. The WM8524 has a detection circuit that automatically determines the relationship between the master clock frequency (MCLK) and the sampling rate (LRCLK), to within ±32 system clock periods. The MCLK must be synchronised with the LRCLK, although the device is tolerant of phase variations or jitter on the MCLK. If during sample rate change the ratio between MCLK and LRCLK varies more than once within 1026 LRCLK periods, then it is recommended that the device be taken into the standby state or the off state before the sample rate change and held in standby until the sample rate change is complete. This will ensure correct operation of the detection circuit on the return to the enabled state. For details on the standby state, please refer to the Power up and down control section of the datasheet on page 16. The DAC supports MCLK to LRCLK ratios of 128fs to 1152fs and sampling rates of 8kHz to 192kHz. Table 3 shows typical master clock frequencies and sampling rates supported by the WM8524 DAC. Sampling Rate LRCLK MASTER CLOCK FREQUENCY (MHz) 128fs 192fs 256fs 384fs 512fs 768fs 1152fs 48kHz Unavailable Unavailable 12.288 18.432 24.576 36.864 Unavailable 96kHz 12.288 18.432 24.576 36.864 Unavailable Unavailable Unavailable 176.4kHz 22.5792 33.8688 Unavailable Unavailable Unav ailable Unavailable Unavailable 192kHz 24.576 36.864 Unavailable Unavailable Unav ailable Unavailable Unavailable Table 3 MCLK Frequencies and Audio Sample Rates
w PD, Rev 4.1, October 2011 HARDWARE CONTROL INTERFACE The device is configured according to logic levels applied to the hardware control pins as described in Table 4. PIN NAME PIN NUMBER MUTE¯¯¯¯¯ 11 Mute Control 0 = Mute 1 = Normal operation AIFMODE 12 Audio Interface Mode 0 = 24-bit LJ 1 = 24-bit I S Z = 24-bit RJ Table 4 Hardware Control Pin Configuration MUTE The MUTE¯¯¯¯¯ pin controls the DAC mute to both left and right channels. When the mute is asserted a softmute is applied to ramp the signal down in 800 samples. When the mute is de-asserted the signal returns to full scale in one step.
w PD, Rev 4.1, October 2011 POWER UP AND DOWN CONTROL The MCLK, BCLK and MUTE¯¯¯¯¯ pins are monitored to control how the device powers up or down, and this is summarised in Figure 9 below. Off Standby Enabled BCLK Enabled MUTE=1 MUTE=0 BCLK Disabled MCLK Disabled MCLK Enabled BCLK Enabled MUTE=0 MCLK Enabled BCLK Enabled MUTE=1 MCLK Disabled Figure 9 Hardware Power Sequence Diagram Off to Enable To power up the device to enabled, start MCLK and BCLK and set MUTE¯¯¯¯¯ = 1. Off to Standby To power up the device to standby, start MCLK and BCLK and set MUTE¯¯¯¯¯ = 0. Once the device is in standby mode, BCLK can be di sabled and the device will remain in standby mode. Standby to Enable To transition from the standby state to the enabled state, set the MUTE¯¯¯¯¯ pin to logic 1 and start BCLK. Enable to Standby To power down to a standby state leaving the charge pump running, either set the MUTE¯¯¯¯¯ pin to logic 0 or stop BCLK. MCLK must continue to run in these situations. The device will automatically mute and power down quietly in either case. Note: It is recommended that the device is placed in standby mode before sample rate change if the sample rate changes more than once in 1026 LRCLK periods, as detailed in Digital Audio Data Sampling Rates on page 14. Enable to Off To power down the device completely, stop MCLK at any time. It is recommended that the device is placed into standby mode as described above before stopping MCLK to allow a quiet shutdown. For the timing of the off state to enabled state transition (power on to audio out timing), and the enabled state to standby state transition (the shutdown timing), please refer to WTN0302.
w PD, Rev 4.1, October 2011 POWER DOMAINS DAC L/R Line Driver LDODC Servo Charge Pump POR Digital Core Device AGND LINEGND LINEVDDAVDD Supply Rail 2.97V … 3.63V Ground Rail Digital Input Pins Figure 10 Power Domain Diagram POWER DOMAIN NAME BLOCKS USING THIS DOMAIN DOMAIN DESCRIPTION DAC Power Supplies 3.3V ± 10% AVDD Line Driver DAC DC Servo Analogue Supply 3.3V ± 10% LINEVDD Charge Pump Digital LDO Digital Pad buffers Analogue Supply Internally Generated Power Supplies and References 1.65V ± 10% VMID DAC, LDO Ext decoupled resistor string -3.3V ± 10% CPVOUTN Line Driver Charge pump generated voltage Table 5 Power Domains
w PD, Rev 4.1, October 2011 DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC Filter – 256fs to 1152fs Passband 0.1dB 0.454fs Passband Ripple 0.1 dB Stopband 0.546fs Stopband attenuation f > 0.546fs -50 dB Group Delay 10 Fs DAC Filter – 128fs and 192fs Passband 0.1dB 0.247fs Passband Ripple 0.1 dB Stopband 0.753fs Stopband attenuation f > 0.753fs -50 dB Group Delay 10 Fs TERMINOLOGY 1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band) 2. Pass-band Ripple – any variation of the frequency response in the pass-band region
w PD, Rev 4.1, October 2011 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 15 Recommended External Components Notes: 1. Wolfson recommend using a single, common ground plane. Where this is not possible, care should be taken to optimize split ground configuration for audio performance. 2. Charge Pump fly-back capacitor C5 should be placed as close to WM8524 as possible, followed by Charge Pump decoupling capacitor C1, then LINEVDD and VMID decoupling capacitors. See Recommended PCB Layout on p21. 3. Capacitor types should be chosen carefully. Capacitors with very low ESR are recommended for optimum performance.
w PD, Rev 4.1, October 2011 RELEVANT APPLICATION NOTES The following application notes, available from www.wolfsonmicro.com, may provide additional guidance for use of the WM8524. DEVICE PERFORMANCE: WTN0302 – WM8524 Recommended Power Sequence and Timing WAN0129 – Decoupling and Layout Methodology for Wolfson DACs, ADCs and CODECs WAN0144 – Using Wolfson Audio DACs and CODECs with Noisy Supplies GENERAL: WAN0108 – Moisture Sensitivity Classification and Plastic IC Packaging WAN0109 – ESD Damage in Integrated Circuits: Causes and Prevention WAN0158 – Lead-Free Solder Profiles for Lead-Free Components WAN0161 – Electronic End-Product Design for ESD
w PD, Rev 4.1, October 2011 PACKAGE DIMENSIONS NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. DM013.BDT: 16 PIN TSSOP (5.0 x 4.4 x 1.0 mm) Symbols Dimensions (mm) MIN NOM MAX A ----- ----- 1.20 A1 0.05 ----- 0.15 A2 0.80 1.00 1.05 b 0.19 ----- 0.30 c 0.09 ----- 0.20 D 4.90 5.00 5.10 e 0.65 BSC E 6.4 BSC E1 4.30 4.40 4.50 L 0.45 0.60 0.75 0 o ----- 8 o REF: JEDEC.95, MO-153 A A2 A1 c L GAUGE PLANE 0.25 D 916 E1 E eb SEATING PLANE -C- 0.1 C
w PD, Rev 4.1, October 2011 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specific ations in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfs on is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support sy stems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is per missible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other noti ces (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS Wolfson Microelectronics plc Westfield House
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Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: apps@wolfsonmicro.com
w PD, Rev 4.1, October 2011
REVISION HISTORY
DATE REV ORIGINATOR CHANGES 25/10/11 4.1 JMacD Order codes changed from WM8524GEDT and WM8524GEDT/R to WM8524CGEDT and WM8524CGEDT/R to reflect change to copper wire bonding.