DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 27
Technical content
Single Channel 16-bit CIS/CCD AFE with 4-bit Wide Output WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews Production Data, August 2011, Rev 4.1 Copyright 2011 Wolfson Microelectronics plc
DESCRIPTION
The WM8253 is a 16-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors (CIS) at pixel sample rates of up to 6MSPS. The device includes a complete signal processing channel containing Reset Level Clamping, Correlated Double Sampling, Programmable Gain and Offset adjust functions. Internal multiplexers allow fast switching of offset and gain for line-by-line colour processing. The output from this channel is time multiplexed into a high-speed 16-bit Analogue to Digital Converter. The digital output data is available in 4-bit wide multiplexed format. An internal 4-bit DAC is supplied for internal reference level generation. This may be used during CDS to reference CIS signals or during Reset Level Clamping to clamp CCD signals. An external reference level may also be supplied. ADC references are generated internally, ensuring optimum performance from the device. The device uses an analogue supply voltage of 3.3V and a digital interface supply of between 2.5V and 3.3V. The WM8253 typically only consumes 132mW when operating from a single 3.3V supply.
FEATURES
16-bit ADC 6MSPS conversion rate Low power - 132mW typical 3.3V single supply or 3.3V/2.5V dual supply operation Single channel operation Correlated double sampling Programmable gain (8-bit resolution) Programmable offset adjust (8-bit resolution) Programmable clamp voltage 4-bit wide multiplexed data output format Internally generated voltage references 20-lead SSOP package Serial control interface
APPLICATIONS
Flatbed and sheetfeed scanners USB compatible scanners Multi-function peripherals High-performance CCD sensor interface BLOCK DIAGRAM VRLC/VBIAS VSMP MCLK SCK TIMING GENERATION AND CONTROL CL RLC VSRS VRT VRB CDS CONFIGURABLE SERIAL CONTROL INTERFACE 16-BIT ADC AGND2 DGND AVDD OP[0] OP[1] OP[2] OP[3]/SDO VREF/BIAS PGA I/P SIGNAL POLARITY ADJUST DATA I/O PORT DVDD1 WM8253 OFFSET DAC + + MUX MUX RGB RGB RLC DAC VINP SDI SEN AGND1 DVDD2
w PD, Rev 4.1, August 2011 TABLE OF CONTENTS
w PD, Rev 4.1, August 2011 PIN CONFIGURATION
ORDERING INFORMATION
o C 20-lead SSOP (Pb-free, drybagged) MSL3 260 o C WM8253SCDS/RV 0 to 70 o C 20-lead SSOP (Pb-free, drybagged, tape and reel) MSL3 260 o C Note: Reel quantity = 2,000
w PD, Rev 4.1, August 2011 PIN DESCRIPTION PIN NO NAME TYPE DESCRIPTION
1 AGND2 Supply Analogue ground pin (0V)
2 DVDD1 Supply Digital Core supply (3.3V) 3 VSMP Digital input Video sample synchronisation pulse. 4 MCLK Digital input Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or any multiple of 2 thereafter depending on input sample mode). 5 DGND Supply Digital ground (0V). 6 SEN Digital input Enables the serial interface when high. 7 DVDD2 Supply Digital I/O supply (2.5V-3.3V), all digital I/O pins. 8 SDI Digital input Serial data input. 9 SCK Digital input Serial clock. Digital multiplexed output data bus. ADC output data (d15:d0) is available in 4-bit multiplexed format as shown below. A B C D
10 OP[0] Digital output d12 d8 d4 d0
11 OP[1] Digital output d13 d9 d5 d1
12 OP[2] Digital output d14 d10 d6 d2
13 OP[3]/SDO Digital output d15 d11 d7 d3
Alternatively, pin OP[3]/SDO may be used to output register read-back data when address bit 4=1 and SEN has been pulsed high. See Serial Interface description in Device Description section for further details. 14 AVDD Supply Analogue supply (3.3V) 15 AGND1 Supply Analogue ground (0V). 16 VRB Analogue output Lower reference voltage. This pin must be connected to AGND via a decoupling capacitor. 17 VRT Analogue output Upper reference voltage. This pin must be connected to AGND via a decoupling capacitor.
18 NC Not Connected
19 VRLC/VBIAS Analogue I/O Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be connected to AGND via a decoupling capacitor. VRLC can be externally driven if programmed Hi-Z.
20 VINP
Video input pin.
w PD, Rev 4.1, August 2011 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guar anteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION MIN MAX Analogue supply voltage: AVDD GND - 0.3V GND + 4.2V Digital core supply voltage: DVDD1 GND - 0.3V GND + 4.2V Digital IO supply voltage: DVDD2 GND - 0.3V GND + 4.2V Digital ground: DGND GND - 0.3V GND + 0.3V Analogue grounds AGND GND - 0.3V GND + 0.3V Digital inputs, digital outputs and digital I/O pins GND - 0.3V DVDD + 0.3V Analogue input GND - 0.3V AVDD + 0.3V Other pins GND - 0.3V AVDD + 0.3V Operating temperature range: TA 0C +70 C Notes: 1. GND denotes the voltage of any ground pin. 2. AGND and DGND pins are intended to be operated at the same potential. Differential voltages between these pins will degrade performance. 3. AVDD and DVDD1 pins are intended to be operated at the sa me potential. Differential voltages between these pins will degrade performance. RECOMMENDED OPERATING CONDITIONS CONDITION SYMBOL MIN TYP MAX UNITS Operating temperature range TA 0 70 C Analogue supply voltage AVDD 2.97 3.3 3.63 V Digital Core supply voltage DVDD1 2.97 3.3 3.63 V Digital I/O supply voltage DVDD2 2.5 3.3 3.63 V
w PD, Rev 4.1, August 2011
ELECTRICAL CHARACTERISTICS
AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 36MHz, mode 1 unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions) Full-scale input voltage range (see Note 1) Max Gain Min Gain 0.25 2.56 Vp-p Vp-p Input signal limits (see Note 2) VIN 0 AVDD V Full-scale transition error Gain = 0dB; PGA[7:0] = 07(hex) -60 10 +60 mV Zero-scale transition error Gain = 0dB; PGA[7:0] = 07(hex) -50 10 +50 mV Differential non-linearity DNL 2.4 LSB Integral non-linearity INL 17 LSB Input referred noise 12 LSB rms References Upper reference voltage VRT 2.05 V Lower reference voltage VRB 1.05 V Diff. reference voltage (VRT-VRB) VRTB 0.95 1.0 1.05 V Output resistance VRT, VRB, VRX 1 VRLC/Reset-Level Clamp (RLC) RLC switching impedance 20 50 100 VRLC short-circuit current 1. 6 2 4.5 mA VRLC output resistance 2 VRLC Hi-Z leakage current VRLC = 0 to AVDD 1 A RLCDAC resolution 4 bits RLCDAC step size VRLCSTEP RLCDACRNG = 0 0.18 V/step RLCDACRNG = 1 0.123 V/step RLCDAC output voltage at code 0(hex) VRLCBOT RLCDACRNG = 0 0.3 V RLCDACRNG = 1 0.2 V RLCDAC output voltage at code F(hex) VRLCTOP RLCDACRNG = 0 3.0 V RLCDACRNG = 1 2.05 V Offset DAC, Monotonicity Guaranteed Resolution 8 bits Differential non-linearity DNL 0.2 LSB Integral non-linearity INL 0.6 LSB Step size 2.03 mV/step Output voltage Code 00(hex) Code FF(hex) -260 +260 mV mV Notes: 1. Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC input range. 2. Input signal limits are the limits within which the full-scale input voltage signal must lie.
w PD, Rev 4.1, August 2011 Test Conditions AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 36MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Programmable Gain Amplifier Resolution 8 bits Gain equation 255 V/V Max gain GMAX 8.2 8.35 8.8 V/V Min gain GMIN 0.75 0.78 0.87 V/V Internal channel offset VOFF 10 mV Analogue to Digital Converter Resolution 16 bits Maximum Speed 6 M S P S Full-scale input range (2*(VRT-VRB)) VFS 2.0 V DIGITAL SPECIFICATIONS Digital Inputs High level input voltage VIH 0.8 DVDD2 V Low level input voltage VIL 0.2 DVDD2 V High level input current IIH 1 A Low level input current IIL 1 A Input capacitance CI 5 pF Digital Outputs High level output voltage VOH I OH = 1mA DVDD2 - 0.5 V Low level output voltage VOL I OL = 1mA 0.5 V Supply Currents Total supply current active 45.9 mA Total analogue AVDD, supply current active IAVDD 39.6 mA Total digital core, DVDD1, supply current active IDVDD1 3 mA Digital I/O supply current, DVDD2 active (see note 3) IDVDD2 3.3 mA Supply current full power down mode 30 200 A Notes: 1. Digital I/O supply current depends on the capacitive load attached to the pin. The Digital I/O supply current is measured with approximately 50pF attached to the pin.
w PD, Rev 4.1, August 2011 Test Conditions AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 36MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Output propagation delay OPDLY = 00 t PD IOH = 1mA, IOL = 1mA 5 9 13 ns Output propagation delay OPDLY = 01 t PD IOH = 1mA, IOL = 1mA 8 12 16 ns Output propagation delay OPDLY = 10 t PD IOH = 1mA, IOL = 1mA 9 13 17 ns SERIAL INTERFACE SCK SDI SEN SDO tSPER tSCKL tSCKH tSSU tSH tSCE tSEW tSEC tSERD tSCRD MSB LSB tSCRDZ ADC DATA ADC DATA REGISTER DATA Figure 3 Serial Interface Timing Test Conditions AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK =36MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS SCK period tSPER 41.6 ns SCK high tSCKH 18.8 ns SCK low tSCKL 18.8 ns SDI set-up time tSSU 6 ns SDI hold time tSH 6 ns SCK to SEN set-up time tSCE 12 ns SEN to SCK set-up time tSEC 12 ns SEN pulse width tSEW 25 ns SEN low to SDO = Register data tSERD 30 ns SCK low to SDO = Register data tSCRD 30 ns SCK low to SDO = ADC data tSCRDZ 30 ns Note: 1. Parameters are measured at 50% of the rising/falling edge
w PD, Rev 4.1, August 2011 DEVICE DESCRIPTION INTRODUCTION A block diagram of the device showing the signal path is presented on Page 1. The WM8253 processes the sampled video signal on VINP with respect to the video-reset level or an internally/externally generated reference level through the analogue-processing channel. This processing channel consists of an Input Samp ling block with optional Reset Level Clamping (RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and an 8-bit Programmable Gain Amplifier (PGA). The ADC then converts each resulting analogue signal to a 16-bit digital word. The digital output from the ADC is presented on a 4-bit wide bus. On-chip control registers determine the configur ation of the device, including the offsets and gains applied to each channel. These registers are programmable via a serial interface. INPUT SAMPLING The WM8253 has a single analogue processing channel and ADC, which can be used in a flexible manner to process both monochrome and line-by-line colour inputs. Monochrome: The selected input (VINP) is sampled, processed by the analogue channel, and converted by the ADC. The same offset DAC and PGA register values are always applied. Colour Line-by-Line: VINP is sampled and processed by the analogue channel before being converted by the ADC. The gains and offset register values applied to the PGA and offset DAC can be switched between the independent Red, Green and Blue digital registers (e.g. Red Green Blue Red…) at the start of each line in order to facilitate line-by-line colour operation. The INTM[1:0] bits determine which register contents are applied (see Table 1) to the PGA and offset DAC. By using the INTM[1:0] bits to select the desired register values only one register write is required at the start of each new colour line. RESET LEVEL CLAMPING (RLC) To ensure that the signal applied to the WM8253 VINP pin lies within the valid input range (0V to AVDD) the CCD output signal is usually level shifted by coupling through a capacitor, C IN. When active, the RLC circuit clamps the WM8253 side of this capacitor to a suitable voltage during the CCD reset period. The RLCINT register bit controls is used to activate the Reset Level Clamp circuit. A typical input configuration is shown in Figure 4. The Timing Control Block generates a clamp pulse, CL, from MCLK and VSMP (when RLCINT is high). When CL is active the voltage on the WM8253 side of C IN, at VINP, is forced to the VRLC/VBIAS voltage (V VRLC) by switch 1. When the CL pulse turns off, the voltage at VINP initially remains at V VRLC but any subsequent variation in sensor voltage (from reset to video level) will couple through CIN to VINP. RLC is compatible with both CDS and non-CDS operating modes, as selected by switch 2. Refer to the CDS/non-CDS Processing section.
w PD, Rev 4.1, August 2011 CDS/NON-CDS PROCESSING For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel common mode noise. For CDS operation, the video level is processed with respect to the video reset level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must be set to 1 (default), this controls switch 2 (Figure 4) and causes the signal reference to come from the video reset level. The time at which the reset level is sampled, by clock R s/CL, is adjustable by programming control bits CDSREF[1:0], as shown in Figure 6. MCLK VSMP VS RS/CL (CDSREF = 00) RS/CL (CDSREF = 01) RS/CL (CDSREF = 10) RS/CL (CDSREF = 11) Figure 6 Reset Sample and Clamp Timing For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described above. The VRLC/VBIAS pin is sampled by Rs at the same time as Vs samples the video level in this mode. OFFSET ADJUST AND PROGRAMMABLE GAIN The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset can be set for each of three colours by writing to control bits DACx[7:0] and PGAx[7:0] (where x can be R, G or B). In colour line-by-line mode the gain and offset coefficients that are applied to the PGA and offset DAC can be multiplexed by control of the INTM[1:0] bits as shown in Table 1. INTM[1:0] DESCRIPTION
00 Red offset and gain registers are applied to offset DAC and PGA
(DACR[7:0] and PGAR[7:0])
01 Green offset and gain registers applied to offset DAC and PGA
(DACG[7:0] and PGAG[7:0])
10 Blue offset and gain registers applied to offset DAC and PGA
(DACB[7:0] and PGAB[7:0]) 11 Reserved. Table 1 Offset DAC and PGA Register Control The gain characteristic of the WM8253 PGA is shown in Figure 7. Figure 8 shows the maximum input voltage (at VINP) that can be gained up to match the ADC full-scale input range (2.0V).
w PD, Rev 4.1, August 2011 CALCULATING OUTPUT FOR ANY GIVEN INPUT The following equations describe the processing of the video and reset level signals through the WM8253. INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING If CDS = 1, (i.e. CDS operation) the previously sampled reset level, V RESET, is subtracted from the input video. If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted instead. If VRLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS. If VRLCEXT = 0, VVRLC is the output from the internal RLC DAC. VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC. OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST The resultant signal V1 is added to the Offset DAC output. PGA NODE: GAIN ADJUST The signal is then multiplied by the PGA gain, V ADC BLOCK: ANALOGUE-DIGITAL CONVERSION The analogue signal is then converted to a 16-bit unsigned number, with input range configured by PGAFS[1:0]. where the ADC full-scale range, VFS = 2.0V if D1[15:0] > 65535 D1[15:0] = 65535 OUTPUT INVERT BLOCK: POLARITY ADJUST The polarity of the digital output may be inverted by control bit INVOP. D
w PD, Rev 4.1, August 2011 REFERENCES The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins VRT and VRB, where they must be decoupled to ground. The output buffer from the RLCDAC also requires decoupling at pin VRLC/VBIAS when this is configured as an output. POWER SUPPLY The WM8253 runs from a 3.3V single supply. POWER MANAGEMENT Power management for the device is performed via the Control Interface. The device can be powered on or off completely by setting the EN bit low. All the internal registers maintain their previously programmed value in power down mode and the Control Interface inputs remain active. OPERATING MODES Table 3 summarises the most commonly used modes, the clock waveforms required and the register contents required for CDS and non-CDS operation. MODE DESCRIPTION CDS AVAILABLE MAX SAMPLE RATE TIMING REQUIREMENTS REGISTER CONTENTS WITH CDS REGISTER
CONTENTS
1 Monochrome/
Yes 6MSPS MCLK max = 36MHz MCLK:VSMP ratio is 6:1 SetReg1: 03(hex) SetReg1: 01(hex)
2 Fast Monochrome/
Yes 6MSPS MCLK max = 18MHz MCLK:VSMP ratio is 3:1 Identical to Mode 1 plus SetReg3: bits 5:4 must be set to 0(hex) Identical to Mode 1
3 Maximum speed
No 6MSPS MCLK max = 12MHz MCLK:VSMP ratio is 2:1 CDS not possible SetReg1: 41(hex)
4 Slow Monochrome/
Yes 4.5MSPS MCLK max = 36MHz MCLK:VSMP ratio is 2n:1, n 4 Identical to Mode 1 Identical to Mode 1 Table 3 WM8253 Operating Modes
w PD, Rev 4.1, August 2011 OPERATING MODE TIMING DIAGRAMS The following diagrams show 4-bit multiplexed output data and MCLK, VSMP and input video requirements for operation of the most commonly used modes as shown in Table 3. The diagrams are identical for both CDS and non-CDS operation. Note that for extended Mode 4 operation (MCLK:VSMP ratios of 2n:1 where n 4) the latency is given by: Latency (in MCLK periods) = 16.5 + ( n – 4 ) * 2 MCLK VSMP VINP OP[3:0] (DEL = 00) OP[3:0] (DEL = 01) OP[3:0] (DEL = 10) OP[3:0] (DEL = 11)
16.5 MCLK PERIODS
A B C DA B C DA B C DA B C D A B C DA B CA B CA B C D A B C DA B CA B CA B C A B C DA B C DA B C DA B C DA B C D D D DA B C D D D D D Figure 14 Mode 1 Operation ABC ABC ABCD ABC ABC ABC ABC ABC D ABC ABCD ABCD ABC ABC C ABC ABC C ABC ABC C ABC ABC C MCLK VSMP (DEL = 00) VINP OP[3:0] (DEL = 01) OP[3:0] (DEL = 10) OP[3:0] (DEL = 11)
24.5 MCLK PERIODS
OP[3:0] RESET SAMPLE VIDEO SAMPLE RS VS RS VS RS VS RS VS RS VS RS VS D D D DDD ABC ABC ABCD D D D ABCD D ABCDD D D D D D D D D D D D Figure 15 Mode 2 Operation
w PD, Rev 4.1, August 2011 MCLK VSMP VINP OP[3:0] (DEL = 00) OP[3:0] (DEL = 01) OP[3:0] (DEL = 10) OP[3:0] (DEL = 11) A B C D A B C D A B C D A B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C D A B C D A B C D A B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C D A B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C D A B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C D A B C D A B C D A B C D A B C D A B C D A B C DA B C D A B C D Figure 16 Mode 3 Operation OP[3:0] (DEL = 00) OP[3:0] (DEL = 01) OP[3:0] (DEL = 10) OP[3:0] (DEL = 11) A B CA B CA B C D A B CA B C A B C D A B CA B C A B C D A B C A B CA B C A B C D D DD D D D D D D D D D Figure 17 Mode 4 Operation (MCLK:VSMP Ratio = 8:1)
w PD, Rev 4.1, August 2011 DEVICE CONFIGURATION REGISTER MAP The following table describes the location of each control bit used to determine the operation of the WM8253. The register map is programmed by writing the required codes to the appropriate addresses via the serial interface. ADDRESS <a5:a0> DESCRIPTION DEF (hex) RW BIT b7 b6 b5 b4 b3 b2 b1 b0
000001 Setup Reg 1 03 RW 0 MODE3 PGAFS[1] PGAFS[0] 0 0 CDS EN
000010 Setup Reg 2 23 RW DEL[1] DE L[0] RLCDACRNG 0 VRLCEXT INVOP 1 1
000011 Setup Reg 3 1F RW 0 0 CDSREF [1] CDSREF [0] RLCV[3] RLCV[2] RLCV[1] RLCV[0]
000100 Software Reset 00 W
000110 Setup Reg 4 05 RW 0 0 INTM[1] INTM[0] INTRLC 1 0 1
001000 Setup Reg 5 00 RW 0 0 0 POSNNEG VDEL[2] VDEL[1] VDEL[0] VSMPDET
001001 Setup Reg 6 16 RW 0 0 0 OPDLY[1] OPDLY[0] 1 1 0
001010 Reserved 00 RW 0 0 0 0 0 0 0 0
001011 Reserved 00 RW 0 0 0 0 0 0 0 0
001100 Reserved 00 RW 0 0 0 0 0 0 0 0
001101 Reserved 00 RW 0 0 0 0 0 0 0 0
001110 Reserved 00 R 0 0 0 0 0 0 0 0
001111 Reserved 00 R 0 0 0 0 0 0 0 0
100000 DAC Value (Red) 80 RW DACR[7
DACR[6 DACR[5] DACR[4] DACR[3] DACR[2] DACR[1] DACR[0]
100001 DAC Value
(Green)
80 RW DACG[7] DACG[6] DACG[5] DACG[4] DACG[3] DACG[2] DACG[1] DACG[0]
100010 DAC Value (Blue) 80 RW DACB[7] DACB[6] DACB[5] DACB[4] DACB[3] DACB[2] DACB[1] DACB[0]
100011 DAC Value
(RGB)
80 W DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0]
101000 PGA Gain (Red) 00 RW PGAR[7
PGAR[6 PGAR[5] PGAR[4] PGAR[3] PGAR[2] PGAR[1] PGAR[0]
101001 PGA Gain
(Green)
00 RW PGAG[7] PGAG[6] PGAG[5] PGAG[4] PGAG[3] PGAG[2] PGAG[1] PGAG[0]
101010 PGA Gain (Blue) 00 RW PGAB[7] PGAB[6] PGAB[5] PGAB[4] PGAB[3] PGAB[2] PGAB[1] PGAB[0]
101011 PGA Gain (RGB) 00 W PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0]
w PD, Rev 4.1, August 2011 REGISTER MAP DESCRIPTION The following table describes the function of each of the control bits shown in Table 4. REGISTER BIT NO BIT NAME(S) DEFAULT DESCRIPTION Setup Register 1 0 EN 1 0 = complete power down, 1 = fully active.
1 CDS 1 Select correlated double sampling mode: 0 = single ended mode,
1 = CDS mode.
2 Reserved 0 Must be set to zero
3 Reserved 0 Must be set to Zero
5:4 PGAFS[1:0] 00 Offsets PGA output to optimise the ADC range for different polarity sensor output signals. Zero differential PGA input signal gives: 00 = Zero output (use for bipolar video) 01 = Zero output 10 = Full-scale positive output (use for negative going video) 11 = Full-scale negative output (use for positive going video)
6 MODE3 0 This bit must be set when operating in MODE3 (MCLK:VSMP=2:1) 0 =
other modes, 1 = MODE3. NB, when in this mode the CDSREF bits should also be set to 01 to allow clamping to operate correctly.
7 Reserved 0 Must be set to zero
1:0 Reserved 11 Must be set to One 2 INVOP 0 Digitally inverts the polarity of output data. 0 = negative going video gives negative going output, 1 = negative-going video gives positive going output data.
3 VRLCEXT 0 When set powers down the RLCDAC, changing its output to Hi-Z, allowing
VRLC/VBIAS to be externally driven.
4 Reserved 0 Must be set to Zero
5 RLCDACRNG 1 Sets the output range of the RLCDAC. 0 = RLCDAC ranges from 0 to VDD (approximately), 1 = RLCDAC ranges from 0 to VRT (approximately). 7:6 DEL[1:0] 00 Sets the output latency in ADC clock periods.
1 ADC clock period = 2 MCLK periods except in Mode 2 where 1 ADC
clock period = 3 MCLK periods. 00 = Minimum latency 01 = Delay by one ADC clock period 10 = Delay by two ADC clock periods 11 = Delay by three ADC clock periods Setup Register 3 3:0 RLCV[3:0] 1111 Controls RLCDAC driving VRLC pin to define single ended signal reference voltage or Reset Level Clamp voltage. See Electrical Characteristics section for ranges. 5:4 CDSREF[1:0] 01 CDS mode reset timing adjust. 00 = Advance 1 MCLK period 01 = Normal 10 = Retard 1 MCLK period 11 = Retard 2 MCLK periods 7:6 Reserved 00 Must be set to Zero Software Reset Any write to Software Reset causes all cells to be reset. It is recommended that a software reset be performed after a power-up before any other register writes. Setup Register 4 2:0 Reserved 101 Must be set to ‘101’ 3 INTRLC 0 This bit is used to determine whether Reset Level Clamping is enabled. 0 = RLC disabled, 1 = RLC enabled. 5:4 INTM[1:0] 00 Colour selection bits used in internal modes. 00 = Red, 01 = Green, 10 = Blue and 11 = Reserved. See Table 1 for details. 7:6 Reserved 00 Must be set to Zero
w PD, Rev 4.1, August 2011 REGISTER BIT NO BIT NAME(S) DEFAULT DESCRIPTION Setup Register 5
0 VSMPDET 0 0 = Normal operation, signal on VSMP input pin is applied directly to
Timing Control block. 1 = Programmable VSMP detect circuit is enabled. An internal synchronisation pulse is generated from signal applied to VSMP input pin and is applied to Timing Control block. 3:1 VDEL[2:0] 000 When VSMPDET = 0 these bits have no effect. When VSMPDET = 1 these bits set a programmable delay from the detected edge of the signal applied to the VSMP pin. The internally generated pulse is delayed by VDEL MCLK periods from the detected edge. See Figure 13, Internal VSMP Pulses Generated for details. 4 POSNNEG 0 When VSMPDET = 0 this bit has no effect. When VSMPDET = 1 this bit controls whether positive or negative edges are detected: 0 = Negative edge on VSMP pin is detected and used to generate internal timing pulse. 1 = Positive edge on VSMP pin is detected and used to generate internal timing pulse. See Figure 13 for further details. 7:5 Reserved 000 Must be set to Zero Setup Register 6
0 Reserved 0 Must be set to Zero
2:1 Reserved 11 Must be set to One 4:3 OPDLY[1:0] 10 Programmable adjust on the output propagation time (tPD) 00 = 8ns 01 = 12ns 10 = 14ns 11 = not valid 7:5 Reserved 000 Must be set to zero Offset DAC (Red) 7:0 DACR[7:0] 10000000 Red channel offset DAC value. Used under control of the INTM[1:0] control bits. Offset DAC (Green) 7:0 DACG[7:0] 10000000 Green channel offset DAC value. Used under control of the INTM[1:0] control bits. Offset DAC (Blue) 7:0 DACB[7:0] 10000000 Blue channel offset DAC value. Used under control of the INTM[1:0] control bits. Offset DAC (RGB) 7:0 DAC[7:0] A write to this register location causes the red, green and blue offset DAC registers to be overwritten by the new value PGA gain (Red) 7:0 PGAR[7:0] 00000000 Determines the gain of the red channel PGA according to the equation: Red channel PGA gain = [0.78+(PGAR[7:0]*7.57)/255]. Used under control of the INTM[1:0] control bits. PGA gain (Green) 7:0 PGAG[7:0] 00000000 Determines the gain of the green channel PGA according to the equation: Green channel PGA gain = [0.78+(PGAG[7:0]*7.57)/255]. Used under control of the INTM[1:0] control bits. PGA gain (Blue) 7:0 PGAB[7:0] 00000000 Determines the gain of the blue channel PGA according to the equation: Blue channel PGA gain = [0.78+(PGAB[7:0]*7.57)/255]. Used under control of the INTM[1:0] control bits. PGA gain (RGB) 7:0 PGA[7:0] A write to this register location causes the red, green and blue PGA gain registers to be overwritten by the new value Table 5 Register Control Bits
w PD, Rev 4.1, August 2011 RECOMMENDED EXTERNAL COMPONENTS Figure 18 External Components Diagram COMPONENT REFERENCE SUGGESTED VALUE C1 100nF De-coupling for DVDD2. C2 100nF De-coupling for DVDD1. C3 100nF De-coupling for AVDD. C4 10nF High frequency de-coupling between VRT and VRB. C5 1 F Low frequency de-coupling between VRT and VRB (non-polarised). C6 100nF De-coupling for VRB. C7 100nF De-coupling for VRT. C8 100nF De-coupling for VRLC. C9 10 F Reservoir capacitor for DVDD2. C10 10 F Reservoir capacitor for DVDD1. C11 10 F Reservoir capacitor for AVDD. C12 200pF Input coupling capacitor Table 6 External Components Descriptions
w PD, Rev 4.1, August 2011 PACKAGE DIMENSIONS NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. DM0015.CDS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm) Symbols Dimensions (mm) MIN NOM MAX A ----- ----- 2.0 A2 1.65 1.75 1.85 b 0.22 0.30 0.38 c 0.09 ----- 0.25 D 6.90 7.20 7.50 e 0.65 BSC E 7.40 7.80 8.20 5.00 5.30 5.60 L 0.55 0.75 0.95 REF: A A2 A1 SEATING PLANE -C- 0.10 C 101 D 1120 eb E1 E -JEDEC.95, MO 150 0o 4o 8o L1 1.25 REF c L GAUGE PLANE 0.25 L 1
w PD, Rev 4.1, August 2011 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specific ations in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfs on is not liable for applications assistance or customer product design. The customer is solely responsible for its se lection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support sys tems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is per missible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other noti ces (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc Westfield House
26 Westfield Road
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
w PD, Rev 4.1, August 2011
REVISION HISTORY
DATE REV ORIGINATOR CHANGES 18/09/07 4.0 JP Page 6 Changed minimum ADC Full-Scale Error from -50mV to -60mV Changed maximum ADC Full-Scale Error from +50mV to +60mV Changed the minimum value of PGA’s maximum gain from 8.0 to 8.2 Changed the maximum value of PGA’s maximum gain from 8.7 to 8.8 Changed the maximum value of PGA’s minimum gain from 0.84 to 0.87 29/08/11 4.1 AA Page 22 Register Map Description: Setup Register 1 (6) – deleted INTRLC =1 from description Setup Register 4 (3) – changed RLCINT to INTRLC