WM8200

WM8200 WOLFSON | Alldatasheet

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Technical content

w WM8200-10/12 40MSPS ADC with PGA WOLFSON MICROELECTRONICS LTD www.wolfsonmicro.com Product Preview March 2002, Rev 1.22 Copyright 2002 Wolfson Microelectronics Ltd.

DESCRIPTION

The WM8200 is a CMOS high speed, low power, pipeline analogue-to-digital converter (ADC) with 10 or 12-bit output options. It also has an on-chip programmable gain amplifier (PGA), dc clamp circuit and internal voltage references. Conversion is controlled by a single clock input. The device has a high bandwidth differential sample and hold input, which gives excellent common-mode noise immunity and low distortion. Alternatively, it can be driven in single ended fashion with an optional voltage clamp for dc restoration that can take its reference from an on-chip 10-bit DAC. The WM8200 provides internal reference voltages for setting the ADC full-scale range without the requirement for external circuitry. However, it can also accept external references for applications where shared or high-precision references are required. A 3-wire serial interface is used to control the device and a 10 or 12-bit parallel interface is to read ADC conversion data. ADC data can be output in unsigned binary or two’s complement format. The WM8200 operates with a single 3V supply and is supplied in a 28-lead QFN package.

FEATURES

10 or 12-bit resolution ADC 40MSPS conversion rate Programmable Gain Amplifier (PGA) Adjustable internal voltage references Built in clamp function (dc restore) with 10-bit DAC Wide Input Bandwidth - 900MHz Unsigned Binary or Two’s complement output format Programmable via 3-wire serial MPU interface Single 3V supply operation Low power - 100mW typical at 3.0V supplies Powerdown mode to <0.1mW typical 28 lead QFN package

APPLICATIONS

Composite Video Digitisation Digital Copiers Digital Video Cameras BLOCK DIAGRAM AINP ON-CHIP REFERENCE GENERATOR ADC Core S/H PGA AINN DO[9:0] WM8200-10 or DO[11:0] WM8200-12 OUTPUT BUFFERS MODE REFSENSE AGND AVDD REFB REFT DGND DVDD SDIN TIMING CONTROL CLK VREF WM8200 CSB SCLK CLAMP AMPLIFIER CLAMP REGISTERS CONTROL CLAMP LEVEL DAC ADC CORE

w PP Rev 1.22 March 2002 PIN CONFIGURATION WM8200-10 AINP AINN REFB MODE REFT CLAMP REFSENSE DO8 DO9 SCLK DGND CLK CSB SDIN DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO0 NC NC DVDD AGND AVDD VREF WM8200-12 AINP AINN REFB MODE REFT CLAMP REFSENSE DO10 DO11 SCLK DGND CLK CSB SDIN DO3 DO4 DO5 DO6 DO7 DO8 DO9 DO2 DO1 DO0 DVDD AGND AVDD VREF

ORDERING INFORMATION

TEMP. RANGE PACKAGE WM8200-10IFL -40 to +85oC 28-lead QFN WM8200-12IFL -40 to +85oC 28-lead QFN

w PP Rev 1.22 March 2002 PIN DESCRIPTION PIN NAME TYPE Digital output bit (MSB) SCLK Digital Input 3-Wire Control Interface Clock Input DGND Ground Negative Digital Supply CLK Analogue Input Clock input CSB Digital Input 3-Wire Control Interface Chip Select SDIN Digital Input 3-Wire Control Interface Data Input REFSENSE Analogue Input VREF feedback/configuration control CLAMP Digital Input High to enable clamp mode, low to disable clamp mode REFT Analogue Input/Output Top ADC reference voltage MODE Analogue Input High (MODE=AVDD) to enable internal ADC references. Low (MODE=AVSS) to enable use of external ADC references applied to REFT and REFB. REFB Analogue Input/Output Bottom ADC reference voltage AINN Analogue Input Positive analogue input AINP Analogue Input Negative analogue Input VREF Analogue Input/Output Internal/external reference voltage AVDD Supply Positive Analogue Supply AGND Ground Negative Analogue Supply DVDD Supply Positive Digital Supply NC DO0 Digital Output Not internally connected (10-bit option)/ Digital output bit (LSB for 12-bit option only) NC DO1 Digital Output Not internally connected (10-bit option) / Digital output bit (for 12-bit Option Only) DO0 DO2 Digital Output Digital output bit (LSB for 10-bit Option)

w PP Rev 1.22 March 2002 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION MIN MAX Digital supply voltage, DVDD to DGND -0.3V +3.63V Analog supply voltage, AVDD to AGND -0.3V +3.63V Maximum voltage difference between AGND and DGND -0.3V +0.3V Voltage range digital input (SCLK, SDIN, CSB, CLAMP) DGND - 0.3V DVDD + 0.3V Voltage range analog inputs AGND - 0.3V AVDD + 0.3V Voltage range CLK, MODE inputs AGND - 0.3V AVDD + 0.3V Operating junction temperature range, TJ -40°C +150°C Storage temperature -65°C +150°C Package Body Temperature (soldering 10 seconds) +240°C Package Body Temperature (soldering 2 minutes) +183°C RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN NOM MAX UNIT Digital supply range DVDD 3.0 3.3 3.6 V Analog supply range AVDD 3.0 3.3 3.6 V Ground DGND, AGND V Clock frequency fCLK MHz Clock duty cycle Operating Free Air Temperature TA -40

w PP Rev 1.22 March 2002

ELECTRICAL CHARACTERISTICS

Test Conditions: AVDD = DVDD = 3.0V, fCLK = 40MHz, 50% duty cycle, MODE = AVDD, VREF=1.0V (REFT = 2.0V, REFB = 1.0V), PGA gain = 1.0, TA = TMIN to TMAX, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DC Accuracy Integral nonlinearity INL ±1.0 LSB Differential nonlinearity DNL ±0.3 LSB Offset error 0.7 % of FSR Full scale error 2.2 % of FSR Missing codes No missing codes guaranteed Analogue Input Signal to AIN pins Differential analogue input voltage (AINP-AINN) PGA=1x gain V Switched input capacitance 1.2 pF Conversion Characteristics Conversion frequency fCLK MHz Pipeline delay cycles of CLK Dynamic Performance (differential input mode) fIN = 4.8MHz 9.6 Effective number of bits ENOB fIN = 20MHz 9.5 bits fIN = 4.8MHz Spurious free dynamic range SFDR fIN = 20MHz dB fIN = 4.8MHz -72.5 Total harmonic distortion THD fIN = 20MHz -71.6 dB fIN = 4.8MHz Signal to noise ratio SNR fIN = 20MHz dB fIN = 4.8MHz 59.7 Signal to noise and distortion ratio SINAD fIN = 20MHz 59.6 dB PGA Gain range (linear scale) 0.5 V/V Gain step size (linear scale) 0.5 V/V Clamp Clamp DAC resolution bits Clamp DAC output voltage REFB REFT V Clamp DAC DNL LSB Clamp output voltage error -40 mV REFB, REFT internal ADC reference voltage outputs (MODE= AVDD) VREF = 0.5V 1.75 Reference voltage top, REFT (AVDD=3V) VREF= 1.0V VREF = 0.5V 1.25 Reference voltage bottom, REFB (AVDD=3V) VREF= 1.0V VREF Input / Output specifications (ADC Input Range = VREFx2) Internal 0.5V reference to VREF REFSENSE = VREF 0.5 V Internal 1V reference to VREF REFSENSE = AGND V External reference applied to VREF pin REFSENSE = AVDD 0.5 V Input impedance in internal ADC reference mode REFSENSE = AVDD, MODE = AVDD kΩ

w PP Rev 1.22 March 2002 Test Conditions: AVDD = DVDD = 3.0V, fCLK = 40MHz, 50% duty cycle, MODE = AVDD, VREF=1.0V (REFT = 2.0V, REFB = 1.0V), PGA gain = 1.0, TA = TMIN to TMAX, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Power Supplies MODE = AGND 28.5 mA Analogue supply current IAVDD MODE = AVDD mA Digital supply current IDVDD CL = 10pF mA Standby power consumption (digital and analogue combined) IVDD(STBY) uW Digital Logic Levels (CMOS Levels) Input LOW level VIL (Note 1) 0.2 x VDD V Input HIGH level VIH (Note 1) 0.8 x VDD V Output LOW VOL IOL = -50µA 0.4 V Output HIGH VOH IOH = 50µA VDD – 0.4 V Notes Digital input and output levels refer to the supply used for the input/output buffer on the relevant pin. CLK and MODE refer to the AVDD supply, all other digital input/output refers to the DVDD supply. CONTROL INTERFACE TIMING CSB SCLK SDIN tCSL tDHO tDSU tCSH tSCY tSCH tSCL tSCS LSB tCSS Figure 1: Control Interface Timing Test Conditions AVDD = DVDD = 3.0V, AGND = DGND = 0V, TA = TMIN to TMAX, unless otherwise stated PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CSB rising edge tSCS ns SCLK pulse cycle time tSCY ns SCLK pulse width low tSCL ns SCLK pulse width high tSCH ns SDIN to SCLK set-up time tDSU ns SCLK to SDIN hold time tDHO ns CSB pulse width low tCSL ns CSB pulse width high tCSH ns CSB rising to SCLK rising tCSS ns Table 1 Control Interface Timing Information

w PP Rev 1.22 March 2002 Gain REFB REFT AINN AINP Gain REFT REFB PROGRAMMABLE-GAIN AMPLIFIER VP is amplified by the PGA and fed into the ADC as a differential voltage VQ = VQ+ - VQ- INN INP P Q V V Gain V Gain V ANALOGUE-TO-DIGITAL CONVERTER Regardless of the reference configuration, VQ is digitised against ADC Reference voltages REFT and REFB, full scale values of VQ being given by: REFB REFT VQFS REFB REFT VQZS Attempts to convert VQ voltages outside the range of VQZS to VQFS are signalled to the application by driving the OVR output pin high when the conversion result is output. If VQ is less than VQZS, the ADC output code is 0. If VQ is greater than VQFS, the output code is 1023. SIGNAL CHAIN SUMMARY Combining the above equations to find the input voltages [AINP – AINN] that correspond to the limits of the ADCs valid input range gives: Therefore the input signal span is given by: Gain REFB REFT AINN AINP In order to match the ADC input range to the input signal amplitude, REFT and REFB should be set such that: Gain AINN AINP REFB REFT ADC REFERENCE MODES The WM8200 references REFT and REFB can be driven from external (off-chip) sources or from the internal reference generation/buffer circuit. The mode of operation is selected by the voltage applied to the MODE pin. These are summarised and explained in Table 2. Note that the internally generated ADC references are intended solely for WM8200 internal use and REFT and REFB must not be used as voltage references for any other device in the application. MODE PIN MODE FUNCTION COMMENTS AGND Full external external REFT = external REFB = On-chip reference generator and reference buffer are not used. AVDD Top/Bottom REFBS REFTS AVDD REFTF REFBS REFTS AVDD REFBF On-chip reference generator is not used. Reference buffer centers external reference voltages around AVDD/2. Table 2 WM8200 Reference Generation Modes and zero scale by

w PP Rev 1.22 March 2002 VDAC DAC code 1023 VREFBF + 0.987(VREFTF-VREFBF) VREFBF VREFTF VREFBF + 0.006(VREFTF-VREFBF) Figure 5 Clamp DAC Output Voltage versus DAC Register Code Value COARSE OFFSET The WM8200 features a coarse offset feature which allows it to accommodate both positive-going and negative-going input signals when using the DC clamp. This feature is enabled by setting the PGAOFF register bit to high. DIAGRAM SHOWING COARSE OFFSET TO BE INSERTED

w PP Rev 1.22 March 2002 CONTROL INTERFACE The internal control registers are programmable via the 3-wire serial interface. SDIN is used for the program data, SCLK is used to clock in the data and CSB is used to latch in the program data. The 3-wire interface protocol is shown in Figure 6. Figure 6: 3-Wire Serial Interface A[3:0] are Control Address Bits D[7:0] are Control Data Bits CSB is edge sensitive – the data is latched on the rising edge of CSB. REGISTER MAP Table 3 shows the location of each control bit used to determine the operation of the WM8200. The procedure for programming the register map is described in the CONTROL INTERFACE section. BIT ADDR NAME DEFAULT (HEX) 0000 Clamp Reg 1 DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0] 0001 Clamp Reg 2 DAC[9] DAC[8] 0010 PGA Control PGASENSE PGAOFF PGA[2] PGA[1] PGA[0] 0011 Control CLPSEL OEB TWOSC CLDIS PD 0100 - 1111 Reserved Reserved, do not write to these register locations Table 3: Register Map D7 D6 D5 D4 D3 D2 D1 D0 CSB SCLK SDIN A3 A2 A1 A0 ADDRESS DATA

w PP Rev 1.22 March 2002 REGISTER MAP DESCRIPTION REGISTER BIT BIT NAMES DEFAULT 7:0 DAC[7:0] 00000000 Clamp DAC value bits 7 to 0 (Unsigned binary format) Clamp Register 2 1:0 DAC[9:8] Clamp DAC value bits 9 to 8 (Unsigned binary format) PGA Gain control 000: PGA Gain = 0.5x 100: PGA Gain = 2.5x 001: PGA Gain = 1.0x 101: PGA Gain = 3.0x 010: PGA Gain = 1.5x 110: PGA Gain = 3.5x 2:0 PGA[2:0] 001 011: PGA Gain = 2.0x 111: PGA Gain = 4.0x PGAOFF Enables a coarse offset to be added to the output of the PGA. Allows the use of single ended input signals with no loss of ADC dynamic range. PGA Control Register PGASENSE Determines the sense of the coarse offset added to the output of the PGA. This bit only has an effect when PGAOFF=1. 0: PGA output is offset to full-scale positive for zero differential input (suitable for negative going video). 1: PGA output is offset to full-scale negative for zero differential input (suitable for positive going video). PD Device power-down 0: Device is powered up 1: Device is powered down. CLDIS CLAMP amplifier enable (for power saving) 0: Enable 1: Disable TWOSC Output data format 0: Unsigned binary 1: Twos complement OEB Output data pin enable 0: DO[9:0]/DO[11:0] enabled 1: DO[9:0]/DO[11:0] disabled (outputs are high impedance). Control Register CLPSEL Clamp source select 0: Clamp to output of Clamp DAC 1: Clamp to voltage on AINN input pin POWER MANAGEMENT In power-sensitive applications (such as battery-powered systems) where the WM8200 ADC is not required to convert continuously, power can be saved between conversion intervals by placing the WM8200 into Power Down mode. This is achieved by setting bit 0 (PD) of the control register to 1. In Power Down mode, the device typically consumes less than 3mW of power. Power down mode is exited by resetting control register bit 1 to 0. On power up from long periods of power down, the WM8200 typically requires 5ms of wake up time before valid conversion results are available. In systems where the ADC must run continuously, but where the clamp is not required, the supply current can be reduced by approximately 1.2mA by setting the control register bit 1 (CLDIS), which disables the clamp circuit. Similarly, when REFSENSE is tied to AVDD, the reference generator is disabled and supply current reduced by approximately 1.2mA. DATA OUTPUT FORMAT While the OEB pin is held low, ADC conversion results are output at the data I/O pins DO[0] (LSB) to DO[9] (MSB). The default output data format is unsigned binary (output codes 0 to 1023). This can be switched to two’s complement format (output codes -512 to 511) by setting control register bit 2 (TWOSC) to 1.

w PP Rev 1.22 March 2002 REFERENCE DECOUPLING VREF, REFT and REFB must be decoupled as shown in Figure 11. REFT REFB WM8200-10/12 100 nF 100 nF 100 nF 10 µµµµF 100 nF VREF 10 µµµµF Figure 11: VREF, REFT and REFB decoupling

w PP Rev 1.22 March 2002 PACKAGE DIMENSIONS DM023.C FL: 28 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.9 mm BODY, 0.50 mm LEAD PITCH b C aaa L D2/2 E2/2 SEE DETAIL B INDEX AREA (D/2 X E/2) C aaa 2 X 2 X C C 0.08 C ccc A (A3) SEATING PLANE B C ccc M A DETAIL B TERMINAL TIP R NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 2. FALLS WITHIN JEDEC.95, MO-220 WITH THE EXCEPTION OF D2, E2, A3: D2,E2: LARGER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION A3: NOMINAL VALUE LESS THAN JEDEC 3. ALL DIMENSIONS ARE IN MILLIMETRES 4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. Symbols Dimensions (mm) MIN NOM MAX NOTE A 0.80 0.90 1.00 b 0.18 0.23 0.30 D

5.00 BSC

3.2 3.3 3.4 E 3.2 3.3 3.4 e

0.5 BSC

L 0.35 0.4 0.45 0.02 0.05

0.2 REF

B B A A DATUM e R b(min)/2 aaa 0.15 ccc 0.10 REF: JEDEC.95, MO-220, VARIATION VHHD-1 Tolerances of Form and Position e D E

w PP Rev 1.22 March 2002 IMPORTANT NOTICE Wolfson Microelectronics Ltd (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s approval, license, warranty or endorsement thereof. Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. ADDRESS: Wolfson Microelectronics plc Westfield House

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