WM8195

WM8195_05 WOLFSON | Alldatasheet

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Technical content

w WM8195 14-bit 12MSPS CIS/CCD Analogue Front End/Digitiser WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ Production Data July 2005 Rev 4.1 Copyright 2005 Wolfson Microelectronics plc.

DESCRIPTION

The WM8195 is a 14-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors (CIS) at pixel sample rates of up to 12MSPS. The device includes three analogue signal processing channels each of which contains Reset Level Clamping, Correlated Double Sampling and Programmable Gain and Offset Adjust functions. Three multiplexers allow single channel processing. The output from each of these channels is time multiplexed into a single high-speed 14-bit analogue-to-digital converter. The digital output data is available in 14-bit parallel or 8, 7 or 4-bit wide multiplexed format, with no missing codes. An internal 4-bit DAC is supplied for internal reference level generation. This may be used during CDS to reference CIS signals or during Reset Level Clamping to clamp CCD signals. Alternatively an external reference level may be applied. ADC references are generated internally, ensuring optimum performance from the device. Using an analogue supply voltage of 5V and a digital interface supply of either 5V or 3.3V, the WM8195 typically only consumes 210mW when operating from a single 5V supply and less than 20µA when in power down mode.

FEATURES

No missing codes guaranteed 12MSPS conversion rate Low power – 210mW typical 5V single supply or 5V/3.3V dual supply operation Single or 3 channel operation Correlated double sampling Programmable gain (8-bit resolution) Programmable offset adjust (8-bit resolution) Programmable clamp voltage 14-bit parallel or 8, 7 or 4-bit wide multiplexed data output formats Internally generated voltage references 48-lead TQFP package Serial or parallel control interface

APPLICATIONS

Flatbed and sheetfeed scanners USB compatible scanners Multi-function peripherals High-performance CCD sensor interface BLOCK DIAGRAM M U X RINP DATA I/O PORT SEN/STB VSMP MCLK VRLC/VBIAS SDI/DNA SCK/RNW TIMING CONTROL CL RLC/ACYC RLC VS RS BINP GINP VRX VREF/BIAS OEB M U X VRB RLC RLC CDS CDS CDS R G B M U X R G B PGA I/P SIGNAL POLARITY ADJUST PGA PGA CONFIGURABLE SERIAL/ PARALLEL CONTROL INTERFACE 14- BIT ADC AVDD1-2 OP[0] OP[1] OP[2] OP[3] OP[4] OP[5] OP[6] OP[7] I/P SIGNAL POLARITY ADJUST I/P SIGNAL POLARITY ADJUST DVDD1-3 OP[8] OP[9] OP[10] OP[11] OP[12] OP[13]/SDO NRESET DGND1-5 AGND1-6 VRT w WM8195 OFFSET DAC OFFSET DAC OFFSET DAC M U X RLC DAC

w PD Rev 4.1 July 2005 TABLE OF CONTENTS

w PD Rev 4.1 July 2005 PIN CONFIGURATION VRT AVDD1 AVDD2 AGND5 AGND6 VRB OP[11] OP[12] OP[13]/SDO DGND5 NC NRESET 47 46 45 44 43 42 41 40 39 38 DVDD2 DGND1 OP[1] NC NC OP[0] OP[2] VSMP SDI/DNA SCK/RNW RLC/ACYC MCLK VRX AGND3 GINP AGND2 BINP AGND1 VRLC/VBIAS RINP AGND4 DVDD1 OEB SEN/STB DGND4 DGND3 OP[7] OP[8] OP[9] OP[10] DVDD3 DGND2 OP[3] OP[4] OP[5] OP[6] 16 17 18 19 20 21 22 13 14 15

ORDERING INFORMATION

0 to 70°C 48-lead TQFP 1mm thick body (Pb-free) MSL2 260oC XWM81955CFT/RV 0 to 70°C 48-lead TQFP 1mm thick body (Pb-free, tape and reel) MSL2 260oC Note: Reel quantity = 2,200

w PD Rev 4.1 July 2005 PIN DESCRIPTION PIN NAME TYPE Input return bias voltage. This pin must be decoupled to AGND via a capacitor. VRLC/VBIAS Analogue I/O Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be decoupled to AGND via a capacitor. VRLC can be externally driven if programmed Hi-Z. AGND1 Supply Analogue ground (0V). BINP Analogue input Blue channel input video. AGND2 Supply Analogue ground (0V). GINP Analogue input Green channel input video. AGND3 Supply Analogue ground (0V). RINP Analogue input Red channel input video. AGND4 Supply Analogue ground (0V). DVDD1 Supply Digital supply (5V) for logic and clock generator. This must be operated at the same potential as AVDD. OEB Digital input Output Hi-Z control, all digital outputs disabled when OEB = 1. Serial interface: enable pulse, active high Parallel interface: strobe, active low SEN/STB Digital input Latched on NRESET rising edge: if Low then device control is via serial interface, if high then device control is via parallel interface. SDI/DNA Digital input Serial interface: serial input data signal Parallel interface: High = data, Low = address SCK/RNW Digital input Serial interface: serial clock signal Parallel interface: High: OP[13:6] is output bus. Low: OP[13:6] is input bus (Hi-Z). VSMP Digital input Video sample synchronisation pulse. RLC/ACYC Digital input RLC (active high) selects reset level clamp on a pixel-by-pixel basis – tie high if used on every pixel. ACYC autocycles between R, G, B inputs when in Line-by-Line mode. MCLK Digital input Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or any multiple of 2 thereafter depending on input sample mode). DGND1 Supply Digital ground (0V). NC No connection. NC No connection. OP[0] Digital output OP[1] Digital output OP[2] Digital output Pins OP[13:0] form a Hi-Z digital bi-directional bus. There are several modes: Hi-Z: when OEB = 1. 14-bit output: 14-bit data is output on OP[13:0]. 8-bit multiplexed output: data is output on OP[13:6] at 2 ∗ ADC conversion rate. 7-bit multiplexed output: data is output on OP[13:6] at 2 ∗ ADC conversion rate. 4-bit multiplexed output: data is output on OP[13:10] at 4 ∗ ADC conversion rate. See Output Formats section in Device Description for further details. Input 8-bit: control data is input on OP[13:6] in parallel mode when SCK/RNW = 0, and SEN/STB = 0. Output 8-bit: register read back data is output in parallel on OP[13:6] when SCK/RNW = 1, and SEN/STB = 0, or in serial on pin SDO when SEN/STB = 1. DVDD2 Supply Digital I/O supply (3.3V/5V). DGND2 Supply Digital ground (0V). OP[3] Digital output OP[4] Digital output OP[5] Digital output OP[6] Digital I/O See pins 21 to 23 for details. DGND3 Supply Digital ground (0V).

w PD Rev 4.1 July 2005 PIN NAME TYPE OP[7] Digital I/O OP[8] Digital I/O OP[9] Digital I/O OP[10] Digital I/O See pins 21 to 23 for details. DVDD3 Supply Digital I/O supply (3.3V/5V). DGND4 Supply Digital ground (0V). OP[11] Digital I/O OP[12] Digital I/O OP[13]/SDO Digital I/O See pins 21 to 23 for details. If the device has been configured to use the serial interface, pin OP[13]/SDO may be used to output register read-back data when OEB = 0 and SEN has been pulsed high. See Serial Interface sections in Device Description for further details. DGND5 Supply Digital ground (0V). NC No connection. NRESET Digital input Reset input, active low. This signal forces a reset of all internal registers and selects whether the serial or parallel control interface is used. See pin SEN/STB. AVDD1 Supply Analogue supply (5V). AVDD2 Supply Analogue supply (5V). AGND5 Supply Analogue ground (0V). AGND6 Supply Analogue ground (0V). VRB Analogue output Lower reference voltage. This pin must be capacitively decoupled to AGND. VRT Analogue output Lower reference voltage. This pin must be capacitively decoupled to AGND.

w PD Rev 4.1 July 2005 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION MIN MAX Analogue supply voltages: AVDD1, 2 GND - 0.3V GND + 7V Digital supply voltages: DVDD1 − 3 GND - 0.3V GND + 7V Digital grounds: DGND1 − 5 GND - 0.3V GND + 0.3V Analogue grounds: AGND1 − 6 GND - 0.3V GND + 0.3V Digital inputs, digital outputs and digital I/O pins GND - 0.3V DVDD2 + 0.3V Analogue inputs (RINP, GINP, BINP) GND - 0.3V AVDD + 0.3V Other pins GND - 0.3V AVDD + 0.3V Operating temperature range: TA 0°C +70°C Storage temperature -65°C +150°C Notes: GND denotes the voltage of any ground pin. AGND1 − 6 and DGND1 − 5 pins are intended to be operated at the same potential. Differential voltages between these pins will degrade performance. RECOMMENDED OPERATING CONDITIONS CONDITION SYMBOL MIN TYP MAX UNITS Operating temperature range TA Analogue supply voltage AVDD1, 2 4.75 5.0 5.25 V Digital core supply voltage DVDD1 4.75 5.0 5.25 V 5V I/O DVDD2, 3 4.75 5.0 5.25 V Digital I/O supply voltage 3.3V I/O DVDD2, 3 2.97 3.3 3.63 V

w PD Rev 4.1 July 2005

ELECTRICAL CHARACTERISTICS

AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 24MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Overall System Specification (including 14-bit ADC, PGA, Offset and CDS functions) NO MISSING CODES GUARANTEED Conversion rate MSPS Full-scale input voltage range (see Note 1) Max Gain Min Gain 0.4 4.08 Vp-p Vp-p Input signal limits (see Note 2) VIN AVDD V Full-scale transition error Gain = 0dB; PGA[7:0] = 4B(hex) mV Zero-scale transition error Gain = 0dB; PGA[7:0] = 4B(hex) mV Differential non-linearity DNL 1.25 LSB Integral non-linearity INL LSB Channel to channel gain matching Total output noise Min Gain Max Gain LSB rms LSB rms References Upper reference voltage VRT 2.85 V Lower reference voltage VRB 1.35 V Input return bias voltage VRX 1.65 V Diff. reference voltage (VRT-VRB) VRTB 1.4 1.5 1.6 V Output resistance VRT, VRB, VRX Ω VRLC/Reset-Level Clamp (RLC) RLC switching impedance Ω VRLC short-circuit current mA VRLC output resistance Ω VRLC Hi-Z leakage current VRLC = 0 to AVDD µA RLCDAC resolution bits RLCDAC step size, RLCDAC = 0 VRLCSTEP 0.25 V/step RLCDAC step size, RLCDAC = 1 VRLCSTEP 0.17 V/step RLCDAC output voltage at code 0(hex), RLCDACRNG = 0 VRLCBOT 0.39 V RLCDAC output voltage at code 0(hex), RLCDACRNG = 1 VRLCBOT 0.26 V RLCDAC output voltage at code F(hex) RLCDACRNG, = 0 VRLCTOP 4.16 V RLCDAC output voltage at code F(hex), RLCDACRNG = 1 VRLCTOP 2.81 V VRLC deviation -50 +50 mV Offset DAC, Monotonicity Guaranteed Resolution bits Differential non-linearity DNL 0.1 0.5 LSB Integral non-linearity INL 0.25 LSB Step size 2.04 mV/step Output voltage Code 00(hex) Code FF(hex) -260 +260 mV mV Notes: Full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain. Input signal limits are the limits within which the full-scale input voltage signal must lie.

w PD Rev 4.1 July 2005 Test Conditions AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 24MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Programmable Gain Amplifier Resolution bits Gain PGA 283 208 V/V Max gain, each channel GMAX 7.4 V/V Min gain, each channel GMIN 0.74 V/V Gain error, each channel Analogue to Digital Converter Resolution bits Speed MSPS Full-scale input range (2*(VRT-VRB)) V DIGITAL SPECIFICATIONS Digital Inputs High level input voltage VIH 0.8 ∗ DVDD2/3 V Low level input voltage VIL 0.2 ∗ DVDD2/3 V High level input current IIH µA Low level input current IIL µA Input capacitance CI pF Digital Outputs High level output voltage VOH IOH = 1mA DVDD2/3 - 0.5 V Low level output voltage VOL IOL = 1mA 0.5 V High impedance output current IOZ µA Digital IO Pins Applied high level input voltage VIH 0.8 ∗ DVDD2/3 V Applied low level input voltage VIL 0.2 ∗ DVDD2/3 V High level output voltage VOH IOH = 1mA DVDD2/3 - 0.5 V Low level output voltage VOL IOL = 1mA 0.5 V Low level input current IIL µA High level input current IIH µA Input capacitance CI pF High impedance output current IOZ µA Supply Currents Total supply current − active (Three channel mode) MCLK = 24MHz mA Total supply current − active (Single channel mode) LINEBYLINE = 1 MCLK = 24MHz mA Total analogue supply current − active (Three channel mode) IAVDD MCLK = 24MHz mA Total analogue supply current − active (One channel mode) IAVDD LINEBYLINE = 1 MCLK = 24MHz mA Digital core supply current, DVDD1 − active (Note1) MCLK = 24MHz mA Digital I/O supply current, DVDD2 − active (Note1) MCLK = 24MHz mA Supply current − full power down mode µA

w PD Rev 4.1 July 2005 SERIAL INTERFACE Figure 5 Serial Interface Timing Test Conditions AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 24MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS SCK period tSPER 41.6 ns SCK high tSCKH 18.8 ns SCK low tSCKL 18.8 ns SDI set-up time tSSU ns SDI hold time tSH ns SCK to SEN set-up time tSCE ns SEN to SCK set-up time tSEC ns SEN pulse width tSEW ns SEN low to SDO = Register data tSERD ns SCK low to SDO = Register data tSCRD ns SCK low to SDO = ADC data tSCADC ns Note: Parameters are measured at 50% of the rising/falling edge. SCK SDI SEN SDO tSPER tSCKL tSCKH tSSU tSH tSCE tSEW tSEC tSERD tSCRD MSB LSB t SCRDZ ADC DATA ADC DATA REGISTER DATA

w PD Rev 4.1 July 2005 PARALLEL INTERFACE STB OP[13:6] DNA RNW ADC DATA OUT ADC DATA OUT REG. DATA OUT ADC DATA OUT Hi-Z Hi-Z tASU tSTB tAH tDSU tDH tSTDO tSTAO tADLS tADLH tADHS tADHH tOPD ADDRESS IN DATA IN tOPZ Figure 6 Parallel Interface Timing Test Conditions AVDD1 = AVDD2 = DVDD1 = DVDD2 = DVDD3 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 24MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS RNW low to OP[13:6] Hi-Z tOPZ ns Address set-up time to STB low tASU ns DNA low set-up time to STB low tADLS ns Strobe low time tSTB ns Address hold time from STB high tAH ns DNA low hold time from STB high tADLH ns Data set-up time to STB low tDSU ns DNA high set-up time to STB low tADHS ns Data hold time from STB high tDH ns Data high hold time from STB high tADHH ns RNW high to OP[13:6] output tOPD ns Data output propogation delay from STB low tSTDO ns ADC data out propogation delay from STB high tSTAO ns Note: Parameters are measured at 50% of the rising/falling edge.

w PD Rev 4.1 July 2005 DEVICE DESCRIPTION INTRODUCTION A block diagram of the device showing the signal path is presented on Page 1. The WM8195 samples up to three inputs (RINP, GINP and BINP) simultaneously. The device then processes the sampled video signal with respect to the video reset level or an internally/externally generated reference level using either one or three processing channels. Each processing channel consists of an Input Sampling block with optional Reset Level Clamping (RLC) and Correlated Double Sampling (CDS), a 8-bit programmable offset DAC and an 8-bit Programmable Gain Amplifier (PGA). The ADC then converts each resulting analogue signal to a 14-bit digital word. The digital output from the ADC is presented on a 14-bit wide bus, with optional 8+6-bit, 7+7-bit or 4+4+4+2-bit multiplexed formats. On-chip control registers determine the configuration of the device, including the offsets and gains applied to each channel. These registers are programmable via a serial or parallel interface. INPUT SAMPLING The WM8195 can sample and process one to three inputs through one or three processing channels as follows: Colour Pixel-by-Pixel: The three inputs (RINP, GINP and BINP) are simultaneously sampled for each pixel and a separate channel processes each input. The signals are then multiplexed into the ADC, which converts all three inputs within the pixel period. Monochrome: A single chosen input (RINP, GINP, or BINP) is sampled, processed by the corresponding channel, and converted by the ADC. The choice of input and channel can be changed via the control interface, e.g. on a line-by-line basis if required. Colour Line-by-Line: A single chosen input (RINP, GINP, or BINP) is sampled and multiplexed into the red channel for processing before being converted by the ADC. The input selected can be switched in turn (RINP → GINP → BINP → RINP…) together with the PGA and offset DAC control registers by pulsing the RLC/ACYC pin. This is known as auto-cycling. Alternatively, other sampling sequences can be generated via the control registers. This mode causes the blue and green channels to be powered down. Refer to the Line-by-Line Operation section for more details. RESET LEVEL CLAMPING (RLC) To ensure that the signal applied to the WM8195 lies within its input range (0V to AVDD) the CCD output signal is usually level shifted by coupling through a capacitor, CIN. The RLC circuit clamps the WM8195 side of this capacitor to a suitable voltage during the CCD reset period. A typical input configuration is shown in Figure 7 An internal clamp pulse, CL, is generated from MCLK and VSMP by the Timing Control Block. When CL is active the voltage on the WM8195 side of CIN, at RINP, is forced to the VRLC/VBIAS voltage (VVRLC) by closing of switch 1. When the CL pulse turns off, switch 1 opens, the voltage at RINP initially remains at VVRLC but any subsequent variation in sensor voltage (from reset to video level) will couple through CIN to RINP. RLC is compatible with both CDS and non-CDS operating modes, as selected by switch 2. Refer to the CDS/Non-CDS Processing section.

w PD Rev 4.1 July 2005 CALCULATING OUTPUT FOR ANY GIVEN INPUT The following equations describe the processing of the video and reset level signals though the WM8199. The values of V1 V2 and V3 are often calculated in reverse order during device setup. The PGA value is written first to set tshe input Voltage range, the Offset DAC is then adjusted to compensate for any Black/Reset level offsets and finally the RLC DAC value is set to position the reset level correctly during operation. Note: Refer to WAN0123 for detailed information on device calibration procedures. The following equations describe the processing of the video and reset level signals through the WM8195. INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING If CDS = 1, (CDS operation) the previously sampled reset level, VRESET, is subtracted from the input video. If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted instead. If RLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS. If RLCEXT = 0, VVRLC is the output from the internal RLC DAC. VVRLC VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC. OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST The resultant signal V1 is added to the offset DAC output. PGA NODE: GAIN ADJUST The signal is then multiplied by the PGA gain, ADC BLOCK: ANALOGUE-DIGITAL CONVERSION The analogue signal is then converted to a 14-bit unsigned number, with input range configured by PGAFS[1:0]. where the ADC full-scale range, VFS = 3V. OUTPUT INVERT BLOCK: POLARITY ADJUST The polarity of the digital output may be inverted by control bit INVOP.

w PD Rev 4.1 July 2005 FME ACYCNRLC NAME Internal, no force mux Input mux, offset and gain registers determined by internal register bits INTM1, INTM0. Auto-cycling, no force mux Input mux, offset and gain registers auto-cycled, RINP → GINP → BINP → RINP… on RLC/ACYC pulse. Internal, force mux Input mux selected from internal register bits FM1, FM0; Offset and gain registers selected from internal register bits INTM1, INTM0. Auto-cycling, force mux Input mux selected from internal register bits FM1, FM0; Offset and gain registers auto-cycled, RED → GREEN → BLUE → RED… on RLC/ACYC pulse. Table 4 Colour Selection Description in Line-by-Line Mode

w PD Rev 4.1 July 2005 OPERATING MODES Table 5 summarises the most commonly used modes, the clock waveforms required and the register contents required for CDS and non-CDS operation. MODE

CONTENTS

parallel. The signal is then gain and offset adjusted before being multiplexed into a single data stream and converted by the ADC, giving an output data rate of 12MSPS max. MCLK max = 24MHz MCLK: VSMP ratio is 6:1 SetReg1: 03(hex) SetReg1: 01(hex) Monochrome/ Colour Line-by-Line Yes 4MSPS x 1 chan As mode 1 except: Only one input channel at a time is continuously sampled. MCLK max = 24MHz MCLK: VSMP ratio is 6:1 SetReg1: 07(hex) SetReg1: 05(hex) Fast Monochrome/ Colour Line-by-Line Yes 8MSPS x 1 chan Identical to mode 2 MCLK max = 24MHz MCLK: VSMP ratio is 3:1 Identical to mode 2 plus SetReg3: bits 5:4 must be set to 0(hex) Identical to mode 2 Maximum speed Monochrome/ Colour Line-by-Line No 12MSPS x 1 chan Identical to mode 2 MCLK max = 24MHz MCLK: VSMP ratio is 2:1 CDS not possible SetReg1: 45(hex) Slow Colour Pixel-by-Pixel Yes 3MSPS x 3 chans Identical to mode 1 MCLK max = 24MHz MCLK: VSMP ratio is 2n:1, n ≥ 4 Identical to mode 1 Identical to mode 1 Slow Monochrome/ Colour Line-by-Line Yes 3MSPS x 1 chan Identical to mode 2 MCLK max = 24MHz MCLK: VSMP ratio is 2n:1, n ≥ 4 Identical to mode 2 Identical to mode 2 Table 5 WM8195 Operating Modes Notes: In Monochrome mode, Setup Register 3 bits 7:6 determine which input is to be sampled. For Colour Line-by-Line, set control bit LINEBYLINE. For input selection, refer to Table 4, Colour Selection Description in Line-by-Line Mode.

w PD Rev 4.1 July 2005 OPERATING MODE TIMING DIAGRAMS The following diagrams show 14-bit parallel format output and MCLK, VSMP and input video requirements for operation of the most commonly used modes as shown in Table 5. The diagrams are identical for both CDS and non-CDS operation. Outputs from RINP, GINP and BINP are shown as R, G and B respectively. X denotes invalid data. MCLK VSMP INPUT VIDEO OP[13:0] (DEL = 00) OP[13:0] (DEL = 01) OP[13:0] (DEL = 10) OP[13:0] (DEL = 11)

16.5 MCLK PERIODS

G B R G B R G R B R B G R R G B R G B R B G B G R B R B R G B R G B G R G R B G B R G B R G B R G R B R B G R G B G G B Figure 21 Mode 1 Operation Figure 22 Mode 2 Operation Figure 23 Mode 3 Operation

w PD Rev 4.1 July 2005 Figure 24 Mode 4 Operation MCLK VSMP INPUT VIDEO OP[13:0] (DEL = 00) OP[13:0] (DEL = 01) OP[13:0] (DEL = 10) OP[13:0] (DEL = 11) G B R B G R G B R X X X R G X G R X R G X B B B X R B R X B X R B G G G B X G X B G B X G R R R B X G B R X R G B X R G Figure 25 Mode 5 Operation (MCLK:VSMP Ratio = 8:1) Figure 26 Mode 6 Operation (MCLK:VSMP Ratio = 8:1)

w PD Rev 4.1 July 2005 DEVICE CONFIGURATION REGISTER MAP The following table describes the location of each control bit used to determine the operation of the WM8195. The register map is programmed by writing the required codes to the appropriate addresses via the serial or parallel interface. BIT ADDRESS <a5:a0> (hex) RW 000001 Setup Reg 1 RW MODE4 PGAFS[1] PGAFS[0] SELPD MONO CDS EN 000010 Setup Reg 2 RW DEL[1] DEL[0] RLCDACRNG VRLCEXT INVOP MUXOP[1] MUXOP[0] 000011 Setup Reg 3 RW CHAN[1] CHAN[0] CDSREF [1] CDSREF [0] RLCV[3] RLCV[2] RLCV[1] RLCV[0] 000100 Software Reset W 000101 Auto-cycle Reset W 000110 Setup Reg 4 RW FM[1] FM[0] INTM[1] INTM[0] RLCINT FME ACYCNRLC LINEBYLINE 000111 Revision Number R 001000 Setup Reg 5 RW POSNNEG VDEL[2] VDEL[1] VDEL[0] VSMPDET 001001 Setup Reg 6 RW SELDIS[3] SELDIS[2] SELDIS[1] SELDIS[0] 001010 Reserved RW 001011 Reserved RW 001100 Reserved RW 100000 DAC Value (Red) RW DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0] 100001 DAC Value (Green) RW DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0] 100010 DAC Value (Blue) RW DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0] 100011 DAC Value (RGB) W DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0] 101000 PGA Gain (Red) RW PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0] 101001 PGA Gain (Green) RW PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0] 101010 PGA Gain (Blue) RW PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0] 101011 PGA Gain (RGB) W PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0] Table 6 Register Map

w PD Rev 4.1 July 2005 REGISTER MAP DESCRIPTION The following table describes the function of each of the control bits shown in Table 7. REGISTER BIT NO BIT NAME(S) DEFAULT When SELPD = 1 this bit has no effect. When SELPD = 0 this bit controls the global power down: 0 = complete power down, 1 = fully active. CDS Select correlated double sampling mode: 0 = single ended mode, 1 = CDS mode. MONO Mono/colour select: 0 = colour, 1 = monochrome operation. SELPD Selective power down: 0 = no individual control, 1 = individual blocks can be disabled (controlled by SELDIS[3:0]). Offsets PGA output to optimise the ADC range for different polarity sensor output signals. Zero differential PGA input signal gives: 5:4 PGAFS[1:0] 00 = Zero output (use for bipolar video) 01 = Zero output 10 = Full-scale positive output (use for negative going video) 11 = Full-scale negative output (use for positive going video) Setup Register 1 MODE4 Required when operating in MODE4: 0 = other modes, 1 = MODE4. Determines the output data format. 1:0 MUXOP[1:0] 00 = 14-bit parallel 01 = 8-bit multiplexed (8+6 bits) 10 = 7-bit multiplexed mode (7+7 bits) 11 = 4-bit multiplexed mode (4+4+4+2 bits) INVOP Digitally inverts the polarity of output data. 0 = negative going video gives negative going output, 1 = negative going video gives positive going output data. VRLCEXT When set powers down the RLCDAC, changing its output to Hi-Z, allowing VRLC/VBIAS to be externally driven. RLCDACRNG Sets the output range of the RLCDAC. 0 = RLCDAC ranges from 0 to AVDD (approximately), 1 = RLCDAC ranges from 0 to VRT (approximately). Sets the output latency in ADC clock periods.

1 ADC clock period = 2 MCLK periods except in Mode 3 where 1 ADC clock

period = 3 MCLK periods. Setup Register 2 7:6 DEL[1:0] 00 = Minimum latency 01 = Delay by one ADC clock period 10 = Delay by two ADC clock periods 11 = Delay by three ADC clock periods 3:0 RLCV[3:0] 1111 Controls RLCDAC driving VRLC/VBIAS pin to define single ended signal reference voltage or Reset Level Clamp voltage. See Electrical Characteristics section for ranges. CDS mode reset timing adjust. 5:4 CDSREF[1:0] 00 = Advance 1 MCLK period 01 = Normal 10 = Retard 1 MCLK period 11 = Retard 2 MCLK periods Monochrome mode channel select. Setup Register 3 7:6 CHAN[1:0] 00 = Red channel select 01 = Green channel select 10 = Blue channel select 11 = Reserved Software Reset Any write to Software Reset causes all cells to be reset. It is recommended that a software reset be performed after a power-up before any other register writes. Auto-cycle Reset Any write to Auto-cycle Reset causes the auto-cycle counter to reset to RINP. This function is only required when LINEBYLINE = 1.

w PD Rev 4.1 July 2005 REGISTER BIT NO BIT NAME(S) DEFAULT Selects line by line operation 0 = normal operation, 1 = line by line operation. When line by line operation is selected MONO is forced to 1 and CHAN[1:0] to 00 internally, ensuring that the correct internal timing signals are produced. Green and Blue PGAs are also disabled to save power. ACYCNRLC When LINEBYLINE = 0 this bit has no effect. When LINEBYLINE = 1 this bit determines the function of the RLC/ACYC input pin and the input multiplexer and offset/gain register controls. 0 = RLC/ACYC pin enabled for Reset Level Clamp. Internal selection of input and gain/offset multiplexers, 1 = Auto-cycling enabled by pulsing the RLC/ACYC input pin. See Table 4, Colour Selection Description in Line-by-Line Mode for colour selection mode details. When auto-cycling is enabled, the RLC/ACYC pin cannot be used for reset level clamping. The RLCINT bit may be used instead. FME When LINEBYLINE = 0 this bit has no effect. When LINEBYLINE = 1 this bit controls the input force mux mode: 0 = No force mux, 1 = Force mux mode. Forces the input mux to be selected by FM[1:0] separately from gain and offset multiplexers. See Table 4 for details. RLCINT When LINEBYLINE = 1 and ACYCNRLC = 1 this bit is used to determine whether Reset Level Clamping is used. 0 = RLC disabled, 1 = RLC enabled. 5:4 INTM[1:0] Colour selection bits used in internal modes. 00 = Red, 01 = Green, 10 = Blue and 11 = Reserved. See Table 4 for details. Setup Register 4 7:6 FM[1:0] Colour selection bits used in input force mux modes. 00 = RINP, 01 = GINP, 10 = BINP and 11 = Reserved. See Table 4 for details. VSMPDET 0 = Normal operation, signal on VSMP input pin is applied directly to Timing Control block. 1 = Programmable VSMP detect circuit is enabled. An internal synchronisation pulse is generated from signal applied to VSMP input pin and is applied to Timing Control block. 3:1 VDEL[2:0] 000 When VSMPDET = 0 these bits have no effect. When VSMPDET = 1 these bits set a programmable delay from the detected edge of the signal applied to the VSMP pin. The internally generated pulse is delayed by VDEL MCLK periods from the detected edge. See Figure 19, Internal VSMP Pulses Generated for details. Setup Register 5 POSNNEG When VSMPDET = 0 this bit has no effect. When VSMPDET = 1 this bit controls whether positive or negative edges are detected: 0 = Negative edge on VSMP pin is detected and used to generate internal timing pulse. 1 = Positive edge on VSMP pin is detected and used to generate internal timing pulse. See Figure 19 for further details. Setup Register 6 3:0 SELDIS[3:0] 0000 Selective power disable register - activated when SELPD = 1. Each bit disables respective cell when 1, enabled when 0. SELDIS[0] = Red CDS, PGA SELDIS[1] = Green CDS, PGA SELDIS[2] = Blue CDS, PGA SELDIS[3] = ADC

w PD Rev 4.1 July 2005 REGISTER BIT NO BIT NAME(S) DEFAULT (Red) 7:0 DAC[7:0] Red channel offset DAC value. Offset DAC (Green) 7:0 DAC[7:0] Green channel offset DAC value Offset DAC (Blue) 7:0 DAC[7:0] Blue channel offset DAC value Offset DAC (RGB) 7:0 DAC[7:0] A write to this register location causes the red, green and blue offset DAC registers to be overwritten by the new value PGA gain (Red) 7:0 PGA[7:0] Determines the gain of the red channel PGA according to the equation: Red channel PGA gain = 208/(283-PGA[7:0]) PGA gain (Green) 7:0 PGA[7:0] Determines the gain of the green channel PGA according to the equation: Green channel PGA gain = 208/(283-PGA[7:0]) PGA gain (Blue) 7:0 PGA[7:0] Determines the gain of the blue channel PGA according to the equation: Blue channel PGA gain = 208/(283-PGA[7:0]) PGA gain (RGB) 7:0 PGA[7:0] A write to this register location causes the red, green and blue PGA gain registers to be overwritten by the new value Table 7 Register Control Bits

w PD Rev 4.1 July 2005 RECOMMENDED EXTERNAL COMPONENTS DVDD1 DVDD2 AGND1 RINP GINP BINP MCLK VSMP RLC/ACYC SEN/STB SDI/DNA SCK/RNW OP[0] OP[1] OP[2] OP[3] OP[4] OP[5] OP[6] OP[7] VRLC/VBIAS VRX VRT VRB C10 Video Inputs Timing Signals Interface Controls Output Data Bus AGND AGND AGND DGND1 AGND2 WM8195 DGND2 DGND3 DGND4 DGND5 AGND3 AGND4 AGND5 45 AGND6 46 OP[8] OP[9] OP[10] OP[11] OP[12] OP[13]/SDO AVDD1 AVDD AGND

35 DVDD3

42 NRESET

11 OEB

C1-10 should be fitted as close to WM8195 as possible. NOTES: AGND1-6 and DGND1-5 should be connected as close to WM8195 as possible. DVDD1-3 should be connected as close to WM8195 as possible. DVDD2, 3 C11 DVDD1 C12 DVDD2, 3 C13 AVDD1, 2 AGND Figure 27 External Components Diagram COMPONENT REFERENCE SUGGESTED VALUE De-coupling for DVDD1. 100nF De-coupling for DVDD2. 100nF De-coupling for DVDD3. 100nF De-coupling for AVDD1 and AVDD2. 10nF High frequency de-coupling between VRT and VRB. 1µF Low frequency de-coupling between VRT and VRB (non-polarised). 100nF De-coupling for VRB. 100nF De-coupling for VRX. 100nF De-coupling for VRT. C10 100nF De-coupling for VRLC. C11 1µF Reservoir capacitor for DVDD1. C12 1µF Reservoir capacitor for DVDD2 and DVDD3. C13 1µF Reservoir capacitor for AVDD1 and AVDD2. Table 8 External Components Descriptions

w PD Rev 4.1 July 2005 PACKAGE DIMENSIONS NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = ABC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. DM004.C FT: 48 PIN TQFP (7 x 7 x 1.0 mm) Symbols Dimensions (mm) MIN NOM MAX A ----- ----- 1.20 0.05 ----- 0.15 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 ----- 0.20 D

9.00 BSC

7.00 BSC

E e

0.50 BSC

L 0.45 0.60 0.75 ΘΘΘΘ 3.5o Tolerances of Form and Position ccc 0.08 REF: JEDEC.95, MS-026 e b D E A SEATING PLANE ccc C -C- ΘΘΘΘ c L

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