WM8150SCDS/R

WM8150_05 WOLFSON | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 26

Technical content

w WM8150 Single Channel 12-bit CIS/CCD AFE with 4-bit Wide Output WOLFSON MICROELECTRONICS plc w :www.wolfsonmicro.com Production Data, February 2005, Rev 4.1 Copyright 2005 Wolfson Microelectronics plc

DESCRIPTION

The WM8150 is a 12-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors (CIS) at pixel sample rates of up to 8MSPS. The device includes a complete analogue signal processing channel containing Reset Level Clamping, Correlated Double Sampling, Programmable Gain and Offset adjust functions. Internal multiplexers allow fast switching of offset and gain for line-by-line colour processing. The output from this channel is time multiplexed into a high-speed 12-bit Analogue to Digital Converter. The digital output data is available in 4-bit wide multiplexed format. An internal 4-bit DAC is supplied for internal reference level generation. This may be used to reference CIS signals or during Reset Level Clamping to clamp CCD signals. An external reference level may also be supplied. ADC references are generated internally, ensuring optimum performance from the device. Using an analogue supply voltage of 5V, a digital core voltage of 5V, and a digital interface supply of either 5V or 3.3V, the WM8150 typically only consumes 160mW when operating from a single 5V supply.

FEATURES

5V single supply or 5V/3.3V dual supply operation Single channel operation Correlated double sampling Programmable gain (8-bit resolution) Programmable offset adjust (8-bit resolution) Programmable clamp voltage 4-bit wide multiplexed data output format Internally generated voltage references 20-pin SSOP package Serial control interface

APPLICATIONS

Flatbed and sheetfeed scanners USB compatible scanners Multi-function peripherals High-performance CCD sensor interface BLOCK DIAGRAM VRLC/VBIAS VINP SEN VSMP MCLK SDI SCK TIMING CONTROL CL RLC VS RS VRX VRT VRB CDS CONFIGURABLE SERIAL CONTROL INTERFACE 12- BIT ADC AGND1 DGND AVDD DVDD1 OP[0] OP[1] OP[2] OP[3]/SDO AGND2 VREF/BIAS R G B M U X R G B PGA I/P SIGNAL POLARITY ADJUST M U X DATA I/O PORT DVDD2 W WM8150 OFFSET DAC RLC DAC

w PD Rev 4.1 February 2005 TABLE OF CONTENTS

w PD Rev 4.1 February 2005 PIN CONFIGURATION WM8150 VINP DVDD1 VSMP MCLK DGND SEN DVDD2 SDI SCK OP[0] AGND2 VRLC/VBIAS VRX VRT VRB AGND1 AVDD OP[3]/SDO OP[1] OP[2]

ORDERING INFORMATION

(tape and reel) MSL1 260oC WM8150SCDS 0 to 70oC 20-pin SSOP (Pb-free) MSL1 260oC WM8150SCDS/R 0 to 70oC 20-pin SSOP (Pb-free, tape and reel) MSL1 260oC Note: Reel quantity = 2,000

w PD Rev 4.1 February 2005 PIN DESCRIPTION PIN NAME TYPE Analogue ground (0V). DVDD1 Supply Digital core (logic and clock generator) supply (5V) VSMP Digital input Video sample synchronisation pulse. MCLK Digital input Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or any multiple of 2 thereafter depending on input sample mode). DGND Supply Digital ground (0V). SEN Digital input Enables the serial interface when high. DVDD2 Supply Digital supply (5V/3.3V), all digital I/O pins. SDI Digital input Serial data input. SCK Digital input Serial clock. Digital multiplexed output data bus. ADC output data (d11:d0) is available in 4-bit multiplexed format as shown below. A B C D OP[0] Digital output OVRNG OP[1] Digital output CC0 OP[2] Digital output d10 CC1 OP[3]/SDO Digital output d11 Alternatively, pin OP[3]/SDO may be used to output register read-back data when address bit 4=1 and SEN has been pulsed high. See Serial Interface description in Device Description section for further details. AVDD Supply Analogue supply (5V) AGND1 Supply Analogue ground (0V). VRB Analogue output Lower reference voltage. This pin must be connected to AGND via a decoupling capacitor. VRT Analogue output Upper reference voltage. This pin must be connected to AGND via a decoupling capacitor. VRX Analogue output Input return bias voltage. This pin must be connected to AGND via a decoupling capacitor. VRLC/VBIAS Analogue I/O Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be connected to AGND via a decoupling capacitor. VRLC can be externally driven if programmed Hi-Z. VINP Analogue input Video input.

w PD Rev 4.1 February 2005 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION MIN MAX Analogue supply voltage: AVDD GND - 0.3V GND + 7V Digital core voltage: DVDD1 GND - 0.3V GND + 7V Digital IO supply voltage: DVDD2 GND - 0.3V GND + 7V Digital ground: DGND GND - 0.3V GND + 0.3V Analogue grounds: AGND1 − 2 GND - 0.3V GND + 0.3V Digital inputs, digital outputs and digital I/O pins GND - 0.3V DVDD2 + 0.3V Analogue input (VINP) GND - 0.3V AVDD + 0.3V Other pins GND - 0.3V AVDD + 0.3V Operating temperature range: TA 0°C +70°C Storage temperature after soldering -65°C +150°C Notes: GND denotes the voltage of any ground pin. AGND1, AGND2 and DGND pins are intended to be operated at the same potential. Differential voltages between these pins will degrade performance. RECOMMENDED OPERATING CONDITIONS CONDITION SYMBOL MIN TYP MAX UNITS Operating temperature range TA Analogue supply voltage AVDD 4.75 5.0 5.25 V Digital core supply voltage DVDD1 4.75 5.0 5.25 V 5V I/O DVDD2 4.75 5.0 5.25 V Digital I/O supply voltage 3.3V I/O DVDD2 2.97 3.3 3.63 V

w PD Rev 4.1 February 2005

ELECTRICAL CHARACTERISTICS

AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 16MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Overall System Specification (including 12-bit ADC, PGA, Offset and CDS functions) Full-scale input voltage range (see Note 1) Max Gain Min Gain 0.30 3.22 Vp-p Vp-p Input signal limits (see Note 2) VIN VDD V Full-scale transition error Gain = 0dB; PGA[7:0] = 07(hex) -50 +50 mV Zero-scale transition error Gain = 0dB; PGA[7:0] = 07(hex) -50 +50 mV Differential non-linearity DNL 0.5 LSB Integral non-linearity INL LSB Total output noise Min Gain Max Gain 0.25 0.70 LSB rms LSB rms References Upper reference voltage VRT 2.70 V Lower reference voltage VRB 1.45 V Input return bias voltage VRX 1.55 1.65 1.75 V Diff. reference voltage (VRT-VRB) VRTB 1.15 1.25 1.35 V Output resistance VRT, VRB, VRX Ω VRLC/Reset-Level Clamp (RLC) RLC switching impedance 100 Ω VRLC short-circuit current 1.86 4.5 mA VRLC output resistance Ω VRLC Hi-Z leakage current VRLC = 0 to AVDD µA RLCDAC resolution bits RLCDAC step size, RLCDAC = 0 VRLCSTEP AVDD = 5.0V 0.23 0.25 0.27 V/step RLCDAC step size, RLCDAC = 1 VRLCSTEP 0.14 0.16 0.20 V/step RLCDAC output voltage at code 0(hex), RLCDACRNG = 0 VRLCBOT AVDD = 5.0V 0.34 0.39 0.44 V RLCDAC output voltage at code 0(hex), RLCDACRNG = 1 VRLCBOT 0.20 0.26 0.31 V RLCDAC output voltage at code F(hex) RLCDACRNG, = 0 VRLCTOP AVDD = 5.0V 4.0 4.16 4.3 V RLCDAC output voltage at code F(hex), RLCDACRNG = 1 VRLCTOP 2.56 2.66 2.76 V Offset DAC, Monotonicity Guaranteed Resolution bits Differential non-linearity DNL 0.1 0.5 LSB Integral non-linearity INL 0.25 LSB Step size 2.04 mV/step Output voltage Code 00(hex) Code FF(hex) -247 +247 -260 +260 -273 +273 mV mV Notes: Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC input range. Input signal limits are the limits within which the full-scale input voltage signal must lie.

w PD Rev 4.1 February 2005 Test Conditions AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 16MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Programmable Gain Amplifier Resolution bits Gain equation 255 7.57 PGA[7 0.78 V/V Max gain GMAX 6.8 8.35 8.7 V/V Min gain GMIN 0.75 0.78 0.82 V/V Gain error Internal channel offset VOFF mV Analogue to Digital Converter Resolution bits Maximum Speed MSPS Full-scale input range (2*(VRT-VRB)) VFS 2.5 V DIGITAL SPECIFICATIONS Digital Inputs High level input voltage VIH 0.8 ∗ DVDD2 V Low level input voltage VIL 0.2 ∗ DVDD2 V High level input current IIH µA Low level input current IIL µA Input capacitance CI pF Digital Outputs High level output voltage VOH IOH = 1mA DVDD2 - 0.5 V Low level output voltage VOL IOL = 1mA 0.5 V Supply Currents Total supply current − active mA Total analogue AVDD, supply current − active IAVDD mA Total digital core, DVDD1, supply current − active IDVDD1 1.7 mA Digital I/O supply current, DVDD2 − active (see note 3) IDVDD2 mA Supply current − full power down mode 300 400 µA Notes: Digital I/O supply current depends on the capacitive load attached to the pin. The Digital I/O supply current is measured with approximately 50pF attached to the pin.

w PD Rev 4.1 February 2005 SERIAL INTERFACE SCK SDI SEN SDO tSPER tSCKL tSCKH tSSU tSH tSCE tSEW tSEC tSERD tSCRD MSB LSB t SCRDZ ADC DATA ADC DATA REGISTER DATA Figure 3 Serial Interface Timing Test Conditions VDD = 5.0, DVDD = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 16MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS SCK period tSPER 83.3 ns SCK high tSCKH 37.5 ns SCK low tSCKL 37.5 ns SDI set-up time tSSU ns SDI hold time tSH ns SCK to SEN set-up time tSCE ns SEN to SCK set-up time tSEC ns SEN pulse width tSEW ns SEN low to SDO = Register data tSERD ns SCK low to SDO = Register data tSCRD ns SCK low to SDO = ADC data tSCRDZ ns Note: Parameters are measured at 50% of the rising/falling edge

w PD Rev 4.1 February 2005 DEVICE DESCRIPTION INTRODUCTION A block diagram of the device showing the signal path is presented on Page 1. The WM8150 processes the sampled video signal on VINP with respect to the video reset level or an internally/externally generated reference level through the analogue processing channel. This processing channel consists of an Input Sampling block with optional Reset Level Clamping (RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and an 8-bit Programmable Gain Amplifier (PGA). The ADC then converts each resulting analogue signal to a 12-bit digital word. The digital output from the ADC is presented on a 4-bit wide bus. On-chip control registers determine the configuration of the device, including the offsets and gains applied to each channel. These registers are programmable via a serial interface. INPUT SAMPLING The WM8150 has a single analogue processing channel and ADC which can be used in a flexible manner to process both monochrome and line-by-line colour inputs. Monochrome: VINP is sampled, processed by the analogue channel, and converted by the ADC. The same offset DAC and PGA register values are always applied. Colour Line-by-Line: VINP is sampled and processing by the analogue channel before being converted by the ADC. The gains and offset register values applied to the PGA and offset DAC can be switched between the independent Red, Green and Blue digital registers (e.g. Red → Green→ Blue → Red…) at the start of each line in order to facilitate line-by-line colour operation. The INTM[1:0] bits determine which register contents are applied (see Table 1) to the PGA and offset DAC. By using the INTM[1:0] bits to select the desired register values only one register write is required at the start of each new colour line. RESET LEVEL CLAMPING (RLC) To ensure that the signal applied to the WM8150 VINP pin lies within the valid input range (0V to VDD) the CCD output signal is usually level shifted by coupling through a capacitor, CIN. When active, the RLC circuit clamps the WM8150 side of this capacitor to a suitable voltage during the CCD reset period. The RLCINT register bit controls is used to activate the Reset Level Clamp circuit. A typical input configuration is shown in Figure 4. The Timing Control Block generates an internal clamp pulse, CL, from MCLK and VSMP (when RLCINT is high). When CL is active the voltage on the WM8150 side of CIN, at VINP, is forced to the VRLC/VBIAS voltage (VVRLC) by closing of switch 1. When the CL pulse turns off switch 1 opens, the voltage at VINP initially remains at VVRLC but any subsequent variation in sensor voltage (from reset to video level) will couple through CIN to VINP. RLC is compatible with both CDS and non-CDS operating modes, as selected by switch 2. Refer to the CDS/non-CDS Processing section.

w PD Rev 4.1 February 2005 VVRLC VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC. OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST The resultant signal V1 is added to the Offset DAC output. PGA NODE: GAIN ADJUST The signal is then multiplied by the PGA gain, ADC BLOCK: ANALOGUE-DIGITAL CONVERSION The analogue signal is then converted to a 12-bit unsigned number, with input range configured by PGAFS[1:0]. where the ADC full-scale range, VFS = 2.5V if D1[11:0] < 0 D1[11:0] = 0 if D1[11:0] > 4095 D1[11:0] = 4095 OUTPUT INVERT BLOCK: POLARITY ADJUST The polarity of the digital output may be inverted by control bit INVOP.

w PD Rev 4.1 February 2005 REFERENCES The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin VRLC/VBIAS when this is configured as an output. POWER SUPPLY The WM8150 can run from a 5V single supply or from split 5V (core) and 3.3V (digital interface) supplies. POWER MANAGEMENT Power management for the device is performed via the Control Interface. The device can be powered on or off completely by setting the EN bit low. All the internal registers maintain their previously programmed value in power down mode and the Control Interface inputs remain active. OPERATING MODES Table 3 summarises the most commonly used modes, the clock waveforms required and the register contents required for CDS and non-CDS operation. MODE

CONTENTS

2.67MSPS MCLK max = 16MHz MCLK:VSMP ratio is 6:1 SetReg1: 0F(hex) SetReg1: 0D(hex) Fast Monochrome/ Colour Line-by-Line Yes 5.33MSPS MCLK max = 16MHz MCLK:VSMP ratio is 3:1 Identical to Mode 1 plus SetReg3: bits 5:4 must be set to 0(hex) Identical to Mode 1 Maximum speed Monochrome/ Colour Line-by-Line No 8MSPS MCLK max = 16MHz MCLK:VSMP ratio is 2:1 CDS not possible SetReg1: 4D(hex) Slow Monochrome/ Colour Line-by-Line Yes 2MSPS MCLK max = 16MHz MCLK:VSMP ratio is 2n:1, n ≥ 4 Identical to Mode 1 Identical to Mode 1 Table 3 WM8150 Operating Modes

w PD Rev 4.1 February 2005 OPERATING MODE TIMING DIAGRAMS The following diagrams show 4-bit multiplexed output data and MCLK, VSMP and input video requirements for operation of the most commonly used modes as shown in Table 3. The diagrams are identical for both CDS and non-CDS operation. MCLK VSMP VINP OP[3:0] (DEL = 00) OP[3:0] (DEL = 01) OP[3:0] (DEL = 10) OP[3:0] (DEL = 11)

16.5 MCLK PERIODS

A B C D A B C D A B C D A B C D A B C D A B C A B C A B C D A B C D A B C A B C A B C A B C D A B C D A B C D A B C D A B C D D D D A B C D D D D D Figure 15 Mode 1 Operation MCLK VSMP (DEL = 00) VINP OP[3:0] (DEL = 01) OP[3:0] (DEL = 10) OP[3:0] (DEL = 11)

23.5 MCLK PERIODS

OP[3:0] C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D C D A B A B C D A B A B C D A B A B Figure 16 Mode 2 Operation

w PD Rev 4.1 February 2005 MCLK VSMP VINP OP[3:0] (DEL = 00) OP[3:0] (DEL = 01) OP[3:0] (DEL = 10) OP[3:0] (DEL = 11) A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D Figure 17 Mode 3 Operation OP[3:0] (DEL = 00) OP[3:0] (DEL = 01) OP[3:0] (DEL = 10) OP[3:0] (DEL = 11) A B C A B C A B C D A B C A B C A B C D A B C A B C A B C D A B C A B C A B C A B C D D D D D D D D D D D D D Figure 18 Mode 4 Operation (MCLK:VSMP Ratio = 8:1)

w PD Rev 4.1 February 2005 DEVICE CONFIGURATION REGISTER MAP The following table describes the location of each control bit used to determine the operation of the WM8150. The register map is programmed by writing the required codes to the appropriate addresses via the serial interface. BIT ADDRESS <a5:a0> (hex) RW 000001 Setup Reg 1 RW MODE3 PGAFS[1] PGAFS[0] CDS EN 000010 Setup Reg 2 RW DEL[1] DEL[0] RLCDACRNG VRLCEXT INVOP 000011 Setup Reg 3 RW CDSREF [1] CDSREF [0] RLCV[3] RLCV[2] RLCV[1] RLCV[0] 000100 Software Reset W 000110 Setup Reg 4 RW INTM[1] INTM[0] RLCINT 000111 Revision Number R 001000 Setup Reg 5 RW POSNNEG VDEL[2] VDEL[1] VDEL[0] VSMPDET 001001 Test Reg 1 RW TCLK 001010 Reserved RW 001011 Reserved RW 001100 Reserved RW 100000 DAC Value (Red) RW DACR[7] DACR[6] DACR[5] DACR[4] DACR[3] DACR[2] DACR[1] DACR[0] 100001 DAC Value (Green) RW DACG[7] DACG[6] DACG[5] DACG[4] DACG[3] DACG[2] DACG[1] DACG[0] 100010 DAC Value (Blue) RW DACB[7] DACB[6] DACB[5] DACB[4] DACB[3] DACB[2] DACB[1] DACB[0] 100011 DAC Value (RGB) W DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0] 101000 PGA Gain (Red) RW PGAR[7] PGAR[6] PGAR[5] PGAR[4] PGAR[3] PGAR[2] PGAR[1] PGAR[0] 101001 PGA Gain (Green) RW PGAG[7] PGAG[6] PGAG[5] PGAG[4] PGAG[3] PGAG[2] PGAG[1] PGAG[0] 101010 PGA Gain (Blue) RW PGAB[7] PGAB[6] PGAB[5] PGAB[4] PGAB[3] PGAB[2] PGAB[1] PGAB[0] 101011 PGA Gain (RGB) W PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0] Table 4 Register Map

w PD Rev 4.1 February 2005 REGISTER MAP DESCRIPTION The following table describes the function of each of the control bits shown in Table 4. REGISTER BIT NO BIT NAME(S) DEFAULT 0 = complete power down, 1 = fully active. CDS Select correlated double sampling mode: 0 = single ended mode, 1 = CDS mode. Offsets PGA output to optimise the ADC range for different polarity sensor output signals. Zero differential PGA input signal gives: 5:4 PGAFS[1:0] 00 = Zero output (use for bipolar video) 01 = Zero output 10 = Full-scale positive output (use for negative going video) 11 = Full-scale negative output (use for positive going video) Setup Register 1 MODE3 Required when operating in MODE3: 0 = other modes, 1 = MODE3. INVOP Digitally inverts the polarity of output data. 0 = negative going video gives negative going output, 1 = negative-going video gives positive going output data. VRLCEXT When set powers down the RLCDAC, changing its output to Hi-Z, allowing VRLC/VBIAS to be externally driven. RLCDACRNG Sets the output range of the RLCDAC. 0 = RLCDAC ranges from 0 to VDD (approximately), 1 = RLCDAC ranges from 0 to VRT (approximately). Sets the output latency in ADC clock periods.

1 ADC clock period = 2 MCLK periods except in Mode 2 where 1 ADC

clock period = 3 MCLK periods. Setup Register 2 7:6 DEL[1:0] 00 = Minimum latency 01 = Delay by one ADC clock period 10 = Delay by two ADC clock periods 11 = Delay by three ADC clock periods 3:0 RLCV[3:0] 1111 Controls RLCDAC driving VRLC pin to define single ended signal reference voltage or Reset Level Clamp voltage. See Electrical Characteristics section for ranges. CDS mode reset timing adjust. Setup Register 3 5:4 CDSREF[1:0] 00 = Advance 1 MCLK period 01 = Normal 10 = Retard 1 MCLK period 11 = Retard 2 MCLK periods Software Reset Any write to Software Reset causes all cells to be reset. It is recommended that a software reset be performed after a power-up before any other register writes. RLCINT This bit is used to determine whether Reset Level Clamping is enabled. 0 = RLC disabled, 1 = RLC enabled. Setup Register 4 5:4 INTM[1:0] Colour selection bits used in internal modes. 00 = Red, 01 = Green, 10 = Blue and 11 = Reserved. See Table 1 for details.

w PD Rev 4.1 February 2005 REGISTER BIT NO BIT NAME(S) DEFAULT 0 = Normal operation, signal on VSMP input pin is applied directly to Timing Control block. 1 = Programmable VSMP detect circuit is enabled. An internal synchronisation pulse is generated from signal applied to VSMP input pin and is applied to Timing Control block. 3:1 VDEL[2:0] 000 When VSMPDET = 0 these bits have no effect. When VSMPDET = 1 these bits set a programmable delay from the detected edge of the signal applied to the VSMP pin. The internally generated pulse is delayed by VDEL MCLK periods from the detected edge. See Figure 14, Internal VSMP Pulses Generated for details. Setup Register 5 POSNNEG When VSMPDET = 0 this bit has no effect. When VSMPDET = 1 this bit controls whether positive or negative edges are detected: 0 = Negative edge on VSMP pin is detected and used to generate internal timing pulse. 1 = Positive edge on VSMP pin is detected and used to generate internal timing pulse. See Figure 14 for further details. 0 = Normal Operation, OP[3:0] output ADC data. 1 = Internal Clock Test Mode. This allows internal timing signals to be multiplexed onto the OP[3:0] pins as follows. PIN TCLK=0 TCLK=1 OP[3] OP[3] INTVSMP OP[2] OP[2] Video sample clock OP[1] OP[1] ADC clock Test Register 1 TCLK OP[0] OP[0] Reset sample clock Offset DAC (Red) 7:0 DACR[7:0] Red channel offset DAC value. Used under control of the INTM[1:0] control bits. Offset DAC (Green) 7:0 DACG[7:0] Green channel offset DAC value. Used under control of the INTM[1:0] control bits. Offset DAC (Blue) 7:0 DACB[7:0] Blue channel offset DAC value. Used under control of the INTM[1:0] control bits. Offset DAC (RGB) 7:0 DAC[7:0] A write to this register location causes the red, green and blue offset DAC registers to be overwritten by the new value PGA gain (Red) 7:0 PGAR[7:0] Determines the gain of the red channel PGA according to the equation: Red channel PGA gain = [0.78+(PGAR[7:0]*7.57)/255]. Used under control of the INTM[1:0] control bits. PGA gain (Green) 7:0 PGAG[7:0] Determines the gain of the green channel PGA according to the equation: Green channel PGA gain = [0.78+(PGAG[7:0]*7.57)/255]. Used under control of the INTM[1:0] control bits. PGA gain (Blue) 7:0 PGAB[7:0] Determines the gain of the blue channel PGA according to the equation: Blue channel PGA gain = [0.78+(PGAB[7:0]*7.57)/255]. Used under control of the INTM[1:0] control bits. PGA gain (RGB) 7:0 PGA[7:0] A write to this register location causes the red, green and blue PGA gain registers to be overwritten by the new value Table 5 Register Control Bits

w PD Rev 4.1 February 2005 RECOMMENDED EXTERNAL COMPONENTS DVDD2 AGND1 VINP MCLK VSMP SCK SEN SDI OP[0] OP[1] OP[2] OP[3]/SDO VRLC/VBIAS VRX VRT VRB AVDD AVDD Video Input Timing Signals Interface Controls Output Data Bus DGND AGND AGND AGND DGND AGND AGND2 C10 C12 AVDD DGND AGND DVDD2 C11 DGND DVDD1 WM8150 C1-9 should be fitted as close to WM8150 as possible. NOTES: AGND and DGND should be connected as close to WM8150 as possible. DVDD2 DGND DVDD1 DVDD1 Figure 19 External Components Diagram COMPONENT REFERENCE SUGGESTED VALUE De-coupling for DVDD2. 100nF De-coupling for DVDD1. 100nF De-coupling for AVDD. 10nF High frequency de-coupling between VRT and VRB. 1µF Low frequency de-coupling between VRT and VRB (non-polarised). 100nF De-coupling for VRB. 100nF De-coupling for VRX. 100nF De-coupling for VRT. 100nF De-coupling for VRLC. C10 10µF Reservoir capacitor for DVDD2. C11 10µF Reservoir capacitor for DVDD1. C12 10µF Reservoir capacitor for AVDD. Table 6 External Components Descriptions

w PD Rev 4.1 February 2005 PACKAGE DIMENSIONS NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. DM0015.B DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm) Symbols Dimensions (mm) MIN NOM MAX A ----- ----- 2.0 0.05 ----- ----- 1.65 1.75 1.85 b 0.22 0.30 0.38 c 0.09 ----- 0.25 D 6.90 7.20 7.50 e

0.65 BSC

E 7.40 7.80 8.20 5.00 5.30 5.60 L 0.55 0.75 0.95 θθθθ REF: A A2 SEATING PLANE -C- 0.10 C D e b E JEDEC.95, MO 150

0.125 REF

ΘΘΘΘ c L GAUGE PLANE 0.25 L 1

w PD Rev 4.1 February 2005 IMPORTANT NOTICE Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s approval, license, warranty or endorsement thereof. Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. ADDRESS: Wolfson Microelectronics plc Westfield House

26 Westfield Road

Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com