WM8150CDSR

WM8150 WOLFSON | Alldatasheet

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Technical content

Single Channel 12-bitCIS/CCDAFEwith4-bitWide Output WOLFSONMICROELECTRONICS plc w :: www.wolfsonmicro.com Production Data, November 2002, Rev 3.0 Copyright 2002 Wolfson Microelectronics plc

DESCRIPTION

The WM8150 is a 12-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors (CIS) at pixel s a mp l er a t e so fu pto8 M S P S . The device includes a complete analogue signal processing channel containing Reset Level Clamping, Correlated Double Sampling, Programmable Gain and Offset adjust functions. Internal multiplexers allow fast switching of offset and gain for line-by-line colour processing. The output from this channel is time multiplexed into a high-speed 12-bit Analogue to Digital Converter. The digital output data is available in 4-bit wide multiplexed format. An internal 4-bit DAC is supplied for internal reference level generation. This may be used during CDS to reference CIS signals or during Reset Level Clamping to clamp CCD signals. An external reference level may also be supplied. ADC references are generated internally, ensuring optimum performance from the device. Using an analogue supply voltage of 5V, a digital core voltage of 5V, and a digital interface supply of either 5V or 3.3V, the WM8150 typically only consumes 160mW when operating from a single 5V supply.

FEATURES

• 12-bit ADC
• 8MSPS conversion rate
• Low power - 170mW typical
• 5V single supply or 5V/3.3V dual supply operation
• Single channel operation
• Correlated double sampling
• Programmable gain (8-bit resolution)
• Programmable offset adjust (8-bit resolution)
• Programmable clamp voltage
• 4-bit wide multiplexed data output format
• Internally generated voltage references
• 20-pin SSOP package
• Serial control interface

APPLICATIONS

• Flatbed and sheetfeed scanners
• USB compatible scanners
• Multi-function peripherals
• High-performance CCD sensor interface BLOCKDIAGRAM VRLC/VBIAS VINP SEN VSMP MCLK SDI SCK TIMINGCONTROLCL RLC VSRS VRXVRT VRB CDS CONFIGURABLE SERIAL CONTROL INTERFACE 12- BIT ADC AGND1 DGND AVDD DVDD1 OP[0] OP[1] OP[2] OP[3]/SDO AGND2 VREF/BIAS R G B M U X R G B PGA I/PSIGNAL POLARITY ADJUST M U X DATA I/O PORT DVDD2 W WM8150 OFFSET DAC RLC DAC

w PD Rev 3.0 November 2002 PINCONFIGURATION ORDERING INFORMATION DEVICE TEMP. RANGE PACKAGE WM8150CDS 0 to 70 oC 20-pin SSOP WM8150CDS/R 0 to 70 oC 20-pin SSOP (tape and reel) WM8150 1V I N P DVDD1 VSMP MCLK DGND SEN DVDD2 SDI SCK OP[0] AGND2 VRLC/VBIAS VRX VRT VRB AGND1 AVDD OP[3]/SDO OP[1] OP[2] Note: Reel quantity = 2,000 PINDESCRIPTION PIN NAME TYPE DESCRIPTION 1 AGND2 Supply Analogue ground (0V).

2 DVDD1 Supply Digital core (logic and clock generator) supply (5V)

3 VSMP Digital input Video sample synchronisation pulse. 4 MCLK Digital input Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or any multiple of 2 thereafter depending on input sample mode). 5 DGND Supply Digital ground (0V). 6 SEN Digital input Enables the serial interface when high. 7 DVDD2 Supply Digital supply (5V/3.3V), all digital I/O pins. 8 SDI Digital input Serial data input. 9 SCK Digital input Serial clock. Digital multiplexed output data bus. ADC output data (d11:d0) is available in 4-bit multiplexed format as shown below. AB C D

10 OP[0] Digital output d8 d4 d0 OVRNG

11 OP[1] Digital output d9 d5 d1 CC0

12 OP[2] Digital output d10 d6 d2 CC1

13 OP[3]/SDO Digital output d11 d7 d3 0

Alternatively, pin OP[3]/SDO may be used to output register read-back data when address bit 4=1 and SEN has been pulsed high. See Serial Interface description in Device Description section for further details.

14 AVDD Supply Analogue supply (5V)

15 AGND1 Supply Analogue ground (0V). 16 VRB Analogue output Lower reference voltage. This pin must be connected to AGND via a decoupling capacitor. 17 VRT Analogue output Upper reference voltage. This pin must be connected to AGND via a decoupling capacitor. 18 VRX Analogue output Input return bias voltage. This pin must be connected to AGND via a decoupling capacitor. 19 VRLC/VBIAS Analogue I/O Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be connected to AGND via a decoupling capacitor. VRLC can be externally driven if programmed Hi-Z. 20 VINP Analogue input Video input.

w PD Rev 3.0 November 2002 ABSOLUTEMAXIMUMRATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. The WM8150 has been classified as MSL1, which has an unlimited floor life at <30 oC / 85%C Relative Humidity and therefore will not be supplied in moisture barrier bags. CONDITION MIN MAX Analogue supply voltage: AVDD GND - 0.3V G N D+7 V Digital core voltage: DVDD1 GND - 0.3V G N D+7 V Digital IO supply voltage: DVDD2 GND - 0.3V G N D+7 V Digital ground: DGND GND - 0.3V GND + 0.3V Analogue grounds: AGND1− 2 GND - 0.3V GND + 0.3V Digital inputs, digital outputs and digital I/O pins GND - 0.3V DVDD2 + 0.3V Analogue input (VINP) GND - 0.3V AVDD + 0.3V Other pins GND - 0.3V AVDD + 0.3V Operating temperature range: TA 0°C +70°C Storage temperature prior to soldering 30oC max / 85% RH max Storage temperature after soldering -65°C +150°C Package body temperature (soldering, 10 seconds) +260°C Package body temperature (soldering, 2 minutes) +183°C Notes: 1. GND denotes the voltage of any ground pin. 2. AGND1, AGND2 and DGND pins are intended to be operated at the same potential. Differential voltages between these pins will degrade performance. RECOMMENDEDOPERATINGCONDITIONS CONDITION SYMBOLMIN TYP MAX UNITS Operating temperature range TA 07 0 °C Analogue supply voltage AVDD 4.75 5.0 5.25 V Digital core supply voltage DVDD1 4.75 5.0 5.25 V 5V I/O DVDD2 4.75 5.0 5.25 VDigital I/O supply voltage 3.3V I/O DVDD2 2.97 3.3 3.63 V

w PD Rev 3.0 November 2002 ELECTRICALCHARACTERISTICS TestConditions AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA =2 5°C, MCLK = 16MHz unless otherwise stated. PARAMETER SYMBOLTEST CONDITIONS MIN TYP MAX UNIT Overall System Specification (including12-bitADC, PGA, OffsetandCDSfunctions) Full-scale input voltage range (see Note 1) MaxGain Min Gain 0.30 3.22 Vp-p Vp-p Input signal limits (see Note 2) VIN 0V D D V Full-scale transition error Gain = 0dB; PGA[7:0] = 07(hex) -50 10 +50 mV Zero-scale transition error Gain = 0dB; PGA[7:0] = 07(hex) -50 10 +50 mV Differential non-linearity DNL 0.5 1 LSB Integral non-linearity INL 2 5 LSB Total output noise Min Gain MaxGain 0.25 0.70 LSB rms LSB rms References Upper reference voltage VRT 2.70 V Lower reference voltage VRB 1.45 V Input return bias voltage VRX 1.55 1.65 1.75 V Diff. reference voltage (VRT-VRB) VRTB 1.15 1.25 1.35 V Output resistance VRT, VRB, VRX 1 Ω VRLC/Reset-Level Clamp (RLC) RLC switching impedance 20 50 100 Ω VRLC short-circuit current 1.86 2 4.5 mA VRLC output resistance 2 Ω VRLC Hi-Z leakage current VRLC = 0 to AVDD 1 µA RLCDAC resolution 4b i t s RLCDAC step size, RLCDAC = 0 VRLCSTEP AVDD = 5.0V 0.23 0.25 0.27 V/step RLCDAC step size, RLCDAC = 1 VRLCSTEP 0.14 0.16 0.20 V/step RLCDAC output voltage at code 0(hex), RLCDACRNG = 0 VRLCBOT AVDD = 5.0V 0.34 0.39 0.44 V RLCDAC output voltage at code 0(hex), RLCDACRNG = 1 VRLCBOT 0.20 0.26 0.31 V RLCDAC output voltage at code F(hex) RLCDACRNG, = 0 VRLCTOP AVDD = 5.0V 4.0 4.16 4.3 V RLCDAC output voltage at code F(hex), RLCDACRNG = 1 VRLCTOP 2.56 2.66 2.76 V OffsetDAC,MonotonicityGuaranteed Resolution 8b i t s Differential non-linearity DNL 0.1 0.5 LSB Integral non-linearity INL 0.25 1 LSB Step size 2.04 mV/step Output voltage Code 00(hex) Code FF(hex) -247 +247 -260 +260 -273 +273 mV mV Notes: 1. Full-scaleinputvoltage denotes the peak input signal amplitude that can be gained to match the ADC input range. 2. Inputsignallimits are the limits within which the full-scale input voltage signal must lie.

w PD Rev 3.0 November 2002 TestConditions AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA =2 5°C, MCLK = 16MHz unless otherwise stated. PARAMETER SYMBOLTEST CONDITIONS MIN TYP MAX UNIT ProgrammableGainAmplifier Resolution 8b i t s Gain equation 255 Max gain GMAX 6.8 8.35 8.7 V/V Min gain GMIN 0.75 0.78 0.82 V/V Gain error 12 % Internal channel offset VOFF 10 mV Analogueto DigitalConverter Resolution 12 bits Maximum Speed 8 MSPS Full-scale input range (2*(VRT-VRB)) VFS 2.5 V DIGITALSPECIFICATIONS DigitalInputs Highlevel input voltage VIH 0.8 ∗ DVDD2 V Low level input voltage VIL 0.2 ∗ DVDD2 V Highlevel input current IIH 1 µA Low level input current IIL 1 µA Input capacitance CI 5p F DigitalOutputs Highlevel output voltage VOH IOH = 1mA DVDD2 - 0.5 V Low level output voltage VOL IOL =1 m A 0 .5 V SupplyCurrents Total supply current− active 35 45 mA Total analogue AVDD, supply current− active IAVDD 30 40 mA Total digital core, DVDD1, supply current− active IDVDD1 1.7 2 mA Digital I/O supply current, DVDD2− active (see note 3) IDVDD2 45 m A Supply current− full power down mode 300 400 µA Notes: 3. Digital I/O supply current depends on the capacitive load attached to the pin. The Digital I/O supply current is measured with approximately 50pF attached to the pin.

w PD Rev 3.0 November 2002 INPUTVIDEOSAMPLING MCLK VSMP INPUT VIDEO tPER tVSMPSU tVSMPH tVSU tVH tRSU tRH tMCLKLtMCLKH Figure1 InputVideoTiming Note: 1. See Page 15 (Programmable VSMP Detect Circuit) for video sampling description. TestConditions VDD = 5.0V, DVDD = 3.3V, AGND = DGND = 0V, TA=2 5°C, MCLK = 16MHz unless otherwise stated. PARAMETER SYMBOLTESTCONDITIONS MIN TYP MAX UNITS MCLK period tPER 62.5 ns MCLK high period tMCLKH 28.1 ns MCLK lowperiod tMCLKL 28.1 ns VSMP set-uptime tVSMPSU 8n s VSMP hold time tVSMPH 4n s Video level set-up time tVSU 15 ns Video level hold time tVH 5n s Reset level set-up time tRSU 15 ns Reset level hold time tRH 5n s Notes: 1. t VSU and tRSU denote the set-up time required after the input video signal has settled. 2. Parameters are measured at 50% of the rising/falling edge. OUTPUTDATATIMING MCLK OP[3:0] tPD tPD Figure2 OutputDataTiming TestConditions VDD = 5.0V, DVDD = 3.3V, AGND = DGND = 0V, TA=2 5°C, MCLK = 16MHz unless otherwise stated. PARAMETER SYMBOLTESTCONDITIONS MIN TYP MAX UNITS Output propagation delay t PD IOH =1 m A ,IOL =1 m A 3 0 ns

w PD Rev 3.0 November 2002 SERIALINTERFACE SCK SDI SEN SDO tSPER tSCKL tSCKH tSSU tSH tSCE tSEW tSEC tSERD tSCRD MSB LSB tSCRDZ ADC DATA ADC DATA REGISTERDATA Figure3 SerialInterfaceTiming TestConditions V D D=5 . 0 ,D V D D=3 .3 V ,A G N D=D G N D=0 V ,TA =2 5°C, MCLK = 16MHz unless otherwise stated. PARAMETER SYMBOLTESTCONDITIONS MIN TYP MAX UNITS SCK period tSPER 83.3 ns SCK high tSCKH 37.5 ns SCK low t SCKL 37.5 ns SDI set-up time tSSU 10 ns SDI hold time tSH 10 ns SCK to SEN set-up time tSCE 20 ns SEN toSCK set-up time tSEC 20 ns SEN pulse width tSEW 50 ns SEN lowto SDO = Register data tSERD 35 ns SCK lowto SDO = Register data tSCRD 35 ns SCK lowto SDO = ADC data t SCRDZ 25 ns Note: 1. Parameters are measured at 50% of the rising/falling edge

w PD Rev 3.0 November 2002 DEVICEDESCRIPTION INTRODUCTION A block diagram of the device showing the signal path is presented on Page 1. The WM8150 processes the sampled video signal on VINP with respect to the video reset level or an internally/externally generated reference level through the analogue processing channel. This processing channel consists of an Input Sampling block with optional Reset Level Clamping (RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and an 8-bit Programmable Gain Amplifier (PGA). The ADC then converts each resulting analogue signal to a 12-bit digital word. The digital output from the ADC is presented on a 4-bit wide bus. On-chip control registers determine the configuration of the device, including the offsets and gains applied to each channel. These registers are programmable via a serial interface. INPUTSAMPLING The WM8150 has a single analogue processing channel and ADC which can be used in a flexible manner to process bothmonoch rome and line-by-line colour inputs. Monochrome: VINP is sampled, processed by the analogue channel, and converted by the ADC. The same offset DAC and PGA register values are always applied. Colour Line-by-Line: VINP is sampled and processing by the analogue channel before being converted by the ADC. The gains and offset register values applied to the PGA and offset DAC can be switched between the independent Red, Green and Blue digital registers (e.g. Red→ Green→ Blue → Red…) at the start of each line in order to facilitate line-by-line colour operation. The INTM[1:0] bits determine which register contents are applied (see Table 1) to the PGA and offset DAC. By using the INTM[1:0] bits to select the desired register values only one register write is required at the start of each newcolour line. RESETLEVELCLAMPING (RLC) To ensure that the signal applied to the WM8150 VINP pin lies within the valid input range (0V to VDD) the CCD output signal is usually level shifted by coupling through a capacitor, CIN. When active, the RLC circuit clamps the WM8150 side of this capacitor to a suitable voltage during the CCD reset period. The RLCINT register bit controls is used to activate the Reset Level Clamp circuit. A typical input configuration is shown in Figure 4. The Timing Control Block generates a clamp pulse, CL, from MCLK and VSMP (when RLCINT is high). When CL is active the voltage on the WM8150 side of C IN, at VINP, is forced to the VRLC/VBIAS voltage (VVRLC) by switch 1. When the CL pulse turns off, the voltage at VINP initially remains at VVRLC but any subsequent variation in sensor voltage (from reset to video level) will couple through CIN toVINP. RLC is compatible withbothCDS and non-CDS operating modes, as selected by switch2. Refer to the CDS/non-CDS Processing section.

w PD Rev 3.0 November 2002 TIMINGCONTROL S/H 4-BIT RLCDAC CL TOOFFSETDAC RLC CDS FROMCONTROL INTERFACE S/H VSRS FROMCONTROL INTERFACE MCLK VSMP INPUTSAMPLING BLOCK CDS CIN VINP VRLC/ VBIAS EXTERNALVRLC VRLCEXT Figure4 ResetLevel ClampingandCDSCircuitry Reset Level Clamping is controlled by register bit RLCINT. Figure 5 illustrates the effect of the RLCINT bit for a typical CCD waveform, withCL applied during th e reset period. The RLCINT register bit is sampled on the positive edge of MCLK that occurs during each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal CL pulse on the next reset level. The position of CL can be adjusted by using control bits CDSREF[1:0] (Figure 6). MCLK VSMP ACYC/RLC or RLCINT CL (CDSREF= 01) INPUTVIDEO 1X X0 X X 0 RGB RGB No RLC on this PixelRLC on this Pixel Programmable Delay RGB Figure5 Relationship ofRLCINT,MCLKand VSMPtoInternalClampPulse,CL The VRLC/VBIAS pin can be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit RLCDACRNG. Alternatively, the VRLC/VBIAS pin can be driven externally by writing to control bit VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin. CDS/NON-CDSPROCESSING For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel common mode noise. For CDS operation, the video level is processed with respect to the video reset level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must be set to 1 (default), this controls switch 2 (Figure 4) and causes the signal reference to come from the video reset level. The time at which the reset level is sampled, by clock R s/CL, is adjustable by programming control bits CDSREF[1:0], as shown in Figure 6.

w PD Rev 3.0 November 2002 MCLK VSMP VS RS/CL(CDSREF=00) RS/CL(CDSREF=01) RS/CL(CDSREF=10) RS/CL(CDSREF=11) Figure6 ResetSampleandClampTiming For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed withrespect to th e voltage on pin VRLC/VBIAS, generated internally or externally as described above. The VRLC/VBIAS pin is sampled by Rs at the same time as Vs samples the video level in this mode. OFFSETADJUSTANDPROGRAMMABLEGAIN The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset can be set for each of three colours by writing to control bits DACx[7:0] and PGAx[7:0] (where x can be R, G or B). In colour line-by-line mode the gain and offset coefficients that are applied to the PGA and offset DAC can be multiplexed by control of the INTM[1:0] bits as shown in Table 1. INTM[1:0] DESCRIPTION

00 Red offset and gain registers are applied to offset DAC and PGA

(DACR[7:0] and PGAR[7:0])

01 Green offset and gain registers applied to offset DAC and PGA

(DACG[7:0] and PGAG[7:0])

10 Blue offset and gain registers applied to offset DAC and PGA

(DACB[7:0] and PGAB[7:0]) 11 Reserved. Table1 OffsetDACandPGARegisterControl The gain characteristic of the WM8150 PGA is shown in Figure 7. Figure 8 shows the maximum input voltage (at VINP) that can be gained up to match the ADC full-scale input range (2.5V). 0 64 128 192 256 GAINREGISTERVALUE,PGA[7:0] PGAGAINV/V 0.5 1.5 2.5 3.5 0 64 128 192 256 GAINREGISTERVALUE,PGA[7:0] PEAKINPUTVOLTAGETOMATCHADC FULL-SCALE RANGE Figure 7 PGAGain Characteristic Figure 8 PeakInputVoltagetoMatchADCFull-scaleRange

w PD Rev 3.0 November 2002 ADC INPUTBLACK LEVELADJUST The output from the PGA should be offset to match the full-scale range of the ADC (VFS =2 . 5 V ) .F o r negative-going input video signals, a black level (zero differential) output from the PGA should be offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. For positive going input signal the black level should be offset to the bottom of the ADC range by setting PGAFS[1:0]=11. Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01 (zero differential input voltage gives mid-range ADC output). OVERALLSIGNALFLOWSUMMARY Figure 9 represents the processing of the video signal through the WM8150. Figure9 OverallSignalFlow The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC, optionally set via the RLC DAC. The OFFSET DAC BLOCKthen adds the amount of fine offset adjustment required to move the black level of the input signal towards 0V, producingV2. The PGA BLOCKthen amplifies the white level of the input signal to maximise the ADC range, outputting voltageV3. TheADC BLOCKthen converts the analogue signal,V3, to a 12-bit unsigned digital output,D1. The digital output is then inverted, if required, through theOUTPUTINVERTBLOCK to produceD2. CALCULATING OUTPUTFOR ANYGIVEN INPUT The following equations describe the processing of the video and reset level signals through the WM8150. INPUT SAMPLINGBLOCK:INPUT SAMPLINGANDREFERENCING If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the input video. If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted instead. If VRLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS. If VRLCEXT = 0, VVRLC is the output from the internal RLC DAC. V RESET V VRLC V CDS= 1 CDS = 0 VRLCEXT=1 analog- X V RLCSTEP *RLCV[3:0] +V RLCBOT OP[3:0] D digital ADCBLOCKPGA BLOCK OFFSET DAC BLOCK INPUT SAMPLING BLOCK D CDS, VRLCEXT,RLCV[3:0], DAC[7:0], PGA[7:0], PGAFS[1:0] and INVOPare set by programming internal control registers. CDS=1 for CDS, 0 for non-CDS V IN isVINPvolta ge sampled on video sample V RESET is VINP sampled during reset clamp V VRLC is voltageapplied to VRLCpin V IN x(4095/V FS +0 if PGAFS[1:0]=11 +4095 if PGAFS[1:0]=10 +2047 if PGAFS[1:0]=0x PGA gain OUTPUT INVERT BLOCK D2 = D1 if INVOP = 0 D2 =4095-D1 if INVOP = 1 Offset DAC RLC DAC V V VRLCEXT=0

w PD Rev 3.0 November 2002 VRLCSTEP i st hes t eps i z eo ftheR L CD A Ca n dVRLCBOT is the minimum output of the RLC DAC. OFFSET DACBLOCK:OFFSET(BLACK-LEVEL) ADJUST The resultant signalV1 is added to the Offset DAC output. PGANODE:GAINADJUST The signal is then multiplied by the PGA gain, ADCBLOCK:ANALOGUE-DIGITALCONVERSION The analogue signal is then converted to a 12-bit unsigned number, with input range configured by PGAFS[1:0]. where the ADC full-scale range, VFS =2 . 5 V if D1[11:0] > 4095 D1[11:0] = 4095 OUTPUTINVERTBLOCK:POLARITYADJUST The polarity of the digital output may be inverted by control bit INVOP.

w PD Rev 3.0 November 2002 OUTPUTDATAFORMAT The digital data output from the ADC is available to the user in 4-bit wide multiplexed. Latency of valid output data withrespect to VSMP is programmable by writing to control bits DEL[1:0]. Th e latency for each mode is shown in the Operating Mode Timing Diagrams section. Figure 10 shows the output data formats for Mode 1 and 3 – 6. Figure 11 shows the output data formats for Mode 2. Table 2 summarises the output data obtained for each format. MCLK 4+4+4-BIT OUTPUT ABCD MCLK 4+4+4-BIT OUTPUT DAB CDAB Figure10 OutputDataFormats (Modes 1, 3, 4) Figure11 OutputDataFormats (Mode2) OUTPUT FORMAT OUTPUT PINS OUTPUT 4+4+4+4-bit (nibble) OP[3:0] A = d11, d10, d9, d8 B = d7, d6, d5, d4 C = d3, d2, d1, d0 D = 0, CC[1], CC[0], OVRNG Table2 DetailsofOutputDataShowninFigure10andFigure11. FLAGS The OVRNG flag that is output during nibble D indicates that the current output data was produced by an input signal that exceeded the input range limit of the device. 1 = Out of range, 0 = within range. The CC[1:0] flags that are output during nibble D are used to indicate which set of offset and gain registers have been used for the current data. CC[1:0] = 00 indicates Red, CC[1:0] = 01 indicates Green and CC[1:0] = 10 indicates that the Blue offset and gain registers were applied during the processing.

w PD Rev 3.0 November 2002 PROGRAMMABLEVSMPDETECTCIRCUIT The VSMP input is used to determine the sampling point and frequency of the WM8150. Under normal operation a pulse of 1 MCLK period should be applied to VSMP at the desired sampling frequency (as shown in the Operating Mode Timing Diagrams) and the input sample will be taken on the first rising MCLK edge after VSMP has gone low. However, in certain applications such a signal may not be readily available. The programmable VSMP detect circuit in the WM8150 allows the sampling point to be derived from any signal of the correct frequency, such as a CCD shift register clock, when applied to the VSMP pin. When enabled, by setting the VSMPDET control bit, the circuit detects either a rising or falling edge (determined by POSNNEG control bit) on the VSMP input pin and generates an internal VSMP pulse. This pulse can optionally be delayed by a number of MCLK periods, specified by the VDEL[2:0] bits. Figure 14 shows the internal VSMP pulses that can be generated by this circuit for a typical clock input signal. The internal VSMP pulse is then applied to the timing control block in place of the normal VSMP pulse provided from the input pin. The sampling point then occurs on the first rising MCLK edge after this internal VSMP pulse, as shown in the Operating Mode Timing Diagrams. MCLK VSMP (VDEL=000)INTVSMP POSNNEG =1 (VDEL=001)INTVSMP (VDEL=010)INTVSMP (VDEL=011)INTVSMP (VDEL=100)INTVSMP (VDEL=101)INTVSMP (VDEL=110)INTVSMP (VDEL=111)INTVSMP POSNNEG=0 (VDEL=000)INTVSMP (VDEL=001)INTVSMP (VDEL=010)INTVSMP (VDEL=011)INTVSMP (VDEL=100)INTVSMP (VDEL=101)INTVSMP (VDEL=110)INTVSMP (VDEL=111)INTVSMP INPUT PINS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS VS Figure14 InternalVSMPPulsesGeneratedbyProgrammableVSMP DetectCircuit

w PD Rev 3.0 November 2002 REFERENCES The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin VRLC/VBIAS when this is configured as an output. POWER SUPPLY The WM8150 can run from a 5V single supply or from split 5V (core) and 3.3V (digital interface) supplies. POWER MANAGEMENT Power management for the device is performed via the Control Interface. The device can be powered on or off completely by setting the EN bit low. All the internal registers maintain their previously programmed value in power down mode and the Control Interface inputs remain active. OPERATING MODES Table 3 summarises the most commonly used modes, the clock waveforms required and the register contents required for CDS and non-CDS operation. MODE DESCRIPTION CDS AVAILABLE MAX SAMPLE RATE TIMING REQUIREMENTS REGISTER CONTENTSWITH CDS REGISTER

CONTENTS

1 Monochrome/

Yes 2.67MSPS MCLK max = 16MHz MCLK:VSMP ratiois 6:1 SetReg1: 0F(hex) SetReg1: 0D(hex)

2 Fast Monochrome/

Yes 5.33MSPS MCLK max = 16MHz MCLK:VSMP ratiois 3:1 Identical to Mode 1 plus SetReg3: bits 5:4 must be set to 0(hex) Identical to Mode 1

3 Maximum speed

No 8MSPS MCLK max = 16MHz MCLK:VSMP ratiois 2:1 CDS not possible SetReg1: 4D(hex)

4 Slow Monochrome/

Yes 2MSPS MCLK max = 16MHz MCLK:VSMP ratiois 2n:1, n≥ 4 Identical to Mode 1 Identical to Mode 1 Table 3 WM8150 OperatingModes

w PD Rev 3.0 November 2002 OPERATING MODETIMINGDIAGRAMS The following diagrams show 4-bit multiplexed output data and MCLK, VSMP and input video requirements for operation of the most commonly used modes as shown in Table 3. The diagrams are identical for bothCDS and non-CDS operation. MCLK VSMP VINP OP[3:0] (DEL=00) OP[3:0] (DEL=01) OP[3:0] (DEL=10) OP[3:0] (DEL=11) 16.5MCLKPERIODS A B C DA B C DA B C DA B C D A B C DA B CA B CA B C D A B C DA B CA B CA B C A B C DA B C DA B C DA B C DA B C D D D DA B C D D D D D Figure15 Mode1Operation MCLK VSMP (DEL=00) VINP OP[3:0] (DEL=01) OP[3:0] (DEL=10) OP[3:0] (DEL=11) 23.5MCLKPERIODS C DA B A B C DA B A B C DA B A B C DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC DOP[3:0] C DA B A B C DA B A B C DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC D C DA B A B C DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC D C DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC DA B A BC D C DA B A B C DA B A B C DA B A B Figure16 Mode2Operation

w PD Rev 3.0 November 2002 MCLK VSMP VINP OP[3:0] (DEL=00) 16.5MCLKPERIODS OP[3:0] (DEL=01) OP[3:0] (DEL=10) OP[3:0] (DEL=11) A B C D A B C D A B C D A B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C D A B C D A B C D A B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C D A B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C D A B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C DA B C D A B C D A B C D A B C D A B C D A B C D A B C DA B C D A B C D Figure17 Mode3Operation 16.5MCLKPERIODS MCLK VSMP VINP OP[3:0] (DEL=00) OP[3:0] (DEL=01) OP[3:0] (DEL=10) OP[3:0] (DEL=11) A B CA B CA B C D A B CA B C A B C D A B CA B C A B C D A B C A B CA B C A B C D D DD D D D D D D D D D Figure18 Mode4Operation(MCLK:VSMPRatio=8:1)

w PD Rev 3.0 November 2002 DEVICECONFIGURATION REGISTER MAP The following table describes the location of each control bit used to determine the operation of the WM8150. The register map is programmed by writing the required codes to the appropriate addresses via the serial interface. BITADDRESS <a5:a0> DESCRIPTION DEF (hex) RW b7 b6 b5 b4 b3 b2 b1 b0

000001 Setup Reg 1 0F RW 0 MODE3 PGAFS[1] PGAFS[0] 1 1 CDS EN

000010 Setup Reg 2 23 RW DEL[1] DEL[0] RLCDACRNG 0 VRLCEXT INVOP 1 1

000011 Setup Reg 3 1F RW 0 0 CDSREF [1] CDSREF [0] RLCV[3] RLCV[2] RLCV[1] RLCV[0]

000100 Software Reset 00 W

000110 Setup Reg 4 05 RW 0 0 INTM[1] INTM[0] RLCINT 1 0 1

001000 Setup Reg 5 00 RW 0 0 0 POSNNEG VDEL[2] VDEL[1] VDEL[0] VSMPDET

001001 Test Reg 1 00 RW TCLK 0 0 0 0 0 0 0

001010 Reserved 00 RW 0 0 0 0 0 0 0 0

001011 Reserved 00 RW 0 0 0 0 0 0 0 0

001100 Reserved 00 RW 0 0 0 0 0 0 0 0

100000 DAC Value (Red) 80 RW DACR[7] DACR[6] DACR[5] DACR[4] DACR[3] DACR[2] DACR[1] DACR[0]

100001 DAC Value

(Green)

80 RW DACG[7] DACG[6] DACG[5] DACG[4] DACG[3] DACG[2] DACG[1] DACG[0]

100010 DAC Value (Blue) 80 RW DACB[7] DACB[6] DACB[5] DACB[4] DACB[3] DACB[2] DACB[1] DACB[0]

100011 DAC Value (RGB) 80 W DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0]

101000 PGA Gain (Red) 00 RW PGAR[7] PGAR[6] PGAR[5] PGAR[4] PGAR[3] PGAR[2] PGAR[1] PGAR[0]

101001 PGA Gain

(Green)

00 RW PGAG[7] PGAG[6] PGAG[5] PGAG[4] PGAG[3] PGAG[2] PGAG[1] PGAG[0]

101010 PGA Gain (Blue) 00 RW PGAB[7] PGAB[6] PGAB[5] PGAB[4] PGAB[3] PGAB[2] PGAB[1] PGAB[0]

101011 PGA Gain (RGB) 00 W PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0]

w PD Rev 3.0 November 2002 REGISTER MAPDESCRIPTION The following table describes the function of each of the control bits shown in Table 4. REGISTER BIT NO BIT NAME(S) DEFAULT DESCRIPTION 0E N 1 0 = complete power down, 1 = fully active. 1C D S 1 Select correlated double sampling mode: 0 = single ended mode, 1 = CDS mode. Offsets PGA output to optimise the ADC range for different polarity sensor output signals. Zero differential PGA input signal gives: 5:4 PGAFS[1:0] 00 00 = Zero output (use for bipolar video) 01 = Zero output 10 = Full-scale positive output (use for negative going video) 11 = Full-scale negative output (use for positive going video) Setup Register 1 6M O D E 3 0 Required when operating in MODE3: 0 = other modes, 1 = MODE3. 2I N V O P 0 Digitally inverts the polarity of output data. 0 = negative going video gives negative going output, 1 = negative-going video gives positive going output data. 3V R L C E X T 0 When set powers down the RLCDAC, changing its output to Hi-Z, allowing VRLC/VBIAS to be externally driven. 5 RLCDACRNG 1 Sets the output range of the RLCDAC. 0 = RLCDAC ranges from 0 to VDD (approximately), 1 = RLCDAC ranges from 0 to VRT (approximately). Sets the output latency in ADC clock periods.

1 ADC clock period = 2 MCLK periods except in Mode 2 where 1 ADC

clock period = 3 MCLK periods. Setup Register 2 7:6 DEL[1:0] 00 00 = Minimum latency 01 = Delay by one ADC clock period 10 = Delay by two ADC clock periods 11 = Delay by three ADC clock periods 3:0 RLCV[3:0] 1111 Controls RLCDAC driving VRLC pin to define single ended signal reference voltage or Reset Level Clamp voltage. See Electrical Characteristics section for ranges. CDS mode reset timing adjust. Setup Register 3 5:4 CDSREF[1:0] 01 00 = Advance 1 MCLK period 01 = Normal 10 = Retard 1 MCLK period 11 = Retard 2 MCLK periods Software Reset AnywritetoSoftware Reset causes all cells to bereset. It is recommended that a software reset be performed after a power-up before any other register writes. 3R L C I N T 0 This bit is used to determine whether Reset Level Clamping is enabled. 0 = RLC disabled, 1 = RLC enabled. Setup Register 4 5:4 INTM[1:0] 00 Colour selection bits used in internal modes. 00 = Red, 01 = Green, 10 = Blue and 11 = Reserved. See Table 1 for details.

w PD Rev 3.0 November 2002 REGISTER BIT NO BIT NAME(S) DEFAULT DESCRIPTION

0 VSMPDET 0 0 = Normal operation, signal on VSMP input pin is applied directly to

Timing Control block. 1 = Programmable VSMP detect circuit is enabled. An internal synchronisation pulse is generated from signal applied to VSMP input pin and is applied to Timing Control block. 3:1 VDEL[2:0] 000 When VSMPDET = 0 these bits have no effect. When VSMPDET = 1 these bits set a programmable delay from the detected edge of the signal applied to the VSMP pin. The internally generated pulse is delayed by VDEL MCLK periods from the detected edge. See Figure 14, Internal VSMP Pulses Generated for details. Setup Register 5 4 POSNNEG 0 When VSMPDET = 0 this bit has no effect. When VSMPDET = 1 this bit controls whether positive or negative edges are detected: 0 = Negative edge on VSMP pin is detected and used to generate internal timing pulse. 1 = Positive edge on VSMP pin is detected and used to generate internal timing pulse. See Figure 14 for further details. 0 = Normal Operation, OP[3:0] output ADC data. 1 = Internal Clock Test Mode. This allows internal timing signals to be multiplexed onto the OP[3:0] pins as follows. PIN TCLK=0 TCLK=1 OP[3] OP[3] INTVSMP OP[2] OP[2] Video sample clock OP[1] OP[1] ADC clock Test Register 1 7T C L K 0 OP[0] OP[0] Reset sample clock Offset DAC (Red) 7:0 DACR[7:0] 80 Red channel offset DAC value. Used under control of the INTM[1:0] control bits. Offset DAC (Green) 7:0 DACG[7:0] 80 Green channel offset DAC value. Used under control of the INTM[1:0] control bits. Offset DAC (Blue) 7:0 DACB[7:0] 80 Blue channel offset DAC value. Used under control of the INTM[1:0] control bits. Offset DAC (RGB) 7:0 DAC[7:0] A write to this register location causes the red, green and blue offset DAC registers to be overwritten by the newvalue PGA gain (Red) 7:0 PGAR[7:0] 0 Determines the gain of the red channel PGA according to the equation: Red channel PGA gain = [0.78+(PGAR[7:0]*7.57)/255]. Used under control of the INTM[1:0] control bits. PGA gain (Green) 7:0 PGAG[7:0] 0 Determines the gain of the green channel PGA according to the equation: Green channel PGA gain = [0.78+(PGAG[7:0]*7.57)/255]. Used under control of the INTM[1:0] control bits. PGA gain (Blue) 7:0 PGAB[7:0] 0 Determines the gain of the blue channel PGA according to the equation: Blue channel PGA gain = [0.78+(PGAB[7:0]*7.57)/255]. Used under control of the INTM[1:0] control bits. PGA gain (RGB) 7:0 PGA[7:0] A write to this register location causes the red, green and blue PGA gain registers to be overwritten by the newvalue Table5 RegisterControlBits

w PD Rev 3.0 November 2002 RECOMMENDEDEXTERNALCOMPONENTS DVDD2 AGND1 VINP MCLK VSMP SCK SEN SDI OP[0] OP[1] OP[2] OP[3]/SDO VRLC/VBIAS VRX VRT VRB AVDD C6 C8 C4 C5 AVDD Video Input Timing Signals Interface Controls Output Data Bus DGND AGND AGND AGND DGND AGND AGND2 C10 C12 AVDD DGND AGND DVDD2 C11+ DGND DVDD1 WM8150 C1-9 should be fitted as close to WM8150 aspossible.NOTES: AGND and DGND should be connected asclose to WM8150 as possible. DVDD2 DGND DVDD1 DVDD1 Figure19 ExternalComponentsDiagram COMPONENT REFERENCE SUGGESTED VALUE C1 100nF De-coupling for DVDD2. C2 100nF De-coupling for DVDD1. C3 100nF De-coupling for AVDD. C4 10nF Highfrequency de-coupling between VRT and VRB. C5 1 µF Lowfrequency de-coupling between VRT and VRB (non-polarised). C6 100nF De-coupling for VRB. C7 100nF De-coupling for VRX. C8 100nF De-coupling for VRT. C9 100nF De-coupling for VRLC. C10 10 µF Reservoir capacitor for DVDD2. C11 10 µF Reservoir capacitor for DVDD1. C12 10 µF Reservoir capacitor for AVDD. Table 6 External ComponentsDescriptions

w PD Rev 3.0 November 2002 PACKAGEDIMENSIONS NOTES: A. ALLLINEARDIMENSIONSAREIN MILLIMETERS. B. THISDRAWINGISSUBJECTTOCHANGEWITHOUTNOTICE. C. BODY DIMENSIONS DO NOTINCLUDEMOLDFLASH ORPROTRUSION, NOTTO EXCEED0.20MM. D. MEETSJEDEC.95MO-150,VARIATION=AE. REFERTOTHISSPECIFICATIONFOR FURTHERDETAILS. DM0015.BDS:20PINSSOP (7.2x5.3x1.75mm) Symbols Dimensions (mm) MIN NOM MAX A ----- ----- 2.0 A2 1.65 1.75 1.85 b 0.22 0.30 0.38 c 0.09 ----- 0.25 D 6.90 7.20 7.50 e 0.65 BSC E 7.40 7.80 8.20 5.00 5.30 5.60 L 0.55 0.75 0.95 θθθθ REF: A A2 A1 SEATINGPLANE -C- 0.10 C 101 D 1120 eb E1 E -JEDEC.95, MO150 0o 4o 8o L1 0.125 REF ΘΘΘΘ c L GAUGE PLANE 0.25

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