WM8141

WM8141 WOLFSON | Alldatasheet

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12-bit 6MSPS CIS/CCD Analogue Front End/Digitiser Production Data, October 2000, Rev 3.0 WOLFSON MICROELECTRONICS LTD Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk http://www.wolfson.co.uk Production Data Datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics’ Terms and Conditions.  2000 Wolfson Microelectronics Ltd.

DESCRIPTION

The WM8141 is a 12-bit analogue front end/digitiser that processes and digitises the analogue output signals from CCDs or Contact Image Sensors (CIS). The device can be operated as either a three channel or a single channel device at pixel sample rates of up to 6MSPS. The device has both external and programmable internal black level reference options for CIS operation. The WM8141 runs off a single supply voltage of either 3.3V or 5V. Alternatively, the device can be operated from split 5V core and 3.3V digital interface supplies. The WM8141 includes three analogue signal processing channels each of which contains reset level clamping, correlated double sampling and programmable offset and gain adjust facilities. Each of these channels is time multiplexed into a single high-speed 12-bit resolution ADC, which digitises the pixel image information. The digital data output is available to the user in either 12-bit parallel or 8/6/4-bit wide multiplexed formats. The internal control registers are programmable via a convenient serial or parallel digital interface. The WM8141 typically consumes only 45mA and less than 10µA when in power down mode.

FEATURES

• 12-bit resolution ADC
• 6MSPS conversion rate at 5V supply
• 5V or 3.3V single supply or 5V/3.3V dual supply operation
• Single or 3 channel operation
• Correlated double sampling
• Programmable gain (8-bit resolution)
• Programmable offset adjust (8-bit resolution)
• 12-bit parallel or 8/6/4-bit wide multiplexed output bus
• Internally generated voltage references
• External or internal reference for CIS operation
• Low power – 225mW typical at 5V supply
• Interface and timing compatible with WM8143, WM8144 and WM8142 devices
• Drop in replacement for WM8143-12
• 32-pin TQFP package

APPLICATIONS

• Flatbed and sheetfeed scanners
• USB compatible scanners
• Multi-function peripherals
• CCD sensor interface
• Contact image sensor (CIS) interface BLOCK DIAGRAM M U X RINP (21) DATA I/O PORT (23) SEN/STB VSMP (27) MCLK (28) VRLC/VBIAS (18) (24) SDI/DNA (25) SCK/RNW DVDD2 (32) TIMING CONTROLCL (26) RLC/ACYC RLC VSR S BINP (19) GINP (20) VRX (17) VRT (16) VREF/BIAS (22) OEB M U X M U X (11) NRESET VRB (15) RLC RLC CDS CDS CDS R G B M U X R G B PGA I/P SIGNAL POLARITY ADJUST

8 OFFSET

(13) AGND (29) DGND AVDD (12) DVDD1 (14) (30) OP[0] (31) OP[1] (1) OP[2] (2) OP[3] (3) OP[4] (4) OP[5] (5) OP[6] (6) OP[7] (7) OP[8] (8) OP[9] (9) OP[10] (10) OP[11]/SDO I/P SIGNAL POLARITY ADJUST I/P SIGNAL POLARITY ADJUST WM8141

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 PIN CONFIGURATION ORDERING INFORMATION DEVICE TEMP. RANGE PACKAGE WM8141CFT/V 0 to 70 °C 32-pin TQFP SCK/RNW OP[1] OP[0] DGND MCLK VSMP RLC/ACYC DVDD2 OP[2] OP[8] OP[7] OP[6] OP[5] OP[4] OP[3] OP[9] VRT OP[11]/SDO NRESET AVDD AGND DVDD1 VRB OP[10] SDI/DNA VRLC/VBIAS BINP GINP RINP OEB SEN/STB VRX 169 10 11 12 13 14 15 2532 31 30 29 28 27 26 PIN DESCRIPTION PIN NAME TYPE DESCRIPTION

1 OP[2] Digital output

2 OP[3] Digital output

3 OP[4] Digital IO

4 OP[5] Digital IO

5 OP[6] Digital IO

6 OP[7] Digital IO

7 OP[8] Digital IO

8 OP[9] Digital IO

9 OP[10] Digital IO

10 OP[11]/

Hi-Z digital 12-bit bi-directional bus. There are several modes: Hi-Z: when OEB = 1. 12-bit output: 12-bit data is output on OP[11:0]. 8-bit multiplexed output: data is output on OP[11:4] at 2 ∗ ADC conversion rate. 6-bit multiplexed output: data is output on OP[11:6] at 2 ∗ ADC conversion rate. 4-bit multiplexed output: data is output on OP[11:8] at 4 ∗ ADC conversion rate. Input 8-bit: control data is input on OP[11:4] in parallel mode when SCK/RNW = 0, and SEN/STB = 0. Output 8-bit: register read back data is output in parallel on OP[11:4] when SCK/RNW = 1, and SEN/STB = 0, or in serial on pin SDO when SEN/STB = 1. 11 NRESET Digital input Reset input, active low. This signal forces a reset of all internal registers and selects whether the serial or parallel control bus is used (see SEN/STB). 12 AVDD Supply Analogue supply (3.3/5V) for CDS, PGA and OFFSET blocks. This must be operated at the same potential as DVDD1. 13 AGND Supply Analogue ground (0V). 14 DVDD1 Supply Digital supply (3.3/5V) for logic and clock generator. This must be operated at the same potential as AVDD. 15 VRB Analogue output Lower reference voltage. This pin must be connected to AGND via a decoupling capacitor. 16 VRT Analogue output Upper reference voltage. This pin must be connected to AGND via a decoupling capacitor. 17 VRX Analogue output Input return bias voltage. This pin must be connected to AGND via a decoupling capacitor.

18 VRLC/

Analogue IO Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be connected to AGND via a decoupling capacitor. VRLC can be externally driven if programmed Hi-Z. 19 BINP Analogue input Blue channel input video. 20 GINP Analogue input Green channel input video. 21 RINP Analogue input Red channel input video. 22 OEB Digital input Output Hi-Z control: all outputs disabled when OEB = 1.

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 PIN NAME TYPE DESCRIPTION Serial Interface: Enable pulse, active high. Parallel Interface: Strobe, active low.23 SEN/STB Digital input Latched on NRESET rising edge: If Low then device control is via serial interface, if High then device control is via parallel interface.

24 SDI/DNA Digital input Serial Interface: Serial input

data signal. Parallel Interface: High = data, Low = address. 25 SCK/RNW Digital input Serial Interface: Serial clock signal. Parallel Interface: High = OP[11:4] is output bus, Low = OP[11:4] is input bus (Hi-Z)

26 RLC/

Digital input Selects whether Reset Level Clamp is applied (active high). If RLC is required on every pixel then this pin can be tied high. ACYC, auto-cycles between RINP, GINP, BINP when in line by line mode. 27 VSMP Digital input Video sample synchronisation pulse. 28 MCLK Digital input Master clock. This clock is applied at N times the input pixel rate (N = 8, 6, 3 or 2 depending on the input sampling mode). 29 DGND Supply Digital ground (0V).

30 OP[0] Digital output

31 OP[1] Digital output

Hi-Z digital 12-bit bi-directional bus, see description for pins OP[2] to OP[11]/SDO. 32 DVDD2 Supply Digital supply (3.3/5V) for all digital pins. ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. As per JEDEC specifications A112-A and A113-B, this product requires specific storage conditions prior to surface mount assembly. It has been classified as having a Moisture Sensitivity Level of 2 and as such will be supplied in vacuum-sealed moisture barrier bags. CONDITION MIN MAX Analogue supply voltage: AVDD GND - 0.3V GND + 7V Digital supply voltages: DVDD1, DVDD2 GND - 0.3V GND + 7V Digital ground: DGND GND - 0.3V GND + 0.3V Analogue ground: AGND GND - 0.3V GND + 0.3V Digital inputs, digital outputs and digital pins GND - 0.3V DVDD2 + 0.3V Analogue inputs (RINP, GINP, BINP) GND - 0.3V AVDD + 0.3V Other pins GND - 0.3V AVDD + 0.3V Operating temperature range: TA 0°C+ 7 0 °C Storage temperature -50°C +150 °C Package body temperature (soldering, 10 seconds) +240°C Package body temperature (soldering, 2 minutes) +183°C Notes: 1. GND denotes the voltage of any ground pin. 2. AGND and DGND pins are intended to be operated at the same potential. Differential voltages between these pins will degrade performance. 3. AVDD and DVDD1 pins are intended to be operated at the same potential. Differential voltages between these pins will degrade performance.

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 RECOMMENDED OPERATING CONDITIONS CONDITION SYMBOL MIN TYP MAX UNITS Operating temperature range TA 07 0 °C Digital supply voltages (5V operation) DVDD1, DVDD2 4.75 5 5.25 V Digital supply voltages (3.3V operation) DVDD1, DVDD2 2.97 3.3 3.63 V Analogue supply voltage (5V operation) AVDD 4.75 5 5.25 V Analogue supply voltage (3.3V operation) AVDD 2.97 3.3 3.63 V POSSIBLE POWER SUPPLY COMBINATIONS COMBINATION AVDD, DVDD1 (VOLTS) DVDD2 (VOLTS) 155 25 3 . 3 33 . 3 3 . 3

ELECTRICAL CHARACTERISTICS

ANALOGUE CHARACTERISTICS (5V OPERATION) Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Overall System Specification Including CDS, PGA, OFFSET and ADC Functions. No Missing Codes Guaranteed. Full-scale input voltage range (see Note 1) Max Gain Min Gain 0.4 4.08 Vp-p Vp-p Input signal limits (see Note 2) VIN 0 AVDD V Full-scale transition error Gain = 0dB; PGA[7:0] = 4B(hex) 20 mV Zero-scale transition error Gain = 0dB; PGA[7:0] = 4B(hex) 20 mV Differential non-linearity DNL 0.5 1 LSB Integral non-linearity INL 2 LSB Channel to channel gain matching 1% References Upper reference voltage VRT 2.70 2.85 3.00 V Lower reference voltage VRB 1.25 1.35 1.45 V Input return bias voltage VRX 0.60 0.65 0.70 V Diff. reference voltage (VRT-VRB)VRTB 1.4 1.5 1.6 V Output resistance VRT, VRB, VRX 1 Ω

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT VRLC/Reset-Level Clamp (RLC) RLC switching impedance 50 Ω VRLC short-circuit current 5m A VRLC output resistance 2 Ω VRLC Hi-Z leakage current 1 µA RLCDAC resolution 4b i t s RLCDAC step size, RLCDAC = 0 VRLCSTEP 0.24 V/step RLCDAC step size, RLCDAC = 1 VRLCSTEP 0.16 V/step RLCDAC output voltage at code 0(hex), RLCDACRNG = 0 VRLCBOT 0.4 V RLCDAC output voltage at code 0(hex), RLCDACRNG = 1 VRLCBOT 0.25 V RLCDAC output voltage at code F(hex) RLCDACRNG, = 0 VRLCTOP 4.2 V RLCDAC output voltage at code F(hex), RLCDACRNG = 1 VRLCTOP 2.85 V Offset DAC, Monotonicity Guaranteed Resolution 8b i t s Differential non-linearity DNL 0.1 0.5 LSB Integral non-linearity INL 0.25 1 LSB Step size 2.04 mV/step Output voltage Code 00(hex) Code FF(hex) -260 +260 mV mV Programmable Gain Amplifier Resolution 8b i t s Gain ]0:7[PGA283 208 − V/V Max gain, each channel G MAX 7.4 V/V Min gain, each channel G MIN 0.74 V/V Gain error, each channel 15 % Supply Currents Total supply current – active 45 65 mA Total analogue supply current – active IAVDD 42 mA Digital logic supply current, DVDD1 – active 2m A Digital I/O supply current, DVDD2 – active 1m A Supply current – full power down mode 10 µA Notes: 1. Full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain. 2. Input signal limits are the limits within which the full-scale input voltage signal must lie.

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 ANALOGUE CHARACTERISTICS (3.3V OPERATION) Test Conditions AVDD = DVDD1 = DVDD2 = 2.97V to 3.63V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 8MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Overall System Specification Including CDS, PGA, OFFSET and ADC Functions. Full-scale input voltage range (see Note 1) Max Gain Min Gain 0.2 2.04 Vp-p Vp-p Input signal limits (see Note 2) VIN 0 AVDD V Full-scale transition error Gain = 0dB; PGA[7:0] = 4B(hex) 20 mV Zero-scale transition error Gain = 0dB; PGA[7:0] = 4B(hex) 20 mV Differential non-linearity DNL 0.5 LSB Integral non-linearity INL 2 LSB Channel to channel gain matching 1% References Upper reference voltage VRT 1.625 1.725 1.825 V Lower reference voltage VRB 0.900 0.975 1.050 V Input return bias voltage VRX 0.60 0.65 0.70 V Diff. reference voltage (VRT-VRB)VRTB 0.65 0.75 0.85 V Output resistance VRT, VRB, VRX 1 Ω VRLC/Reset-Level Clamp (RLC) RLC switching impedance 140 Ω VRLC short-circuit current 5m A VRLC output resistance 2 Ω VRLC Hi-Z leakage current <0.1 µA RLCDAC resolution 4b i t s RLCDAC step size, RLCDAC = 0 VRLCSTEP 0.16 V/step RLCDAC step size, RLCDAC = 1 VRLCSTEP 0.09 V/step RLCDAC output voltage at code 0(hex), RLCDACRNG = 0 VRLCBOT 0.25 V RLCDAC output voltage at code 0(hex), RLCDACRNG = 1 VRLCBOT 0.2 V RLCDAC output voltage at code F(hex), RLCDACRNG = 0 VRLCTOP 2.75 V RLCDAC output voltage at code F(hex), RLCDACRNG = 1 VRLCTOP 1.7 V Offset DAC Resolution 8b i t s Differential non-linearity DNL 0.1 LSB Integral non-linearity INL 0.25 LSB Step size 1.02 mV/step Output voltage Code 00(hex) Code FF(hex) -130 +130 mV mV Programmable Gain Amplifier Resolution 8b i t s Gain ]0:7[PGA283 208 − V/V Max gain, each channel G MAX 7.4 V/V Min gain, each channel G MIN 0.74 V/V Gain error, each channel 1% Notes: 1. Full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain. 2. Input signal limits are the limits within which the full-scale input voltage signal must lie.

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 Test Conditions AVDD = DVDD1 = DVDD2 = 2.97V to 3.63V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 8MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Supply Currents Total supply current – active 43 mA Total analogue supply current – active IAVDD 40 mA Digital logic supply current, DVDD1 – active 2m A Digital I/O supply current, DVDD2 – active 1m A Supply current – full power down mode 10 µA DIGITAL CHARACTERISTICS Test Conditions AVDD = DVDD1 = DVDD2 = 2.97V to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DIGITAL SPECIFICATIONS Digital Inputs High level input voltage VIH 0.8 ∗ DVDD2 V Low level input voltage VIL 0.2 ∗ DVDD2 V High level input current IIH 1 µA Low level input current IIL 1 µA Input capacitance C I 5p F Digital Outputs High level output voltage VOH IOH = 1mA DVDD2 - 0.5 V Low level output voltage VOL IOL = 1mA 0.5 V High impedance output current IOZ 1 µA Digital IO Pins Applied high level input voltageVIH 0.8 ∗ DVDD2 V Applied low level input voltage VIL 0.2 ∗ DVDD2 V High level output voltage VOH IOH = 1mA DVDD2 - 0.5 V Low level output voltage VOL IOL = 1mA 0.5 V Low level input current IIL 1 µA High level input current IIH 1 µA Input capacitance C I 5p F High impedance output current IOZ 1 µA

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 PARALLEL INTERFACE STB DNA RNW OP[11:4] Hi-Z Hi-Z ADC DATA OUT ADC DATA OUT REG. DATA OUT ADC DATA OUT tSTB tASU tAH tDSU tDH tSTDO tSTAO tADLS tADLH tADHS tADHH tOPDtOPZ ADDRESS IN DATA IN Figure 5 Parallel Interface Diagram Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS RNW low to OP[11:4] tri-state. tOPZ 20 ns Address set-up time to STB low tASU 0n s DNA low set-up time to STB low tADLS 10 ns Strobe low time tSTB 50 ns Address hold time from STB high tAH 10 ns DNA low hold time from STB high tADLH 10 ns Data set-up time to STB low tDSU 0n s DNA high set-up time to STB low tADHS 10 ns Data hold time from STB high tDH 10 ns Data high hold time from STB high tADHH 10 ns RNW high to OP[11:4] output tOPD 35 ns Data output propagation delay from STB low tSTDO 35 ns ADC data out propagation delay from STB high tSTAO 35 ns Note: Parameters are measured at 50% of the rising/falling edge.

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 DEVICE DESCRIPTION INTRODUCTION A block diagram of the device showing the signal path is presented on Page 1. The WM8141 samples up to three inputs (RINP, GINP and BINP) simultaneously. The device then processes the sampled video signal with respect to the video reset level or an internally/externally generated reference level using either one or three processing channels. Each processing channel consists of an Input Sampling block with optional Reset Level Clamping (RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and an 8-bit Programmable Gain Amplifier (PGA). The ADC then converts each resulting analogue signal to a 12-bit digital word. The digital output from the ADC is presented on a 12-bit wide bi-directional bus, with optional 8+4-bit, 6+6-bit or 4+4+4-bit multiplexed formats. On-chip control registers determine the configuration of the device, including the offsets and gains applied to each channel. These registers are programmable via serial or parallel interfaces. INPUT SAMPLING The WM8141 can sample and process one to three inputs through one or three processing channels as follows: Colour Pixel-by-Pixel: The three inputs (RINP, GINP and BINP) are simultaneously sampled for each pixel and a separate channel processes each input. The signals are then multiplexed into the ADC, which converts all three inputs within the pixel period. Monochrome: A single chosen input (RINP, GINP, or BINP) is sampled, processed by the corresponding channel, and converted by the ADC. The choice of input and channel can be changed via the control interface, e.g. on a line-by-line basis if required. Colour Line-by-Line: A single chosen input (RINP, GINP, or BINP) is sampled and multiplexed into the red channel for processing before being converted by the ADC. The input selected can be switched in turn (RINP → GINP → BINP → RINP… ) together with the PGA and Offset DAC control registers by pulsing the RLC/ACYC pin. This is known as auto-cycling. Alternatively, other sampling sequences can be generated via the control registers. This mode causes the blue and green channels to be powered down. Refer to the Line-by-Line Operation section for more details. RESET LEVEL CLAMPING (RLC) To ensure that the signal applied to the WM8141 lies within its input range (0V to AVDD) the CCD output signal is usually level shifted by coupling through a capacitor, C IN. The RLC circuit clamps the WM8141 side of this capacitor to a suitable voltage during the CCD reset level. A typical input configuration is shown in Figure 5. A clamp pulse, CL, is generated from MCLK and VSMP by the Timing Control Block. When CL is active the voltage on the WM8141 side of CIN, at RINP, is forced to the VRLC/VBIAS voltage (VVRLC ) by switch 1. When the CL pulse turns off, the voltage at RINP initially remains at VVRLC but any subsequent variation in sensor voltage (from reset to video level) will couple through CIN to RINP. RLC is compatible with both CDS and non-CDS operating modes, as selected by switch 2. Refer to the CDS/non-CDS Processing section.

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the difference between the input video level VIN and the input reset level VRESET . For non-CDS this is the difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC , optionally set via the RLC DAC. The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the black level of the input signal towards 0V, producing V2. The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range, outputting voltage V3. The ADC BLOCK then converts the analogue signal, V3, to a 12-bit unsigned digital output, D 1. The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D 2. CALCULATING OUTPUT FOR ANY GIVEN INPUT The following equations describe the processing of the video and reset level signals through the WM8141. INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET , is subtracted from the input video. If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted instead. If RLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS. If RLCEXT = 0, VVRLC is the output from the internal RLC DAC. VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC. OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST The resultant signal V1 is added to the Offset DAC output. PGA NODE: GAIN ADJUST The signal is then multiplied by the PGA gain, ADC BLOCK: ANALOGUE-DIGITAL CONVERSION The analogue signal is then converted to a 12-bit unsigned number, with input range configured by PGAFS[1:0]. where the ADC full-scale range, VFS = 3V at AVDD=5V and VFS = 1.5V at AVDD=3.3V OUTPUT INVERT BLOCK: POLARITY ADJUST The polarity of the digital output may be inverted by control bit INVOP.

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 OUTPUT FORMATS The digital data output from the ADC is available to the user in either 12-bit parallel or 8/6/4-bit wide multiplexed formats by setting control bits MUXOP[1:0]. Latency of valid output data with respect to VSMP is programmable by writing to control bits DEL[1:0]. The latency for each mode is shown in the Mode Timing Diagrams section. Figure 10 shows the output data formats for Modes 1 – 2 and 4 – 6. Figure 11 shows the output data formats for Mode 3. Table 1 summarises the output data obtained for each format. MCLK 4+4+4-BIT OUTPUT A AB AB CF 12-BIT PARALLEL OUTPUT 8+4 AND 6+6-BIT OUTPUT MCLK 4+4+4-BIT OUTPUT A AB 12-BIT PARALLEL OUTPUT 8+4 AND 6+6-BIT OUTPUT AB C FAB Figure 10 Output Data Formats (Modes 1 − 2, 4 − 6) Figure 11 Output Data Formats (Mode 3) OUTPUT FORMAT MUXOP[1:0] OUTPUT PINS OUTPUT 12-bit parallel 00 OP[11:0] A = d11, d10, d9, d8, d7, d6, d5, d4, d3, d2, d1, d0 8+4-bit multiplexed

01 OP[11:4] A = d11, d10, d9, d8, d7, d6, d5, d4

B = d3, d2, d1, d0, PNS, CC[1], CC[0], OVRNG 6+6-bit multiplexed B = d5, d4, d3, d2, d1, d0, PNS, OVRNG 4+4+4-bit multiplexed (nibble)

11 OP[11:8] A = d11, d10, d9, d8

B = d7, d6, d5, d4 C = d3, d2, d1, d0 F = PNS, CC[1], CC[0], OVRNG Table 1 Details of Output Data Shown in Figures 9 and 10 FLAGS The following flags are output during multiplexed modes: PNS indicates whether the control interface is operating in parallel or serial, 1 = parallel, 0 = serial. CC[1] and CC[0] indicate from which input the current output was sampled: INPUT CC[1] CC[0] RINP 00 GINP 01 BINP 10 Table 2 Input Sampled Flags CC[1:0] OVRNG indicates that the current output data was produced by an input signal that exceeded the input range limit of the device. 1 = out of range, 0 = within range.

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 MCLK VSMP (VDEL = 000) INTVSMP POSNNEG = 1 (VDEL = 001) INTVSMP (VDEL = 010) INTVSMP (VDEL = 011) INTVSMP (VDEL = 100) INTVSMP (VDEL = 101) INTVSMP (VDEL = 110) INTVSMP (VDEL = 111) INTVSMP POSNNEG = 0 (VDEL = 000) INTVSMP (VDEL = 001) INTVSMP (VDEL = 010) INTVSMP (VDEL = 011) INTVSMP (VDEL = 100) INTVSMP (VDEL = 101) INTVSMP (VDEL = 110) INTVSMP (VDEL = 111) INTVSMP INPUT PINS Figure 16 Internal VSMP Pulses Generated by Programmable VSMP Detect Circuit REFERENCES The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin VRLC/VBIAS POWER SUPPLY The WM8141 can run off either 3.3V or 5V single supplies or from split 5V (core) and 3.3V (digital interface) supplies. POWER MANAGEMENT Power management for the device is performed via the Control Interface. The device can be powered on or off completely by the EN bit. Alternatively, when control bit SELPD is high, only blocks selected by further control bits (SELDIS[3:0]) are powered down. This allows the user to optimise power dissipation in certain modes, or to define an intermediate standby mode to allow a quicker recovery into a fully active state. In Line-by-line operation, the green and blue channel PGAs are automatically powered down. All the internal registers maintain their previously programmed value in power down modes and the Control Interface inputs remain active. Table 3 summarises the power down control bit functions. EN SELDPD 00 Device completely powers down. 10 Device completely powers up. X1 Blocks with respective SELDIS[3:0] bit high are disabled. Table 3 Power Down Control

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 LINE-BY-LINE OPERATION Certain linear sensors (e.g Contact Image Sensors) give colour output on a line-by-line basis. i.e a full line of red pixels followed by a line of green pixels followed by a line of blue pixels. In order to accommodate this type of signal the WM8141 can be set into Monochrome mode, with the input channel switched by writing to control bits CHAN[1:0] between every line. Alternatively, the WM8141 can be placed into colour line-by-line mode by setting the LINEBYLINE control bit. When this bit is set the green and blue processing channels are powered down and the device is forced internally to only operate in MONO mode (because only one colour is sampled at a time) through the red channel. Figure 17 shows the signal path when operating in colour line-by-line mode. RINP SEN/STB VSMP MCLKVRLC/VBIAS SDI/DNA SCK/RNW RLC/ACYC RLC BINP GINP INPUT MUX OFFSET MUX RLC RLC R G B R G B PGA I/P SIGNAL POLARITY ADJUST RLC DAC CONFIGURABLE SERIAL/ PARALLEL CONTROL INTERFACE OP[11:0]+ WM8141 12-BIT ADC DATA I/O PORT Figure 17 Signal Path When in Line-by-Line Mode In this mode the input multiplexer and (optionally) the PGA/Offset register multiplexers can be auto- cycled by the application of pulses to the RLC/ACYC input pin by setting the ACYCNRLC register bit. The multiplexers change on the first MCLK rising edge after RLC/ACYC is taken high. Alternatively, all three multiplexers can be controlled via the serial interface by writing to register bits INTM[1:0] to select the desired colour. It is also possible for the input multiplexer to be controlled separately from the PGA and Offset multiplexers. Table 4 describes all the multiplexer selection modes that are possible. FME ACYCNRLC NAME DESCRIPTION

00 Internal,

Input mux, offset and gain registers determined by internal register bits INTM1, INTM0.

01 Auto-cycling,

Input mux, offset and gain registers auto-cycled, RINP → GINP → BINP → RINP… on RLC/ACYC pulse.

10 Internal,

Input mux selected from internal register bits FM1, FM0; Offset and gain registers selected from internal register bits INTM1, INTM0.

11 Auto-cycling,

Input mux selected from internal register bits FM1, FM0; Offset and gain registers auto-cycled, RINP → GINP → BINP → RINP… on RLC/ACYC pulse. Table 4 Colour Selection Description in Line-by-Line Mode

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 OPERATING MODES Table 5 summarises the most commonly used modes, the clock waveforms required and the register contents required for CDS and non-CDS operation. MODE DESCRIPTION CDS AVAILABLE MAX SAMPLE RATE SENSOR INTERFACE

CONTENTS

1 Colour

Yes 2MSPS The 3 input channels are sampled in parallel. The signal is then gain and offset adjusted before being multiplexed into a single data stream and converted by the ADC, giving an output data rate of 6MSPS max. MCLK max MCLK: VSMP ratio is 6:1 SetReg1: 03(hex) SetReg1: 01(hex)

2 Monochrome/

Yes 2MSPS As mode 1 except: Only one input channel at a time is continuously sampled. MCLK max MCLK: VSMP ratio is 6:1 SetReg1: 07(hex) SetReg1: 05(hex)

3 Fast

Yes 4MSPS Identical to mode 2 MCLK max MCLK: VSMP ratio is 3:1 Identical to mode 2 plus SetReg3: bits 5:4 must be set to 0(hex) Identical to mode 2

4 Maximum

No 6MSPS Identical to mode 2 MCLK max MCLK: VSMP ratio is 2:1 CDS not possible SetReg1: 45(hex) 5 Slow Colour Yes 1.5MSPS Identical to mode 1 MCLK max MCLK: VSMP ratio is 2n:1, n ≥ 4 Identical to mode 1 Identical to mode 1

6 Slow

Yes 1.5MSPS Identical to mode 2 MCLK max MCLK: VSMP ratio is 2n:1, n ≥ 4 Identical to mode 2 Identical to mode 2 Table 5 WM8141 Operating Modes Notes: 1. In Monochrome mode, SetReg3 bits 7:6 determine which input is to be sampled. 2. For Colour Line-by-Line, set control bit LINEBYLINE. For input selection, refer to Table 4, Colour Selection Description in Line-by-Line Mode. 3. MCLK max = 12MHz at AVDD = 5V, MCLK max = 8MHz at AVDD = 3.3V.

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 OPERATING MODE TIMING DIAGRAMS The following diagrams show 12-bit parallel format output and MCLK, VSMP and input video requirements for operation of the most commonly used modes as shown in Table 5. The diagrams are identical for both CDS and non-CDS operation. Outputs from RINP, GINP and BINP are shown as R, G and B respectively. X denotes invalid data. MCLK VSMP INPUT VIDEO OP[11:0] (DEL = 00) OP[11:0] (DEL = 01) OP[11:0] (DEL = 10) OP[11:0] (DEL = 11)

16.5 MCLK PERIODS

B R G B R G B GR G RBG B R G B R G B R G RB R BGR G B G G B Figure 18 Mode 1 Operation OP[11:0] (DEL = 00) OP[11:0] (DEL = 01) OP[11:0] (DEL = 10) OP[11:0] (DEL = 11) X X R X X R X RX R XXR R X X R X X R XX X XRX X R X X R X X XR X RXX X X R X X R X RX R XXR Figure 19 Mode 2 Operation MCLK VSMP OP[11:0] (DEL = 00) INPUT VIDEO OP[11:0] (DEL = 01) OP[11:0] (DEL = 10) OP[11:0] (DEL = 11)

23.5 MCLK PERIODS

R R R RR RRRRRRR R R RR RRRRRRR R R R R R Figure 20 Mode 3 Operation

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 MCLK VSMP INPUT VIDEO OP[11:0] (DEL = 00) OP[11:0] (DEL = 01) OP[11:0] (DEL = 10) OP[11:0] (DEL = 11) R R R R R R R R Figure 21 Mode 4 Operation MCLK VSMP INPUT VIDEO OP[11:0] (DEL = 00) OP[11:0] (DEL = 01) OP[11:0] (DEL = 10) OP[11:0] (DEL = 11) B X G B R X R G B X R G Figure 22 Mode 5 Operation (MCLK:VSMP Ratio = 8:1) MCLK VSMP INPUT VIDEO OP[11:0] (DEL = 00) OP[11:0] (DEL = 01) OP[11:0] (DEL = 10) OP[11:0] (DEL = 11) X X X Figure 23 Mode 6 Operation (MCLK:VSMP Ratio = 8:1)

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 DEVICE CONFIGURATION REGISTER MAP The following table describes the location of each control bit used to determine the operation of the WM8141. The register map is programmed by writing (in serial or parallel) the required codes to the appropriate addresses. BITADDRESS <a5:a0> DESCRIPTION DEF (hex) RW b7 b6 b5 b4 b3 b2 b1 b0

000001 Setup Reg 1 03 RW MODE4 PGAFS[1] PGAFS[0] SELPD MONO CDS EN

000010 Setup Reg 2 20 RW DEL[1] DEL[0] RLCDACRNG 0 VRLCEXT INVOP MUXOP[1] MUXOP[0]

000011 Setup Reg 3 1F RW CHAN[1] CHAN[0] CDSREF [1] CDSREF [0] RLCV[3] RLCV[2] RLCV[1] RLCV[0]

000100 Software Reset 00 W

000101 Auto- cycle Reset 00 W

000110 Setup Reg 4 00 RW FM[1] FM[0] INTM[1] INTM[0] RLCINT FME ACYCNRLC LIN EBYLINE

001000 Setup Reg 5 00 RW 0 0 0 POSNNEG VDEL[2] VDEL[1] VDEL[0] VSMPDET

001001 Setup Reg 6 00 RW 0 0 0 0 SELDIS[3] SELDIS [2] SELDIS[1] SELDIS[0]

001010 Reserved 00 RW 0 0 0 0 0 0 0 0

001011 Reserved 00 RW 0 0 0 0 0 0 0 0

001100 Reserved 00 RW 0 0 0 0 0 0 0 0

100000 DAC Value (Red) 80 RW DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0]

100001 DAC Value (Green) 80 RW DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0]

100010 DAC Value (Blue) 80 RW DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0]

100011 DAC Value (RGB) 80 W DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0]

101000 PGA Gain (Red) 00 RW PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0]

101001 PGA Gain (Green) 00 RW PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0]

101010 PGA Gain (Blue) 00 RW PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0]

101011 PGA Gain (RGB) 00 W PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0]

The following table describes the function of each of the control bits shown in Table 6. REGISTER BIT NO BIT NAME(S) DEFAULT DESCRIPTION 0E N 1 Global power down: 0 = complete power down, 1 = fully active.

1 CDS 1 Select correlated double sampling mode: 0 = single ended mode,

1 = CDS mode. 2M O N O 0 Mono/colour select: 0 = colour, 1 = monochrome operation.

3 SELPD 0 Selective power down: 0 = no individual control,

1 = individual blocks can be disabled (controlled by SELDIS[3:0]). Offsets PGA output to optimise the ADC range for different polarity sensor output signals. Zero differential PGA input signal gives: 5:4 PGAFS[1:0] 00 00 = Zero output (use for bipolar video) 01 = Zero output 10 = Full-scale positive output (use for negative going video) 11 = Full-scale negative output (use for positive going video) Setup Register 1 6M O D E 4 0 Required when operating in MODE4: 0 = other modes, 1 = MODE4.

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 REGISTER BIT NO BIT NAME(S) DEFAULT DESCRIPTION Determines the output data format.1:0 MUXOP[1:0] 0 00 = 12-bit output 01 = 8-bit multiplexed (8+4 bits) 10 = 6-bit multiplexed mode (6+6 bits) 11 = 4-bit multiplexed mode (4+4+4 bits) 2I N V O P 0 Digitally inverts the polarity of output data. 0 = negative going video gives negative going output. 1 = negative-going video gives positive going output data.

3 VRLCEXT 0 When set powers down the RLCDAC, changing its output to Hi-Z, allowing

VRLC to be externally driven. 5 RLCDACRNG 1 Sets the output range of the RLCDAC. 0 = RLCDAC ranges from 0 to AVDD (approximately). 1 = RLCDAC ranges from 0 to VRT (approximately). Sets the output latency in ADC clock periods.

1 ADC clock period = 2 MCLK periods except in mode 3 where 1 ADC clock

period = 3 MCLK periods. Setup Register 2 7:6 DEL[1:0] 00 00 = Minimum latency 01 = Delay by one ADC clock period 10 = Delay by two ADC clock periods 11 = Delay by three ADC clock periods 3:0 RLCV[3:0] 1111 Controls RLCDAC driving VRLC pin to define single ended signal reference voltage or Reset Level Clamp voltage. See Electrical Characteristics section for ranges. 5:4 CDSREF[1:0] 01 CDS mode reset timing adjust. 00 = Advance 1 MCLK period 01 = Normal 10 = Retard 1 MCLK period 11 = Retard 2 MCLK periods Monochrome mode channel select. Setup Register 3 7:6 CHAN[1:0] 00 00 = Red channel select 01 = Green channel select 10 = Blue channel select 11 = Reserved Software Reset Any write to Software Reset causes all cells to be reset. Auto-cycle Reset Any write to Auto-cycle Reset causes the auto-cycle counter to reset to RINP.

0 LINEBYLINE 0 Selects line by line operation 0 = normal operation,

1 = line by line operation. When line by line operation is selected MONO is forced to 1 and CHAN[1:0] to 00 internally, ensuring that the correct internal timing signals are produced. Green and Blue PGAs are also disabled to save power. 1 ACYCNRLC 0 When LINEBYLINE = 0 this bit has no effect. When LINEBYLINE = 1 this bit determines the function of the RLC/ACYC input pin and the input multiplexer and offset/gain register controls. 0 = RLC/ACYC pin enabled for Reset Level Clamp. Internal selection of input and gain/offset multiplexers. 1 = Auto-cycling enabled by pulsing the RLC/ACYC input pin. See Table 4, Colour Selection Description in Line-by-Line Mode for colour selection mode details. When auto-cycling is enabled, the RLC/ACYC pin cannot be used for reset level clamping. The RLCINT bit may be used instead. 2F M E 0 When LINEBYLINE = 0 this bit has no effect. When LINEBYLINE = 1 this bit controls the input force mux mode: 0 = No force mux, 1 = Force mux mode. Forces the input mux to be selected by FM[1:0] separately from gain and offset multiplexers. See Table 4 for details. 3R L C I N T 0 When LINEBYLINE = 1 and ACYCNRLC = 1 this bit is used to determine whether Reset Level Clamping is used. 0 = RLC disabled, 1 = RLC enabled. 5:4 INTM[1:0] 00 Colour selection bits used in internal modes. See Table 4 for details. 00 = Red, 01 = Green, 10 = Blue and 11 = Reserved. Setup Register 4 7:6 FM[1:0] 00 Colour selection bits used in input force mux modes. See Table 4 for details. 00 = Red, 01 = Green, 10 = Blue and 11 = Reserved.

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 REGISTER BIT NO BIT NAME(S) DEFAULT DESCRIPTION

0 VSMPDET 0 0 = Normal operation, signal on VSMP input pin is applied directly to Timing

Control block. 1 = Programmable VSMP detect circuit is enabled. An internal synchronisation pulse is generated from signal applied to VSMP input pin and is applied to Timing Control block. 3:1 VDEL[2:0] 000 When VSMPDET = 0 these bits have no effect. When VSMPDET = 1 these bits set a programmable delay from the detected edge of the signal applied to the VSMP pin. The internally generated pulse is delayed by VDEL MCLK periods from the detected edge. See Figure 16 Internal VSMP Pulses Generated by Programmable VSMP Detect Circuit, for details. Setup Register 5 4 POSNNEG 0 When VSMPDET = 0 this bit has no effect. When VSMPDET = 1 this bit controls whether positive or negative edges are detected: 0 = Negative edge on VSMP pin is detected and used to generate internal timing pulse. 1 = Positive edge on VSMP pin is detected and used to generate internal timing pulse. See Figure 15 for further details. Setup Register 6 3:0 SELDIS[3:0] 0 Selective power disable register - activated when SELPD = 1. Each bit disables respective function when 1, enabled when 0. SELDIS[0] = Red CDS, PGA SELDIS[1] = Green CDS, PGA SELDIS[2] = Blue CDS, PGA SELDIS[3] = ADC Table 7 Register Control Bits

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 APPLICATIONS RECOMMENDATIONS INTRODUCTION The WM8141 is a mixed signal device, therefore careful PCB layout is required. The following section contains PCB layout guidelines, which are recommended for optimal performance from the WM8141, and some typical applications circuits. PCB LAYOUT 1) Use separate analogue and digital power and ground planes. The analogue and digital ground planes should be connected as close as possible to, or underneath, the WM8141. 2) Place all supply decoupling capacitors as close as possible to their respective supply pins and provide a low impedance path from the capacitors to the appropriate ground. 3) Avoid noise on AGND, pin 13. 4) Avoid noise on reference pins VRT, VRB and VRX. Place the decoupling capacitors as close as possible to these pins and provide a low impedance path from the capacitors to analogue ground. 5) Input signals should be screened from each other and from other sources of noise to avoid cross- talk and interference. 6) Minimise load capacitance on digital outputs. Capacitive loads of greater than 20pF will degrade performance. Use buffers if necessary and keep tracks short. TYPICAL APPLICATIONS DIAGRAMS The WM8141 is intended to be used in three types of architecture.

• Monochrome
• Colour Pixel-By-Pixel
• Colour Line-By-Line Each of these architectures is outlined in this section. The output from a CCD sensor usually has a high impedance and must therefore be buffered as close to the sensor as possible. The sensor manufacturers’ datasheets specify the buffer circuit to use. Initially, the designer must decide if CDS and RLC are to be used. The WM8141 supports both of these functions and Wolfson recommend using both CDS and pixel-by-pixel RLC for optimal performance. In this case a low value a.c. coupling capacitor is required between the sensor and the WM8141. Experiments have shown that a 100pF capacitor is the optimum value to use, however this may vary for particular applications depending on speed of operation and PCB layout.

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 MONOCHROME CCD S E N S O R BUFFER WM8141 INCLUDING RECOMMENDED EXTERNAL COMPONENTS DATA CONTROL I/F CLOCKSVOUT RINP C See sensor datasheet for details SENSOR TIMING Maximum pixel rate = 1.5Mpixels/second (Mode 6) Maximum pixel rate = 2Mpixels/second (Mode 2) Maximum pixel rate = 4Mpixels/second (Mode 3) Maximum pixel rate = 6Mpixels/second (Mode 4) SYSTEM ASIC Figure 24 Block Diagram of Monochrome CCD Application, AC Coupled REGISTER SETTING NAME ADDRESS HEX BINARY NOTE Set-up register 1 000001 2F 0010 1111 EN = 1: Device enabled; CDS = 1: CDS enabled; MONO = 1: Monochrome operation; SELPD = 1: Selective power down possible; PGAFS[1:0] = 10: ADC range optimised for negative going video; MODE4 = 0: Only set when 2:1 MCLK:VSMP ratio required (mode 4). Set-up register 2 000010 20 0010 0000 MUXOP[1:0] = 00: 12-bit parallel output; INVOP = 0: Output data not inverted; VRLCEXT = 0: RLCDAC required to provide reset level clamp voltage since sensor is AC coupled; RLCDACRNG = 1: RLCDAC range is 0V to V RT ; DEL[1:0] = 00: Default latency. Set-up register 3 000011 1F 0001 1111 RLCV[3:0] = 1111: RLCDAC full scale voltage; CDSREF[1:0] = 01: Default reset sample position; CHAN[1:0] = 00: Red channel selected. Set-up register 4 000101 00 0000 0000 Line-by-line mode not used so this register is not required. Set-up register 5 001000 00 0000 0000 Only used if programmable VSMP circuit is required. Set-up register 6 001001 06 0000 0110 SELDIS[3:0] = 0110: Disable green and blue channels to reduce power. Table 8 Typical Control Register Settings for Figure 24 (CDS, Negative-Going CCD Video Signal, MCLK:VSMP = 2:1/3:1/6:1/8:1)

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 COLOUR PIXEL-BY-PIXEL S E N S O R BUFFER WM8141 INCLUDING RECOMMENDED EXTERNAL COMPONENTS BUFFER BUFFER DATA CONTROL I/F CLOCKSR G B RINP GINP BINP C R C G C B See sensor datasheet for details. SENSOR TIMING Maximum pixel rate = 1.5Mpixels/second (Mode 5) Maximum pixel rate = 2Mpixels/second (Mode 1) SYSTEM ASIC Figure 25 Block Diagram of Colour Pixel-By-Pixel Application, AC Coupled REGISTER SETTING NAME ADDRESS HEX BINARY NOTE Set-up register 1 000001 13 0010 0011 EN = 1: Device enabled; CDS = 1: CDS enabled; MONO = 0: Colour operation; SELPD = 0: No selective power down; PGAFS[1:0] = 10: ADC range optimised for negative going video; MODE4 = 0: Not required for colour. Set-up register 2 000010 20 0010 0000 MUXOP[1:0] = 00: 12-bit parallel output; INVOP = 0: Output data not inverted; VRLCEXT = 0: RLCDAC required to provide reset level clamp voltage since sensor is AC coupled; RLCDACRNG = 1: RLCDAC range is 0V to V RT ; DEL[1:0] = 00: Default latency Set-up register 3 000011 1F XX01 1111 RLCV[3:0] = 1111: RLCDAC full scale voltage; CDSREF[1:0] = 01: Default reset sample position; CHAN[1:0] = XX: Colour mode so not required. Set-up register 4 000101 00 0000 0000 Line-by-Line mode not used so this register is not required. Set-up register 5 001000 00 0000 0000 Only used if programmable VSMP circuit is required. Set-up register 6 001001 00 0000 0000 All channels enabled. Table 9 Typical Control Register Settings for Figure 25 (CDS, Negative-Going CCD Video Signal, MCLK:VSMP = 6:1/8:1)

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 COLOUR LINE-BY-LINE S E N S O R BUFFER WM8141 INCLUDING RECOMMENDED EXTERNAL COMPONENTS DATA CONTROL I/F CLOCKSVOUT RINP C See sensor datasheet for details SENSOR TIMING Maximum pixel rate = 1.5Mpixels/second (Mode 6) Maximum pixel rate = 2Mpixels/second (Mode 2) Maximum pixel rate = 4Mpixels/second (Mode 3) Maximum pixel rate = 6Mpixels/second (Mode 4) SYSTEM ASIC Figure 26 Block Diagram Of Colour Line-By-Line Application, AC Coupled REGISTER SETTING NAME ADDRESS HEX BINARY NOTE Set-up register 1 000001 23 0010 0X11 EN = 1: Device enabled; CDS = 1: CDS enabled; MONO = X: Forced internally when LINEBYLINE is set; SELPD = 0: No selective power down; PGAFS[1:0] = 10: ADC range optimised for negative going video; MODE4 = 0: set high if MCLK:VSMP ratio of 2:1 is required. Set-up register 2 000010 20 0010 0000 MUXOP[1:0] = 00: 12-bit parallel output; INVOP = 0: Output data not inverted; VRLCEXT = 0: RLCDAC required to provide reset level clamp voltage since sensor is AC coupled; RLCDACRNG = 1: RLCDAC range is 0V to V RT ; DEL[1:0] = 00: Default latency. Set-up register 3 000011 1F 01 1111 RLCV[3:0] = 1111: RLCDAC full scale voltage; CDSREF[1:0] = 01: Default reset sample position; CHAN[1:0] = XX: Colour mode so not required. Set-up register 4 000101 0B 00XX 1111 LINEBYLINE = 1: Line by line mode selected; ACYCNRLC = 1: Auto-cycling required; FME = 1: Input mux controlled by FME bits; RLCINT = 1: RLC performed on every pixel; INTM[1:0] = XX: PGA/Offset multiplexers controlled by auto-cycling so these bits have no effect; FME[1:0] = 00: Controls input multiplexer to select red channel. Set-up register 5 001000 00 0000 0000 Only used if programmable VSMP circuit is required. Set-up register 6 001001 00 0000 0000 Green and blue channels are automatically powered down when LINEBYLINE = 1. Table 10 Typical Control Register Settings for Figure 26 (CDS, Negative-Going CCD Video Signal, MCLK/VSMP = 2:1/3:1/6:1/8:1)

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 RECOMMENDED EXTERNAL COMPONENTS DVDD1 DVDD2 AGND RINP GINP BINP MCLK VSMP RLC/ACYC SCK/RNW SEN/STB SDI/DNA OEB 30OP[0] OP[1] OP[2] OP[3] OP[4] OP[5] OP[6] OP[11]/SDO OP[10] OP[9] OP[8] OP[7] VRLC/VBIAS VRX VRT VRB AVDD WM8141 C2C1 C6 C8 C4 C5 DVDD AVDD C11C10 DVDD C12 AVDD ++ + Video Inputs Timing Signals Interface Controls Output Data Bus C1-9 should be fitted as close toNOTES: DGND DGND AGND AGND AGND AGND and DGND should be connected as close to WM8141 as possible. WM8141 as possible.

11 NRESET

Figure 27 External Components Diagram COMPONENT REFERENCE SUGGESTED VALUE C1 100nF De-coupling for DVDD1. C2 100nF De-coupling for DVDD2. C3 100nF De-coupling for AVDD. C4 10nF High frequency de-coupling between VRT and VRB. C5 1 µF Low frequency de-coupling between VRT and VRB (non-polarised). C6 100nF De-coupling for VRB. C7 100nF De-coupling for VRX. C8 100nF De-coupling for VRT. C9 100nF De-coupling for VRLC. C10 10 µF Reservoir capacitor for DVDD. C11 10 µF Reservoir capacitor for DVDD. C12 10 µF Reservoir capacitor for AVDD. Table 11 External Components Descriptions

WOLFSON MICROELECTRONICS LTD PD Rev 3.0 October 2000 PACKAGE DIMENSIONS NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = BBA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. Symbols Dimensions (mm) MIN NOM MAX A ----- ----- 1.60 A 2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 ----- 0.20 D 9.00 BSC D 1 7.00 BSC E 9.00 BSC E1 7.00 BSC e 0.80 BSC L 0.45 0.60 0.75 Θ 0 o 3.5 o o Tolerances of Form and Position ccc 0.10 REF: JEDEC.95, MS-026 DM002.BFT: 32 PIN TQFP (7 x 7 x 1.4 mm) A 1724 D E1 E 1625 b e ccc SEATING PLANEC A1A2 -C- Θ c L