WM5615 WOLFSON | Alldatasheet

Document overview

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Technical content

Features

  • 10-bit CMOS voltage output DAC in an 8-terminal package
  • 5V single supply operation
  • 3-wire serial interface
  • High-impedance reference input
  • Maximum voltage output twice reference input voltage
  • Internal power-on reset
  • Low power consumption ... 1.75mW max
  • 877kHz update rate
  • Monotonic over temperature
  • Pin compatible with the Maxim MAX515

Applications

  • Battery-powered test Instruments
  • Digital offset and gain adjustment
  • Battery-operated/remote industrial controls
  • Machine and motion control devices
  • Cellular telephones Wolfson Microelectronics © 1996 Wolfson Microelectronics VDD 16-BIT SHIFT REGISTER CS SCLK DIN DOUT (LSB) Xs DUMMY BITS (MSB) CONTROL LOGIC POWER-ON RESET RESISTOR STRING DAC VOUT 10-BIT DAC REGISTER Block Diagram R R WM5615 SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp. Production Data data sheets contain final specifications current on publication date. Supply of products conforms to Wolfson Mi- croelectronics standard terms and conditions. AGND REFIN

WM5615CD 0 oC to +70oC 8 pin SO WM5615CP 0 oC to +70oC 8 pin DIP WM5615ID -40 oC to +85oC 8 pin SO WM5615IP -40 oC to +85oC 8 pin DIP Absolute Maximum Ratings Digital input voltage range to AGND . .-0.3V to VDD +0.3V Output voltage at OUT from external source . .VDD + 0.3V Operating free-air temperature range TA: Lead temperature 1.6mm (1/16 inch) DIN SCLK CS DOUT V DD VOUT REFIN AGND 4 5 Ordering InformationPin Configuration D or P package Top View Note: Stresses beyond those listed under 'Absolute Maximum Ratings' may cause damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under 'Recommended Operating Conditions' is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Recommended Operating Conditions PARAMETER SYMBOL MIN TYP MAX UNIT Supply voltage V DD 4.5 5 5.5 V High-level digital input voltage V IH 2.4 V Low-level digital input voltage V IL 0.8 V Reference voltage to REFIN terminal V ref 0 2.048 V DD -2 V Load resistance R L 2k Ω Operating free air temperature WM5615C T A 07 0 oC WM5615I T A -40 85 oC

Integral nonlinearity INL (see note 1) ±1 LSB Differential nonlinearity DNL (see note 2) +0.1 ±0.5 LSB Zero scale error (offset error) E ZS (see note 3) ±3 LSB Zero scale error (offset error) (see note 4) 3 ppm/oC temperature coefficient Gain error E G (see note 5) ±3 LSB Gain error temperature (see note 6) 1 ppm/oC coefficient Power-supply rejection ratioPSRR Offset (see notes 7 and 8) 0.1 LSB/V Gain 0.1 Analogue full scale output R L = 100kΩ 2Vref(1023/1024) V Electrical Characteristics (over recommended operating free-air temperature range) VDD = 5.0V ±5%, Vref = 2.048V unless otherwise stated. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Static DAC Specifications Notes: 1. The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation ot the output from the line between zero and full scale, excluding the effect of zero code and full scale errors (see text). 2. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 3. Zero-scale error is the deviation from zero voltage output when the digital input is zero (see text) 4. Zero-scale error temperature coefficient is given by E ZS TC = [EZS (Tmax ) - EZS (Tmin)] /Vref x 106/ (Tmax- Tmin) Voltage Output (OUT) 5. Gain error is the deviation from the ideal output (Vref - 1LSB) with an output load of 10kΩ , excluding the effects of zero error. 6. Gain temperature coefficient is given by EG TC = [EG (Tmax ) - EG (Tmin)] /Vref x 106/(Tmax -Tmin). 7. Zero-scale offset error rejection ratio (EZS -RR) is measured by varying the VDD from 4.5V to 5.5V DC and measuring the proportion of this signal imposed on the zero-code output voltage. 8. Gain error rejection ratio (EG -RR) is measured by varying the VDD from 4.5 to 5.5 V DC and measuring the proportion of this signal imposed on the full-scale output voltage after subtracting the zero scale change. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Voltage output range V O R L = 10kΩ 0V DD -0.4 V Output load regulation accuracy V O (OUT) = 2V RL=2kΩ 0.5 LSB Output short circuit current IOSC OUT to VDD or AGND 20 mA Output voltage, low level V OL(low) IO (OUT) <= 5mA 0.25 V Output voltage, high level V OH(high) IO (OUT) <= -5mA 4.75 V

Output voltage high V OH IO = -2mA V DD -1 V Output voltage low V OL IO = 2mA 0.4 V PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Supply voltage V DD 4.5 5 5.5 V VDD = 5.5V, no load. Vref = 0V 150 250 µ A Power supply current IDD All inputs = 0V or VDD VDD = 5.5V, no load. Vref = 2.048V 230 350 µ A All inputs = 0V or VDD High level digital input voltage VIH 2.4 V Low level digital input voltage VIL 0.8 V High level digital input current IIH VI = VDD ±1 µ A Low level digital input current IIL VI = 0V ±1 µ A Input capacitance C I 8p F Digital Output (DOUT) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Input voltage range V I 0V DD -2 V Input resistance 10 M Ω Input capacitance C I 5p F Digital Inputs (DIN, SCLK, CS) Electrical Characteristics (continued) VDD = 5.0V ±5%, Vref = 2.048V unless otherwise stated. Reference Input (REFIN) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Power Supply PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT

Setup time, DIN before SCLK high t su (DS) 45 ns Hold time, DIN valid after SCLK high t h (DH) 0 ns Setup time, CS low to SCLK high t su (CSS) 1 ns Setup time CS high to SCLK high t su (CS1) 50 ns Hold time, SCLK low to CS low t h (CSHO) 1 ns Hold time, SCLK low to CS high t h (CSHI) 0 ns Pulse duration, min. chip select pulse width height tw (CS) 20 ns Pulse duration, SCLK low t w (CL) 18 ns Pulse duration, SCLK high tw (CH) 18 ns Output Switching Specification PARAMETER SYMBOL MIN TYP MAX UNIT Output slew rate SR C L = 100pF RL = 10 kΩ 0.3 0.5 V/ µ s TA = 25oC Output settling time t S TO 0.5 LSB CL = 100pF 12.5 µ s RL = 2kΩ (see note 9) Glitch energy DIN = All 0s to all 1s 5 nV . s Signal to noise + distortionS/(N+D) V ref = 2Vpp at 1kHz + 60 dB

2.048 V DC, code 512

Note 9: Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change from code zero to 1023 rising and 1023 to 64 falling. Digital Input Timing Specifications Electrical Characteristics (continued) VDD = 5.0V ±5%, Vref = 2.048V unless otherwise stated. Analogue Output Dynamic Performance PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Propagation delay time t pd (DOUT) C L = 50pF 50 ns Reference feedthrough Input code = 00 -80 dB (see note 10) Reference input bandwidth Input code = 512 100 kHz (see note 10) Note 10: Reference feedthrough and bandwidth are measured at the DAC output with Vref input = 2Vpp at 1kHz + 2.048V DC reference input (REFIN) PARAMETER CONDITIONS MIN TYP MAX UNIT

-0.2 -0.15 -0.1 -0.05 0. 05 0. 1 0. 15 0. 2 256 511 766 1021 -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 256 511 766 1021 Typical Performance Characteristics LSBs 0 256 512 768 1024 INPUT CODE WM5615 INL Linearity Error WM5615 DNL Linearity Error LSB 0 256 512 768 1024 INPUT CODE LSB

1 DIN Serial data input. 2 SCLK Serial clock input. 3 CS Chip select, active low.

4 DOUT Serial data output for daisy-

chaining. 5 AGND Analogue ground. 6 REFIN Reference input. 7 VOUT DAC output. 8 VDD Positive power supply. Timing Diagram Detailed Description General Function The WM5615 uses a resistor string network buffered with a single-supply CMOS op amp in a fixed gain of x2 to convert 10-bit digital data to analogue voltage levels (see Block Diagram). The topology of the WM5615 makes the output the same polarity as the reference input (see Ta- ble 1). An internal reset circuit forces the DAC register to reset to all 0s on power-up. VOUT R VDD AGND 0.1µF DOUTDIN SCLK R +5V CS REFIN Figure 1 - Typical Operating Circuit th(CSHO) tsu(CSS) th(CSH1) th(DH) tsu(DS) DIN DOUT SCLK CS tw(CH) tw(CL) tw(CS) tsu(CS1) tpd(DOUT) Previous LSB NOTES: A. The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimise clock feedthrough. B. Data input from preceeding conversion cycle. C. Sixteenth SCLK falling edge. See note ASee note C See note B

The WM5615 uses a three-wire serial interface which is compatible with SPI, QSPI (CPOL = CPHA = 0) and Microwire standards as shown in figures 2 and 3. The DAC is programmed by writing two 8-bit words, MSB first (see Block Diagram and Timing Diagram). 16 bits of serial data are clocked into the DAC in the following or- der, 4 fill (dummy) bits, 10 data bits and 2 sub-LSB Xs. The 4 dummy bits are not normally needed and are re- quired only when DACs are daisy chained. The 2 sub- LSB Xs, however, are always needed because the input register is 12 bits wide. Transitions at CS should occur while SCLK is low. Data is clocked in on the SCLK rising edge while CS is low. The serial input data is held in a 16- bit serial shift register. On the CS rising edge, the ten data-bits are transferred to the DAC register and update the DAC. With CS high, data cannot be clocked into the DIN terminal. The WM5615 receives data in 16-bit blocks. The SPI and Microwire interfaces output data in 8-bit blocks requiring two write cycles to input data to the DAC. The QSPI interface allows variable data output from 8 to 16 bits so can load into the DAC in one write cycle. Buffer Amplifier The output buffer is a rail-to-rail output CMOS op amp. Max. setting time is 12.5µs to +/-0.5 LSB of final value. The output is short-circuit protected and can drive a 2kΩ load with a 100pF load capacitance. External Reference The external voltage input is buffered and must be posi- tive but less than V DD - 2V. The reference voltage deter- mines the DAC full-scale output. Since the reference terminal is buffered, the DAC input resistance is not code dependent and is 10MΩ minimum. The REFIN input ca- pacitance is typically 5pF. Digital Interface The digital inputs are designed to be compatible with TTL or CMOS logic levels. However, to achieve the lowest power dissipation, the digital inputs should be driven with rail-to-rail CMOS logic. With TTL logic levels, the power requirement increases by a factor of approximately two. INPUT* OUTPUT 1111 1111 11 (xx) +2(V REFIN ) 1000 0000 01 (xx) +2(VREFIN ) 1000 0000 00 (xx) +2(VREFIN ) = VREFIN 01 11 1111 11 (xx) +2(VREFIN ) 0000 0000 01 (xx) +2(VREFIN ) 0000 0000 00 (xx) 0V Detailed Description (Continued) 1023 1024 513 1024 511 1024 1024 Table 1 - Binary Code Table (0V to 2VREFIN Output), Gain = 2 512 1024 * A 10-bit data word with two sub-LSB Xs must be written since the DAC input latch is 12-bits wide.

Plastic Small-Outline Package Notes: A. Dimensions in millimeters. B. Complies with Jedec standard MS-012. C. This drawing is subject to change without notice. D. Body dimensions do not include mold flash or protrusion. E. Dimension A, mould flash or protrusion shall not exceed 0.15mm. Body width, interlead flash or protrusions shall not exceed 0.25mm. NM i n M a x 8 4.80 5.00 14 8.55 8.75 16 9.80 10.00 Dimension 'A' Variations D - 8 pins shown 0.51 0.33 1.75 1.35 0.25

0.10 Pin spacing

1.27 B.S.C. 1.27 0.40 0 to 8 OO 0.25 0.19 0.50 0.25 x 45 NOM O 6.20 5.80 4.00 3.80 A Rev. 1 November 96

Notes: A. Dimensions are in inches B. Falls within JEDEC MS-001( 20 pin package is shorter than MS-001) C. N is the maximum number of terminals D. All end pins are partial width pins as shown, except the 14 pin package which is full width. Dimension 'A' Variations Dual-In-Line Package N or P Rev. 1 November 96 NM i n M a x 8 0.355 0.400 14 0.735 0.775 16 0.735 0.775 20 0.940 0.975 0.210 Max. 0.070 Max. 0.045 0.030 0.022 0.014 0.015 Min. 0.150 0.115 0.005 Min. Pin spacing 0.100 B.S.C. N Seating plane 0.280 0.240 0.325 0.290 0.014 0.008 105 O O N/2 A