WM2630 WOLFSON | Alldatasheet

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Technical content

Octal 12-bit, Serial Input, Voltage Output DAC with Internal Reference Production Data, February 2001, Rev 1.1 WOLFSON MICROELECTRONICS LTD Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk www.wolfsonmicro.co.uk Production Data datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics’ Terms and Conditions. Ó 2001 Wolfson Microelectronics Ltd.

FEATURES

  • Eight 12-bit DACs in one package
  • Dual supply 2.7V to 5.5V operation
  • DNL –0.5 LSBs, INL –2.0 LSBs typ.
  • Programmable settling time / power (1.0m s typ. in fast mode)
  • Internal programmable Voltage Reference
  • Microcontroller compatible Serial Interface
  • Power Down Mode ( < 0.1m A)
  • Monotonic over Temperature
  • Data Output for Daisy Chaining

APPLICATIONS

  • Battery powered test instruments
  • Digital offset and gain adjustment
  • Battery operated / remote industrial controls
  • Programmable Loop Controllers
  • CNC Machine Tools
  • Machine and motion control devices
  • Wireless telephone and communication systems
  • Robotics

ORDERING INFORMATION

DEVICE TEMP. RANGE PACKAGE WM2630CDT 0 ° to 70°C 20-pin TSSOP WM2630IDT -40 ° to 85°C 20-pin TSSOP

DESCRIPTION

The WM2630 is an octal, 12-bit, resistor string digital-to- analogue converter. The eight individual DACs contained in the IC can be switched in pairs between fast and slow (low power) operation modes, or powered down, under software control. Alternatively, the whole device can be powered down, reducing current consumption to less than 0.1mA. The DAC outputs are buffered by a rail-to-rail amplifier with a gain of two, which is configurable as Class A (fast mode) or Class AB (for low-power mode). The WM2630 has been designed to interface directly to industry standard microprocessors and DSPs, and can operate on two separate analogue and digital power supplies. It is programmed with a 16-bit serial word comprising 4 address bits and up to 12 DAC or control register data bits. All eight DACs can be simultaneously forced to a preset value using a preset input pin. A daisy-chain data output makes it possible to control several of Wolfson’s octal DACs from the same interface, without increasing the number of control lines. The device is available in a 20-pin TSSOP package. Commercial temperature (0° to 70°C) and Industrial temperature (-40° to 85°C) variants are supported. BLOCK DIAGRAM TYPICAL PERFORMANCE LATCH POWER/SPEED CONTROL RESISTOR STRING (12) OUT A DAC A DIN (2) SCLK (3) FS (4) PREB (5) 1.024V / 2.048V SELECTABLE REFERENCE DOUT (19) REF (16) DACs B, C, D, E, F, G, H as DAC A (6-9, 13-15) OUT B to H REF SERIAL INTERFACE AND CONTROL LOGIC MODE (17) AVDD (11) DVDD (20) AGND (10) DGND (1) LOADB (18) -0.75 -0.5 -0.25 0.25 0.5 0.75 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL CODE Differential Non-Linearity (LSBs)

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001 PIN CONFIGURATION OUTH AGND OUTA AVDD DVDD OUTC OUTD REF MODE LOADB DOUT OUTB8 OUTG DIN SCLK FS PREB OUTE OUTF DGND PIN DESCRIPTION PIN NO NAME TYPE DESCRIPTION

1 DGND Supply Digital Ground

2 DIN Digital input Digital serial data input

3 SCLK Digital input Serial clock input

4 FS Digital input Frame sync input

5 PREB Digital input Preset input

6 OUTE Analogue output DAC Output E

7 OUTF Analogue output DAC Output F

8 OUTG Analogue output DAC Output G

9 OUTH Analogue output DAC Output H

10 AGND Supply Analogue Ground

11 AVDD Supply Analogue positive power supply

12 OUTA Analogue output DAC Output A

13 OUTB Analogue output DAC Output B

14 OUTC Analogue output DAC Output C

15 OUTD Analogue output DAC Output D

16 REF Analogue I/O Voltage reference input / output

17 MODE Digital input Input mode

18 LOADB Digital input Load DAC

19 DOUT Digital output Data serial data output

20 DVDD Supply Digital positive power supply

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to dama ge from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION MIN MAX Digital supply voltages, AVDD or DVDD to GND 7V Reference input voltage -0.3V AVDD + 0.3V Digital input voltage range to GND -0.3V DVDD + 0.3V Operating temperature range, TA WM2630CDT WM2630IDT 0°C -40°C 70°C 85°C Storage temperature -65°C 150 °C Soldering lead temperature, 1.6mm (1/16 inch) from package body for 10 seconds 260°C RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Supply voltage AVDD, DVDD 2.7 5.5 V High-level digital input voltageVIH See Note 2 V Low-level digital input voltage VIL See Note 0.8 V AVDD = 5V GND 2.048 AVDDReference voltage to REF VREF AVDD = 3V GND 1.024 AVDD V Output Load Resistance R L 2k W Load capacitance C L 100 pF WM2630CDT 0 70 °COperating free-air temperature TA WM2630IDT -40 85 °C Note: Reference input voltages greater than AVDD/2 will cause saturation for large DAC codes.

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001

ELECTRICAL CHARACTERISTICS

Test Characteristics: R L = 10kW , CL = 100pF AVDD = DVDD = 5V ± 10%, VREF = 2.048V and AVDD = DVDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Static DAC Specifications Resolution 12 bits Integral non-linearity INL Code 40 to 4095 (see Note 1) ±2 ±6 LSB Differential non-linearity DNL Code 40 to 4095 (see Note 2) ±0.5 ±1 LSB Zero code error ZCE See Note 3 ±30 mV Gain error GE See Note 4 ±0.6 % FSR DC power supply rejection ratio PSRR See Note 5 -50 dB Zero code error temperature coefficient See Note 6 30 mV/°C Gain error temperature coefficient See Note 6 10 ppm/ °C DAC Output Specifications Output voltage range 10kW Load 0 AVDD-0.4 V Output load regulation 2kW to 10kW load See Note 7 ±0.3 % Full Scale Power Supplies Active supply current IDD No load, V IH=DVDD, V IL=0V AVDD = DVDD = 5V, VREF = 2.048V Slow Fast See Note 8 mA mA Power down supply current No load, all inputs 0V or DVDD 0.1 mA Dynamic DAC Specifications Slew rate DAC code 10%-90% Load = 10kW , 100pF Fast Slow See Note 9 V/ms V/ms Settling time DAC code 10%-90% Load = 10kW , 100pF Fast Slow See Note 10 ms ms Glitch energy Code 2047 to code 2048 4 nV-s Channel Crosstalk 10kHz sine wave, 4V pk-pk -90 dB

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001 Test Characteristics: R L = 10kW , CL = 100pF AVDD = DVDD = 5V ± 10%, VREF = 2.048V and AVDD = DVDD = 3V ± 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Reference Configured as Input Reference input resistance RREF 50 k W Reference input capacitance CREF 10 pF Reference feedthrough VREF =2VPP at 1kHz + 2.048V DC, DAC code 0 -84 dB Reference input bandwidth VREF = 0.4VPP + 2.048V DC, DAC code 2048 Slow Fast 1.9 2.2 MHz MHz Reference Configured as Output Low reference voltage VREFOUTL 1.010 1.024 1.040 V High reference voltage VREFOUTH VDD > 4.75V 2.020 2.048 2.096 V Output source current IREFSRC 1m A Output sink current IREFSNK -1 mA Load Capacitance in parallel with 100nF cap. 1 10 mF PSRR 60 dB Digital Inputs High level input current IIH Input voltage = DVDD 1 mA Low level input current IIL Input voltage = 0V -1 mA Input capacitance C I 8p F Notes: 1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full scale errors). 2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code. 3. Zero code error is the voltage output when the DAC input code is zero. 4. Gain error is the deviation from the ideal full-scale output excluding the effects of zero code error. 5. Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error. 6. Zero code error and Gain error temperature coefficients are normalised to full-scale voltage. 7. Output load regulation is the difference between the output voltage at full scale with a 10kW load and 2kW load. It is expressed as a percentage of the full scale output voltage with a 10kW load. 8. I DD is measured while continuously writing code 2048 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V supply current will increase. 9. Slew rate results are for the lower value of the rising and falling edge slew rates. 10.Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested.

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001 SERIAL INTERFACE X 1234 1 6 X XD 1 5 D14 D13 tWL D1 D0 X SCLK DIN XD 1 5 * D14 * D13 * D12 * D1 * D0 * XDOUT tWH tSUD tHD No high to low transitions tSUC16-FStWH FS tSUFSCLK FS (mC MODE) FS (DSP MODE) tWLFS * DIN data from previous word (delayed by 16 clock cycles) Figure 1 Timing Diagram SYMBOL TEST CONDITIONS MIN TYP MAX UNIT tSUFSCLK Setup time, FS pin low before first falling edge of SCLK 8n s tC16-FS Setup time, 16 th falling clock edge after FS low to rising edge of FS (only used in microcontroller mode) 10 ns tWLOADB Pulse duration, LOADB low 10 ns tWH Pulse duration, SCLK high 16 ns tWL Pulse duration, SCLK low 16 ns tSUD Setup time, data ready before SCLK falling edge 8n s tHD Hold time, data held valid after SCLK falling edge 5n s tWHFS Pulse duration, FS high 10 ns tWLFS Pulse duration, FS low 10 ns ts DAC Output settling time see Dynamic DAC Specifications

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001 DEVICE DESCRIPTION GENERAL FUNCTION The WM2630 is an octal 12-bit, voltage output DAC. It contains a serial interface, control logic for speed and power down, a programmable voltage reference, and eight digital to analogue converters. Each converter uses a resistor string network buffered with an op amp to convert 12-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and the input code according to the following relationship: Output voltage = 4096 CODE V2 REF INPUT OUTPUT 1111 1111 1111 4096 4095 V2 REF 1000 0000 0001 4096 2049 V2 REF 1000 0000 0000 () REFREF V 4096 2048 V2 = 0111 1111 1111 4096 2047 V2 REF 0000 0000 0001 4096 V2 REF 0000 0000 0000 0V Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2 POWER ON RESET An internal power-on-reset circuit resets the DAC register to all 0s on power-up. BUFFER AMPLIFIER The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2kW load with a 100pF load capacitance. PROGRAMMABLE REFERENCE The DAC reference can be sourced internally or externally under software control. If an external reference voltage is applied to the REF pin, the device must be configured to accept this. If an internal reference is selected, a voltage of 1.024V or 2.048 is available. The internal reference can source up to 1mA and can therefore be used as an external system reference.

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001 DAISY CHAINING MULTIPLE DEVICES The DOUT output (pin 19) provides the data sampled on DIN with a delay of 16 clock cycles. This signal can be used to control another WM2630 or similar device in a daisy-chain type circuit. DIN SCLK LOADB FS DIN SCLK LOADB FS DOUT OCTAL DAC #1 DIN SCLK LOADB FS DOUT OCTAL DAC #2 DIN SCLK LOADB FS DOUT OCTAL DAC #3 Figure 9 Daisy Chaining SOFTWARE CONFIGURATION OPTIONS DATA FORMAT The WM2630 is controlled with a 16-bit code consisting of four address bits, A0-A3, and 12 data bits. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0 Data Table 3 Input Data Format Using the four address bits, 16 different registers can be addressed. A3 A2 A1 A0 REGISTER 0 0 0 0 DAC A Code 0 0 0 1 DAC B Code 0 0 1 0 DAC C Code 0 0 1 1 DAC D Code 0 1 0 0 DAC E Code 0 1 0 1 DAC F Code 0 1 1 0 DAC G Code 0 1 1 1 DAC H Code 1 0 0 0 Control Register 0 1 0 0 1 Control Register 1 1 0 1 0 Preset all DACs 1 0 1 1 RESERVED 1 1 0 0 DAC A and complement B 1 1 0 1 DAC C and complement D 1 1 1 0 DAC E and complement F 1 1 1 1 DAC G and complement H Table 4 Register Map

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001 DAC A TO H CODE REGISTERS Addresses 0 to 7 are the DAC registers. The data written to these registers is transferred to the respective DAC when the LOADB input (pin 18) is low. For instantaneous updating, LOADB can be held low permanently. CONTROL REGISTER 0 Control register 0 (address 8) is used to select functions that apply to the whole IC, such as Power Down and Data Input Format. B I T D 1 1 D 1 0 D 9 D 8 D 7 D 6 D 5 D 4D 3D 2D 1D 0 F u n c t i o n X X XXXXXP DD O R 1 R 0 I M D e f a u l t XX X X X X X 00000 Table 5 Register Map BIT DESCRIPTION 0 1 PD Full device Power Down Normal Power Down DO DOUT Enable Disabled Enabled R1 Int / Ext Reference Select External Internal R0 Internal Reference Select 1.024V 2.048V IM Input Mode Straight Binary Two’s Complement X Reserved Table 6 Register Map CONTROL REGISTER 1 Control register 1 (address 9) is used to power down individual pairs of DACs and select their settling time. Powering down a pair of DACs disables their amplifiers and reduces the power consumption of the device. The settling time in fast mode is typically 1ms. In slow mode, the settling time is typically 3ms and power consumption is reduced. B I T D 1 1 D 1 0 D 9 D 8 D 7 D 6 D 5 D 4D 3D 2D 1D 0 Function X X X X P GH PEF PCD PAB SGH SEF SCD SAB D e f a u l t XX X X 0 0 0 0000 0 Table 7 Register Map BIT DESCRIPTION 0 1 PXY Power Down DACs X and Y Normal Power Down SXY Speed Setting for DACs X and Y Slow Fast Table 8 Register Map DAC PRESET REGISTER The Preset register (address 10) makes it possible to update all eight DACs at the same time. The value stored in this register becomes the digital input to all the DACs when the asynchronous PREB input (pin 5) is driven low. If no data has previously been written to the preset register, all DACs are set to zero scale. TWO-CHANNEL REGISTERS The two-channel registers (addresses 12 to 15) provide a ‘differential output’ function where writing data to one DAC will automatically write the complement to the other DAC in the pair. For example, writing a hexadecimal value of FFFF to address 12 will set DAC A to full scale and DAC B to zero scale.

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001 PROGRAMMABLE INTERNAL REFERENCE The reference can be sourced internally or externally under software control. If an external reference voltage is applied to the REF pin, the device must be configured to accept this. If an external reference is selected, the reference voltage input is buffered which makes the DAC input resistance independent of code. The REF pin has an input resistance of 10MW and an input capacitance of typically 55pF. The reference voltage determines the DAC full-scale output. If an internal reference is selected, a voltage of 1.024V or 2.048 is available. The internal reference can source up to 1mA and can therefore be used as an external system reference. REF1 REF0 REFERENCCE 0 0 External (default) 0 1 1.024V 1 0 2.048V

11 E x t e r n a l

Table 9 Programmable Internal Reference APPLICATIONS INFORMATION LINEARITY, OFFSET, AND GAIN ERROR Amplifiers operating from a single supply can have positive or negative voltage offsets. With a positive offset, the output voltage changes on the first code transition. However, if the offset is negative, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. This is because with the most negative supply rail being ground, any attempt to drive the output amplifier below ground will clamp the output at 0 V. The output voltage then remains at zero until the input code is sufficiently high to overcome the negative offset voltage, resulting in the transfer function shown in Figure 10. DAC codeNegative Offset Output Voltage 0 V Figure 10 Effect of Negative Offset This offset error, not the linearity error, produces the breakpoint. The transfer function would follow the dotted line if the output buffer could drive below the ground rail. DAC linearity is measured between zero-input code (all input bits at 0) and full-scale code (all inputs at 1), disregarding offset and full-scale errors. However, due to the breakpoint in the transfer function, single supply operation does not allow for adjustment when the offset is negative. In such cases, the linearity is therefore measured between full-scale and the lowest code that produces a positive (non-zero) output voltage. POWER SUPPLY DECOUPLING AND GROUNDING Printed circuit boards with separate analogue and digital ground planes deliver the best system performance. The two ground planes should be connected together at the low impedance power supply source. Ground currents should be managed so as to minimise voltage drops across the ground planes. A 0.1mF decoupling capacitor should be connected between the positive supply and ground pins of the DAC, with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analogue supply from the digital supply.

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001 PACKAGE DIMENSIONS q c L GAUGE PLANE 0.25 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. DM008.DDT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm) Symbols Dimensions (mm) MIN NOM MAX A ----- ----- 1.20 A 2 0.80 1.00 1.05 b 0.19 ----- 0.30 c 0.09 ----- 0.20 D 6.40 6.50 6.60 e 0.65 BSC E 6.4 BSC E1 4.30 4.40 4.50 L 0.45 0.60 0.75 q 0o ----- 8 o REF: JEDEC.95, MO-153 A A2 A1 SEATING PLANE 1120 E1 E eb 101 D -C- 0.1 C