WM2604 WOLFSON | Alldatasheet

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Quad 10-Bit Serial Input Voltage Output DAC Production Data, June 1999, Rev 1.0 WOLFSON MICROELECTRONICS LTD Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk http://www.wolfson.co.uk Production Data Datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics' Terms and Conditions.  1999 Wolfson Microelectronics Ltd .

FEATURES

  • Four 10-bit voltage output DACs
  • Dual 2.7V to 5.5V supply (separate digital and analogue supplies)
  • DNL ±±0.1 LSB, INL ±±0.4 LSB
  • Low power consumption: - 5.5mW, slow mode - 5V supply - 3.3mW, slow mode - 3V supply
  • TMS320, (Q)SPI  , and Microwire  compatible serial interface
  • Programmable settling time of 4 µµs or 12 µµs typical

APPLICATIONS

  • Battery powered test instruments
  • Digital offset and gain adjustment
  • Battery operated/remote industrial controls
  • Machine and motion control devices
  • Wireless telephone and communication systems
  • Speech synthesis
  • Arbitrary waveform generation

ORDERING INFORMATION

DEVICE TEMP. RANGE PACKAGE WM2604CDT 0° to 70°C 16-pin TSSOP WM2604IDT -40° to 85°C 16-pin TSSOP

DESCRIPTION

The WM2604 is a quadruple 10-bit voltage output, resistor string, digital-to-analogue converter. Each DAC can be individually powered down under software control. A hardware controlled mode is provided that powers down all DACs. Power down reduces current consumption to 10nA. The device has been designed to interface efficiently to industry standard microprocessors and DSPs, including the TMS320 family. The WM2604 is programmed with a 16-bit serial word comprising of a DAC address, individual DAC control bits and a 10-bit value. The WM2604 has provision for two supplies: one supply for the serial interface (DVDD, DGND ), and one for the DACs, reference buffers and output buffers (AVDD, AGND). This enables a typical application where the device can be controlled via a microprocessor operating on a 3V supply, with the DACs operating on a 5V supply. Alternatively, the supplies can be tied together in a single supply application. Excellent performance is delivered with a typical DNL of ±0.1 LSB. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The output stage is buffered by a x2 gain near rail-to-rail amplifier, which features a Class AB output stage. DACs A and B can have a different reference voltage to DACs C and D. The device is available in a 16-pin TSSOP package. Commercial temperature (0 ° to 70 °C) and Industrial temperature (-40 ° to 85 °C) variants are supported. BLOCK DIAGRAM TYPICA L PERFORMANCE (11) OUTD (12) OUTC (13) OUTB (14) OUTA 12-BIT DATA AND CONTROL HOLDING LATCH 10-BIT DAC LATCH16-BIT SHIFT REGISTER AND CONTROL LOGIC REFINAB (15) POWER-ON RESET DIN (4) FS (7) SCLK (5) NCS (6) (9) AGND (8) DGND (3) NLDAC (2) NPD AV DD (16) DV DD (1) DAC A DAC C DAC D POWERDOWN/ SPEED CONTROL WM2604 2-BIT CONTROL LATCH REFINCD (10) DAC B X1 DAC OUTPUT BUFFER data REFERENCE INPUT BUFFER AVDD = DVDD =5V, V REF = 2.048V, Speed = Fast mode, Load = 10k/100pF -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 0 256 512 767 1023 CODE DNL (LSB)

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 June 1999 PIN CONFIGURATION REFINCD OUTD OUTC OUTB OUTA AV DD REFINAB FS NCS SCLK DIN NLDAC DV DD NPD 8DGND 9 AGND PIN DESCRIPTION PIN NO NAME TYPE DESCRIPTION 1 DVDD Supply Digital supply. 2 NPD Digital input Power down. Powers down all DACs overriding their individual power down settings and all output stages. This pin is active low. 3 NLDAC Digital input Load DAC. Digital input active low. NLDAC must be taken low to update the DAC latch from the holding latches. 4 DIN Digital input Serial data input. 5 SCLK Digital input Serial clock input. 6 NCS Digital input Chip select. This pin is active low. 7 FS Digital input Frame synchronisation for serial input data. 8 DGND Ground Digital ground. 9 AGND Ground Analogue ground. 10 REFINCD Analogue input Voltage reference input for DACs C and D. 11 OUTD Analogue output DAC D output. 12 OUTC Analogue output DAC C output. 13 OUTB Analogue output DAC B output. 14 OUTA Analogue output DAC A output. 15 REFINAB Analogue input Voltage reference input for DACs A and B. 16 AVDD Supply Analogue supply.

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 June 99 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION MIN MAX Supply voltages, AVDD to AGND, DVDD to DGND 7V Supply voltage differences, AVDD to DVDD -2.8V 2.8V Digital input voltage -0.3V DVDD + 0.3V Reference input voltage -0.3V AVDD + 0.3V Operating temperature range, T A WM2604C WM2604I 0 °C -40 °C 70 °C 85 °C Storage temperature -65 °C 150 °C Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds 260 °C RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Supply voltage AVDD, DVDD 2.7 5.5 V High-level digital input voltage V IH DVDD = 2.7V to 5.5V 2 V Low-level digital input voltage V IL DVDD = 2.7V to 5.5V 0.8 V Reference voltage to REFINAB, REFINCD V REF See Note AVDD - 1.5 V Load resistance R L 2 10 k Ω Load capacitance C L 100 pF Serial clock rate f SCLK 20 MHz WM2604CDT 0 70 °COperating free-air temperature T A WM2604IDT -40 85 °C Note: Reference voltages greater than AVDD/2 will cause output saturation for large DAC codes.

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 June 1999

ELECTRICAL CHARACTERISTICS

Test Conditions: R L = 10k Ω , C L = 100pF. AVDD = DVDD = 5V ±± 10%, V REF = 2.048V and AVDD = DVDD = 3V ±± 10%, V REF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Static DAC Specifications Resolution 10 bits Integral non-linearity INL See Note 1 ±±0.4 ±±1 LSB Differential non-linearity DNL See Note 2 ±±0.1 ±±0.25 LSB Zero code error ZCE See Note 3 3 ±±12 mV Gain error GE See Note 4 0.25 ±±0.6 % FSR d.c. power supply rejection ratio DC PSRR See Note 5 0.5 mV/V Zero code error temperature coefficient See Note 6 10 ppm/ °C Gain error temperature coefficient See Note 6 10 ppm/ °C DAC Output Specifications Output voltage range 0 AVDD - 0.1 V Output load regulation 2k Ω to 10k Ω load See Note 7 0.1 0.25 % Power Supplies No load, V IH = DVDD, V IL = 0V AVDD = 5V, V REF = 2.048V Slow 1.4 2.2 AVDD = 5V, V REF = 2.048V Fast 3.5 5.5 AVDD = 3V, V REF = 1.024V Slow 1.0 1.5 Active supply current IDD AVDD = 3V, V REF = 1.024V Fast See Note 8 3.0 4.5 mA Power down supply current No load, all digital inputs 0V or DVDD See Note 9 0.01 10 µA Dynamic DAC Specifications Slew rate DAC code 32 to 1023, 10% to 90% Slow Fast See Note 10 0.5 2.5 1.0 4.0 V/ µs V/ µs Settling time DAC code 32 to 1023 Slow Fast See Note 11 12.0 4.0 µs µs Glitch energy Code 511 to 512 10 nV-s Signal to noise ratio SNR fs = 400ksps, f OUT = 1kHz, BW = 20kHz See Note 12 60 68 dB Signal to noise and distortion ratio SNRD fs = 400ksps, f OUT = 1kHz, BW = 20kHz See Note 12 54 65 dB Total harmonic distortion THD fs = 400ksps, f OUT = 1kHz, BW = 20kHz See Note 12 -68 -54 dB Spurious free dynamic range SPFDR fs = 400ksps, f OUT = 1kHz, BW = 20kHz See Note 12 54 70 dB

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 June 99 Test Conditions: R L = 10k Ω , C L = 100pF. AVDD = DVDD = 5V ±± 10%, V REF = 2.048V and AVDD = DVDD = 3V ±± 10%, V REF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Reference Reference input resistance R REFIN 10 M Ω Reference input capacitance C REFIN 5 pF Reference feedthrough V REF = 1V PP at 1kHz + 1.024V dc, DAC code 0 -75 dB Reference input bandwidth V REF = 0.2V PP + 1.024V dc DAC code 512 Slow Fast 0.5 MHz MHz Digital Inputs High level input current IIH Input voltage = DVDD 1 µA Low level input current IIL Input voltage = 0V -1 µA Input capacitance C I 3 pF Notes: 1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full scale errors). 2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code. 3. Zero code error is the voltage output when the DAC input code is zero. 4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error. 5. Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error. 6. Zero code error and Gain error temperature coefficients are normalised to full scale voltage. 7. Output load regulation is the difference between the output voltage at full scale with a 10k Ω load and 2k Ω load. It is expressed as a percentage of the full scale output voltage with a 10k Ω load. 9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test. 10. Slew rate results are for the lower value of the rising and falling edge slew rates. 11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested. 12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency f OUT generated with a sampling frequency fs .

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 June 1999 SERIAL INTERFACE NCS FS SCLK DIN 1 2 3 4 5 15 16 D0D1D12D13D14D15 t WL t WH t SUD t HD t SUCSFS t SUC16CS t WHFS t SUFSCLK t SUC16FS Figure 1 Timing Diagram Test Conditions: R L = 10k Ω , C L = 100pF. AVDD = DVDD = 5V ±± 10%, V REF = 2.048V and AVDD = DVDD = 3V ±± 10%, V REF = 1.024V over recommended operating free-air temperature range (unless noted otherwise) SYMBOL TEST CONDITIONS MIN TYP MAX UNIT tSUCSFS Setup time NCS low before negative FS edge. 10 ns tSUFSCLK Setup time FS low before first negative SCLK edge. 8 ns tSUC16FS Setup time, sixteenth negative SCLK edge after FS low on which D0 is sampled before rising edge of FS. 10 ns tSUC16CS Setup time, sixteenth positive SCLK edge (first positive after D0 sampled) before NCS rising edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup time is between the FS rising edge and the NCS rising edge. 10 ns tWHCLK Pulse duration, SCLK high. 25 ns tWLCLK Pulse duration, SCLK low. 25 ns tSUDCLK Setup time, data ready before SCLK falling edge. 8 ns tHDCLK Hold time, data held valid after SCLK falling edge. 5 ns tWHFS Pulse duration, FS high. 20 ns

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 June 1999 DEVICE DESCRIPTION GENERAL FUNCTION The device uses a resistor string network buffered with an op amp to convert 10-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and the input code according to the following relationship: Output voltage = ( ) 1024 CODEV2 REF INPUT OUTPUT 11 1111 1111 ( )1024 1023V2 REF : : 10 0000 0001 ( )1024 513V2 REF 10 0000 0000 ( ) REFREF V1024 512V2 = 01 1111 1111 ( )1024 511V2 REF : : 00 0000 0001 ( )1024 1V2 REF 00 0000 0000 0V Table 1 Binary Code Table (0V to 2V REFIN Output), Gain = 2 POWER ON RESET An internal power-on-reset circuit resets the DAC registers to all 0s on power-up. BUFFER AMPLIFIER The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2k Ω load with a 100pF load capacitance. EXTERNAL REFERENCE The reference voltage input is buffered which makes the DAC input resistance independent of code. REFINAB and REFINCD pins have an input resistance of 10M Ω and an input capacitance of typically 5pF. The reference voltage determines the DAC full-scale output. HARDWARE CONFIGURATION OPTIONS The device has two configuration options that are controlled by device pins. DEVICE POWER DOWN The device can be powered-down by pulling pin NPD (Pin 2) high. This powers down all DACs overriding their individual power down settings. This will reduce power consumption to typically 10nA. When the power down function is released the device reverts to the DAC code set prior to power down. SIMULTANEOUS DAC UPDATE The NLDAC pin (Pin 3) can be held high to prevent serial word writes from updating the DAC latches. By writing new values to multiple DACs then pulling NLDAC low, all new DAC codes are loaded into the DAC latches simultaneously.

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 June 99 SERIAL INTERFACE Explanation of data transfer: First, the device has to be enabled with NCS set to low. Then, a falling edge of FS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred, the next rising edge on SCLK or FS causes the content of the shift register to be moved to the DAC holding latch. If NLDAC is low, the DAC latch will also be updated immediately. The serial interface of the device can be used in two basic modes:

  • four wire (with chip select)
  • three wire (without chip select) Using chip select ( four wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or microcontroller). If there is no need to have more than one device on the serial bus, then NCS can be tied low. SERIAL CLOCK AND UPDATE RATE Figure 1 shows the device timing. The maximum serial rate is: f SCLK max = MHz20tt minWCLminWCH The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC settling time to 10 bits limits the update rate for large input step transitions. SOFTWARE CONFIGURATION OPTIONS The 16 bits of data can be transferred with the sequence shown in Table 2. D11-D2 contains the 10-bit data word. D15-D12 hold the programmable options. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A1 A0 PWR SPD New DAC value (10 bits) X X Table 2 Register Map DAC ADDRESSING A particular DAC (A, B, C, D) within the device is selected by A1 and A0 within the input word. A1 A0 DAC ADDRESS 0 0 DAC A 0 1 DAC B 1 0 DAC C 1 1 DAC D PROGRAMMABLE SETTLING TIME (SPD – BIT D12) Settling time is a software selectable 12 µs or 4 µs, typical to within ±0.5LSB of final value. This is controlled by the value of SPD – Bit D12 and an associated DAC address. A ONE defines a settling time of 4 µs , a ZERO defines a settling time of 12 µs for that DAC. PROGRAMMABLE POWER DOWN The power down function is controlled by PWR - Bit D13 and an associated DAC address. A ZERO configures that DAC as active , a ONE configures that DAC into power down mode.

WOLFSON MICROELECTRONICS LTD PD Rev 1.0 June 1999 PACKAGE DIMENSIONS NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. DM013.ADT: 16 PIN TSSOP ( 5.0 x 4.4 x 1.0 mm ) Symbols Dimensions (mm) MIN NOM MAX A ----- ----- 1.20 A 2 0.80 1.00 1.05 b 0.19 ----- 0.30 c 0.09 ----- 0.20 D 4.90 5.00 5.10 e 0.65 BSC E 6.4 BSC E 1 4.30 4.40 4.50 L 0.45 0.60 0.75 θθ 0 o ----- 8 o REF: JEDEC.95, MO-153 A A2 A1 SEATING PLANE -C- 0.05 C θθ c L GAUGE PLANE 0.25 D 916 E1 E eb