WM2331

WM2331 WOLFSON | Alldatasheet

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10-bit 30MSPS ADC with PGA and Clamp Production Data, April 2001, Rev 1.4 WOLFSON MICROELECTRONICS LTD Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk www.wolfsonmicro.com Production Data datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics’ Terms and Conditions.  2001 Wolfson Microelectronics Ltd.

DESCRIPTION

The WM2331 is a high speed, 10-bit pipeline analogue-to- digital converter (ADC) with on-chip programmable gain amplifier (PGA) and clamp circuit, and internal voltage references. Conversion is controlled by a single clock input. The device has a high bandwidth differential sample and hold input, which gives excellent common-mode noise immunity and low distortion. Alternatively, it can be driven in single ended fashion with an optional voltage clamp for DC restoration that can take its reference from an on-chip 10-bit DAC or an external source. The WM2331 provides internal reference voltages for setting the ADC full-scale range without the requirement for external circuitry. However, it can also accept external references for applications where common or high-precision references are required. A bidirectional 10-bit parallel interface is used both to control the device and to read ADC conversion data. ADC data can be output in unsigned binary or two’s complement format. An out-of-range output pin indicates when the input signal is outside the converter’s range. The WM2331 operates with independent analogue and digital supplies of 3V to 5.5V and is supplied in a 28-pin TSSOP package.

FEATURES

• 10-bit resolution ADC
• 30MSPS conversion rate
• Programmable Gain Amplifier (PGA)
• Built in clamp function (DC restore) with 10-bit DAC
• Adjustable internal voltage references
• Wide Input Bandwidth - 150MHz
• Unsigned Binary or Two’s complement output format
• Programmable via parallel interface
• Independent analogue and digital supplies, 3V to 5.5V
• Low power - 92mW typical at 3.0V supplies
• Powerdown mode to 3mW typical
• 28-pin TSSOP package

APPLICATIONS

• Composite Video Digitisation
• Digital Copiers
• Digital Video Cameras
• Set Top Box (STB)
• IF and Baseband Digitisation
• Medical Imaging
• High Speed Data Acquisition BLOCK DIAGRAM AIN ON-CHIP REFERENCE GENERATOR ADC Core S/H PGAREFTS DIO[9:0]INPUT/ OUTPUT BUFFERS OVR REFBS MODE REFSENSE AGNDAVDD REFBF REFTF CLAMP LEVEL DAC CLAMP AMPLIFIER OEB DGND DVDD CONTROL REGISTERS CLAMP CLAMPIN M U X WR TIMING CONTROL CLK VREF WM2331

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001 PIN CONFIGURATION ORDERING INFORMATION DEVICE TEMP. RANGE PACKAGE WM2331CDT/V 0 to +70 oC 28-pin TSSOP WM2331IDT/V -40 to +85 oC 28-pin TSSOP 1514 DIO0 OVR OEB AGND DVDD REFTS REFBS REFBF REFTF MODE VREF AIN AVDD DIO8 REFSENSE DIO2 DIO3 DIO1 DIO7 CLAMP DIO6 DIO5 CLAMPIN DIO4 DIO9 DGND WR CLK PIN DESCRIPTION PIN NAME TYPE DESCRIPTION

1 AGND Ground Negative Analogue Supply

2 DVDD Supply Positive Digital Supply

3 DIO0 Digital Input/Output Digital input/output bit 0 (LSB)

4 DIO1 Digital Input/Output Digital input/output bit 1

5 DIO2 Digital Input/Output Digital input/output bit 2

6 DIO3 Digital Input/Output Digital input/output bit 3

7 DIO4 Digital Input/Output Digital input/output bit 4

8 DIO5 Digital Input/Output Digital input/output bit 5

9 DIO6 Digital Input/Output Digital input/output bit 6

10 DIO7 Digital Input/Output Digital input/output bit 7

11 DIO8 Digital Input/Output Digital input/output bit 8

12 DIO9 Digital Input/Output Digital input/output bit 9 (MSB)

13 OVR Digital Output Overrange output (tri-state)

14 DGND Ground Negative Digital Supply

15 CLK Analogue Input Clock input

16 OEB Digital Input Output enable bar – low to enable DIO[9:0] and OVR

17 WR Digital Input Write strobe

18 REFSENSE Analogue Input VREF mode control

19 CLAMP Digital Input Clamp control – high to enable clamp amplifier

20 CLAMPIN Analogue Input Clamp reference input

21 REFTS Analogue Input/Output Top reference sense

22 REFTF Analogue Input/Output Top reference force

23 MODE Analogue Input Input mode select

24 REFBF Analogue Input/Output Bottom reference force

25 REFBS Analogue Input/Output Bottom reference sense

26 VREF Analogue Input/Output Reference voltage

27 AIN Analogue Input Analog Input

28 AVDD Supply Positive Analogue Supply

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. As per JEDEC specifications A112 and A113, this product requires specific storage conditions prior to surface mount assembly. It has been classified as having a Moisture Sensitivity Level of 2 and as such will be supplied in vacuum-sealed moisture barrier bags. CONDITION MIN MAX Digital supply voltage, DVDD to DGND -0.3V +6.5V Analogue supply voltage, AVDD to AGND -0.3V +6.5V Supply voltage difference, AVDD to DVDD -6.5V +6.5V Ground difference, AGND to DGND -0.3V +0.3V Voltage range digital inputs (DIO[9:0], WR, CLAMP, OEB) DGND - 0.3V DVDD + 0.3V Voltage range analogue inputs (REFTS, REFBS, REFTF, REFBF, AIN, VREF, REFSENSE, CLK, MODE) AGND - 0.3V AVDD + 0.3V WM2331CDT 0°C+ 7 0 °COperating temperature range, TA WM2331IDT -40°C+ 8 5 °C Storage temperature -65°C +150 °C Lead temperature (1.6mm from package body for 10 seconds) +300°C RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN NOM MAX UNIT Digital supply range DVDD 3.0 3.0 5.5 V Analogue supply range AVDD 3.0 3.0 5.5 V Ground DGND,AGND 0 V Clock frequency fCLK 53 0 M H z Clock duty cycle 45 50 55 % WM2331C 07 0 °COperating Free Air Temperature TA WM2331I -40 85 °C

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001

ELECTRICAL CHARACTERISTICS

Test Conditions: AVDD = DVDD = 3.0V, fCLK = 30MHz, 50% duty cycle, MODE = AVDD, REFTS = 2.5V, REFBS = 0.5V, PGA gain = 1.0, TA = TMIN to TMAX , unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DC Accuracy Integral nonlinearity INL ±1.0 ±2.0 LSB Differential nonlinearity DNL ±0.3 ±1.0 LSB Offset error 0.4 2.0 % of FS Gain error 1.4 3.5 % of FS Missing codes No missing codes guaranteed Analogue Input Signal to AIN pin MODE = AGND REFBS REFTS MODE = AVDD / 2, VCMCS fixed VCMCS - VREF/2 VCMCS + VREF/2 VInput signal range for unity PGA gain (see Note 1) MODE = AVDD REFBS REFTS AIN voltage limits AGND AVDD V Switched input capacitance 1.2 pF Analogue input bandwidth -3dB amplitude 150 MHz DC leakage current ± Full-scale input ±100 µA Conversion Characteristics Conversion frequency fCLK 53 0 M H z Pipeline delay 3 cycles of CLK Aperture delay tA 4.0 ns Aperture jitter 2.0 ps rms Dynamic Performance fIN = 3.5MHz 8.2 9.0Effective number of bits ENOB fIN = 15MHz 7.7 bits fIN = 3.5MHz 55 60Spurious free dynamic range SFDR fIN = 15MHz 48 dB fIN = 3.5MHz -58 -54.7Total harmonic distortion THD fIN = 15MHz -47 dB fIN = 3.5MHz 51.2 56Signal to noise ratio SNR fIN = 15MHz 53 dB fIN = 3.5MHz 51.1 56Signal to noise and distortion ratio SNDR fIN = 15MHz 48 dB PGA Gain range (linear scale) 0.5 4 V/V Gain step size (linear scale) 0.5 V/V Gain error from nominal 3% Clamp Clamp DAC resolution 10 bits Clamp DAC output voltage REFBF REFTF V Clamp DAC DNL -1 1 LSB Clamp DAC DNL ±1 LSB External clamp reference on CLAMPIN 0.1 AVDD - 0.1 V Clamp output voltage error -40 40 mV

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001 Test Conditions: AVDD = DVDD = 3.0V, fCLK = 30MHz, 50% duty cycle, MODE = AVDD, REFTS = 2.5V, REFBS = 0.5V, PGA gain = 1.0, TA = TMIN to TMAX , unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue Reference Inputs / Outputs in Top/Bottom Mode (MODE=AVDD) Bottom reference voltage applied to REFBS 0 AVDD - 1 V Top reference voltage applied to REFTS 1 AVDD V Differential reference input (REFTS – REFBS) VTB 12 V Reference input common mode (REFTS + REFBS) / 2 VCMTB 0.5 AVDD - 0.5 V Switched input capacitance on REFBS 0.6 pF Switched input capacitance on REFTS 0.6 pF REFBF output voltage (AVDD - VTB )/2 V REFTF output voltage (AVDD + VTB )/2 V Analogue Reference Inputs / Outputs in Centre-Span Mode (MODE=AVDD/2) Reference voltage derived or applied to VREF 12 V REFBF output voltage (AVDD - VREF)/2 V REFTF output voltage (AVDD + VREF)/2 V Non-AIN side of differential input applied to REFTS and REFBS VCMCS (Note 2) 0.5 AVDD - 0.5 V Analogue Reference Inputs / Outputs in Full External Reference Mode (MODE=AGND) (Note 3) Differential reference voltage applied (REFTF – REFBF) 12 V AVDD = 3.0V 1.3 1.5 1.7 VReference input common mode (REFTF + REFBF) / 2 AVDD = 5.0V 2.0 2.5 3.0 V Reference input resistance 680 Ω VREF Input / Output specifications Internal 1V reference to VREF REFSENSE = VREF 0.95 1.0 1.05 V Internal 2V reference to VREF REFSENSE = AGND 1.9 2.0 2.1 V External reference applied to VREF pin in centre-span mode REFSENSE = AVDD, MODE = AVDD / 2 12 V Input impedance in centre-span mode REFSENSE = AVDD, MODE = AVDD / 2 18 k Ω

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001 Test Conditions: AVDD = DVDD = 3.0V, fCLK = 30MHz, 50% duty cycle, MODE = AVDD, REFTS = 2.5V, REFBS = 0.5V, PGA gain = 1.0, TA = TMIN to TMAX , unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Power Supplies MODE = AGND, REFSENSE = AVDD 31 45 mA MODE = AVDD/2, REFSENSE = VREF 37 mAAnalogue supply current IAVDD MODE = AVDD, REFSENSE = AVDD 36 mA Digital supply current IDVDD C L = 10pF 6 mA Standby power consumption (digital and analogue combined)IVDD (STBY) 3 5 mW Digital Logic Levels (CMOS Levels) Input LOW level VIL (Note 2) 0.2 x VDD V Input HIGH level VIH (Note 2) 0.8 x VDD V Output LOW VOL IOL = -50µA0 . 2 V Output HIGH VOH IOH = 50µA VDD – 0.2 V Notes 1. V CMCS can be applied as a single voltage source to REFTS and REFBS with these two pins connected together. Alternatively the common mode of the input can be set by applying different voltage sources to these two pins, in which case the common mode voltage is effectively the average of these two voltages, V CMCS = (REFTS + REFBS)/2. 2. Digital input and output levels refer to the supply used for the input/output buffer on the relevant pin. CLK and MODE refer to the AVDD supply, all other digital input/output refers to the DVDD supply. 3. In full external reference mode the REFTF and REFTS pins should be shorted together, and the REFBF and REFBS pins should be shorted together. Please refer to device operation examples in the device description section of the datasheet.

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001 PROGRAMMABLE-GAIN AMPLIFIER VP is amplified by the PGA and fed into the ADC as a differential voltage VQ = VQ+ - VQ- () MINPQ VVGainVGainV −×=×= ANALOGUE-TO-DIGITAL CONVERTER Regardless of the reference configuration, VQ is digitised against ADC Reference Voltages REFTF and REFBF, full scale values of VQ being given by: REFBFREFTFVQFS −=+ and   −−=− REFBFREFTFVQFS Attempts to convert VQ voltages outside the range of VQFS- to VQFS+ are signalled to the application by driving the OVR output pin high. If VQ is less than VQFS- , the ADC output code is 0. If VQ is greater than VQFS+ , the output code is 1023. SIGNAL CHAIN SUMMARY Combining the above equations and referring back to the input, the positive and negative full-scale voltages at the AIN pin are: Gain REFBFREFTFVV MINFS −+=+ and Gain REFBFREFTFVV MINFS −−=− Therefore the input signal span is given by: Gain REFBFREFTFVV INFSINFS −=− −+ In order to match the ADC input range to the input signal amplitude, REFTF and REFBF should be set such that: GainVVREFBFREFTF INFSINFS ×−=− −+ )( ADC REFERENCE MODES The WM2331 supports three basic modes of reference generation, selected by the voltage applied to the MODE pin. These are summarised and explained in Table 1. In differential, Centre Span and Top/Bottom modes, the internally generated ADC references are intened solely for WM2331 internal use and REFTF and REFBF must not be used as voltage references for any other device in the application.

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001 MODE PIN MODE FUNCTION COMMENTS AGND Full external REFTSREFTF = REFBSREFBF = On-chip reference generator and reference buffer are not used. AVDD/2 Differential REFVAVDDREFTF += REFVAVDDREFTF −= VREF can be internally or externally generated. REFTS and REFBS are joined together and connected either to the negative end of the input signal (true differential mode) or to the AIN mid-scale voltage (centre-span mode). AVDD Top/Bottom () REFBSREFTSAVDDREFTF −+= REFBSREFTSAVDDREFBF −−= On-chip reference generator is not used. Reference buffer centers external reference voltages around AVDD/2. Table 1 WM2331 Reference Generation Modes FULL EXTERNAL REFERENCE MODE (MODE = AGND) When MODE is connected to AGND, the WM2331 operates in full external reference mode. The internal reference buffer is powered down and bypassed, so that the ADC core takes the user- supplied reference voltages at pins REFTS and REFBS (REFTS and REFBS are internally connected to REFTF and REFBF). The mean of REFTF and REFBF must be equal to AVDD/2. Only single-ended input is possible in this mode. SAMPLE AND HOLD REFTS REFBS AIN -1/2 -1/2 PGA REFTF REFBF INTERNAL REFERENCE BUFFER ADC CORE Figure 7 ADC Reference Generation in Full External Mode The full external mode of operation is useful when the application requires more accurate or lower drift reference voltages than the WM2331 can provide, or when devices need to share common reference voltages for best ADC matching. It also offers the possibility of using REFTS and REFBS as sense lines to drive the REFTF and REFBF lines (Kelvin mode) to eliminate any voltage drops from remote references within the system (see Figure 9). In Kelvin configurations, take care when choosing the external op-amps to ensure that they can drive large capacitive loads without oscillating. Although the on-chip reference generator is not used by the WM2331 in full external mode, its output is available on the VREF pin and can be used by other parts of the system. Note that in addition to the internal connections from REFTS to REFTF and REFBS to REFBF, external wire connections must also be made as shown in Figure 8 to minimise resistance (except in Kelvin mode).

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001 AVDD AIN REFSENSE REFTF REFBF +FS -FS REFTS REFBS MODE DC SOURCE = VM + [(FS+) - (FS-)]* GAIN/2 DC SOURCE = VM - [(FS+) - (FS-)]* GAIN/2 0.1µF10µF 0.1µF 0.1µF Figure 14 Top/Bottom Mode (Reference Generator Disabled) ON-CHIP REFERENCE VOLTAGE GENERATOR The On-chip Reference Generator (ORG) can provide a reference voltage on the VREF pin that is independent of temperature and supply voltage. External connections to the REFSENSE pin control the ORG’s output to VREF, as shown in Table 2. REFSENSE CONNECTION ORG OUTPUT TO VREF VREF pin 1 Volt AGND 2 Volts External divider junction (1 + RA/RB) Volts – see Figure 15 AVDD None (VREF becomes input pin) Table 2 Controlling the On-chip Reference Generator Connecting REFSENSE to AVDD powers the ORG down, saving power when the ORG function is not required. In differential mode (MODE = AVDD/2), the voltage on VREF determines the ADC reference voltages as follows: REFVAVDDREFTF += REFVAVDDREFBF −= REFVREFBFREFTF =− When the ORG is enabled, the VREF pin should be decoupled to the circuit board’s analogue ground plane close to the WM2331 AGND pin via a 1µF tantalum capacitor and a 0.1µF ceramic capacitor. The ORG can source currents up to 1mA into external grounded loads when it is not used by the WM2331. Typical buffer load regulation is about 0.5Ω .

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001 After power up, the clamp reference voltage is the voltage supplied on the CLAMPIN pin. However, it can also be generated by the on-chip 10-bit clamp level DAC by suitably programming the WM2331 clamp and control registers (see Digital Control Registers, below). Clamp design for minimum acquisition time and droop is discussed in Applications Information. CLAMP DAC OUTPUT VOLTAGE RANGE AND LIMITS Important: When using the internal clamp DAC in Top/Bottom or Centre Span Mode, the user must ensure that the desired DC clamp level at AIN lies within the voltage range REFBF to REFTF. This is because the clamp DAC voltage is constrained to lie within this range REFBF to REFTF. Specifically: V DAC = REFBF + (REFTF /c237/c3/c53/c40/c41/c37/c41/c12/c3 × (0.006 + 0.988×(DAC code)/1024) DAC codes can range from 0 to 1023. Figure 18 shows the clamp DAC output voltage versus the DAC code. VDAC DAC code0 1023 VREFBF + 0.987(VREFTF-VREFBF) VREFBF VREFTF VREFBF + 0.006(VREFTF-VREFBF) Figure 18 Clamp DAC Output Voltage versus DAC Register Code Value If the desired DC level at AIN does not lie within the range REFTF to REFBF, then either:

• the CLAMPIN pin can be used instead to provide a suitable reference voltage or
• it may be possible to re-design the application to move the AIN input range into the CLAMP DAC voltage range. This is achieved in both Top/Bottom and Centre Span Modes by shifting both REFTS and REFBS up or down by the voltage through which the AIN input range is to be moved. POWER MANAGEMENT In power-sensitive applications (such as battery-powered systems) where the WM2331 ADC is not required to convert continuously, power can be saved between conversion intervals by placing the WM2331 into Power Down mode. This is achieved by setting bit 3 (PDWN) of the control register to 1. In Power Down mode, the device typically consumes less than 3mW of power. Power down mode is exited by resetting control register bit 3 to 0. On power up from long periods of power down, the WM2331 typically requires 5ms of wake up time before valid conversion results are available. In systems where the ADC must run continuously, but where the clamp is not required, the supply current can be reduced by approximately 1.2mA by setting the control register bit 6 (CLDIS), which disables the clamp circuit. Similarly, when REFSENSE is tied to AVDD, the reference generator is disabled and supply current reduced by approximately 1.2mA. OUTPUT FORMAT AND DIGITAL I/O While the OEB pin is held low, ADC conversion results are output at the data I/O pins DIO0 (LSB) to DIO9 (MSB). The default output data format is unsigned binary (output codes 0 to 1023). This can be switched to two’s complement format (output codes -512 to 511) by setting control register bit 5 (TWOC) to 1. WRITING TO THE INTERNAL REGISTERS THROUGH THE DIGITAL I/O BUS Pulling the OEB pin high disables the data and out-of-range indicator (OVR) pins’ output drivers, setting the driver outputs to a high impedance state. This allows control register data to be loaded into the WM2331 by presenting it on the DIO0 to DIO9 pins and pulsing the WR pin high to latch the data into the chosen control or DAC register.

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001 Figure 19 shows an example register write cycle where the clamp DAC code is set to 199 (hex) by writing to clamp registers 1 and 2 (see ‘Digital Control Registers’, below). Pins DIO0 to DIO7 are driven to the clamp DAC code lower byte (0F hex) and pins DIO8 and DIO9 are both driven to 0 to select clamp register 1 as the data destination. The clamp low-byte data is then loaded into this register by pulsing WR high. The top 2 bits of the DAC word are then loaded by driving 01(hex) on pins DIO0 to DIO7 and by driving pin DIO8 to 1 and pin DIO9 to 0 to select clamp register 2 as the data destination. WR is pulsed a second time to latch this second control word into clamp register 2. NOE WR DIO[9:0] OUTPUT OUTPUTINPUT 099 INPUT 101 Load 99 hex into register 0 Load 01 hex into register 1 Figure 19 Example Register Write Cycle to Clamp DAC Register DIGITAL CONTROL REGISTERS The WM2331 contains two clamp registers and a control register for user programming. Binary data can be written into these registers using pins DIO0 to DIO9 and the WR and OEB pins (see the previous section). In input mode, DIO9 and DIO8 are address bits and the remaining DIO pins are data bits. DATA BITS DIO[7:0] ADDRESS DIO[9:8] DESCRIPTION DEFAULT (HEX) READ/ WRITE DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0 00 Clamp Reg. 1 00 RW DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0] 01 Clamp Reg. 2 00 RW DAC[9] DAC[8] 10 Control Reg. 01 RW CLDIS TWOC CLINT PDWN PGA[2] PGA[1] PGA[0]

11 Reserved

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001 REGISTER BIT NO BIT NAME(S) DEFAULT DESCRIPTION Clamp Register 1 DIO[9:8] = 00 7:0 DAC[7:0] 0 Clamp DAC voltage (DAC[0] = LSB.) DAC[9:0] = 00h: Clamp voltage = REFBF DAC[9:0] = 3Fh: Clamp voltage = REFTF 7:2 UnusedClamp Register 2 DIO[9:8] = 01 1:0 DAC[9:8] 01 Clamp DAC voltage (DAC[9] = MSB) 2:0 PGA[2:0] 001 PGA gain: 000 = 0.5 001 = 1.0 010 = 1.5 011 = 2.0 100 = 2.5 101 = 3.0 110 = 3.5 111 = 4.0 3P D W N 0 Power down 0 = WM2331 powered up 1 = WM2331 powered down 4C L I N T 0 Clamp voltage internal/external 0 = external analogue clamp voltage from CLAMPIN pin. 1 = from on-chip DAC (see Clamp Register) 5T W O C 0 Output format 0 = unsigned binary 1 = two’s complement 6C L D I S 0 Clamp Amplifier Disable (for power saving) 0 = Enable 1 = Disable Control Register DIO[9:8] = 10

7 Unused

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001 REFERENCE DECOUPLING VREF PIN When the on-chip reference generator is enabled, the VREF pin should be decoupled to the circuit board’s analogue ground plane close to the WM2331 AGND pin via a 1µF tantalum capacitor and a 0.1µF ceramic capacitor. REFTF AND REFBF PINS In any mode of operation, the REFTF and REFBF pins should be decoupled as shown in Figure 28 below. Use short board traces between the WM2331 and the capacitors to minimise parasitic inductance. WM2331 REFTF REFBF 0.1µF 0.1µF 0.1µF10µF Figure 28 Recommended Decoupling for the ADC Reference Pins REFTF and REFBF SUPPLY DECOUPLING The analogue (AVDD, AGND) and digital (DVDD, DGND) power supplies to the WM2331 should be separately decoupled for best performance. Each supply needs at least a 10µF electrolytic or tantalum capacitor (as a charge reservoir) and a 100nF ceramic type capacitor placed as close as possible to the respective pins (to suppress spikes and supply noise). DIGITAL OUTPUT LOADING AND CIRCUIT BOARD LAYOUT The WM2331 outputs are capable of driving rail-to-rail with up to 20pF of load per pin at 30MHz clock and 3V digital supply. Minimising the load on the outputs will improve WM2331 signal-to-noise performance by reducing the switching noise coupling from the WM2331 output buffers to the internal analogue circuits. The output load capacitance can be minimised by buffering the WM2331 digital outputs with a low input capacitance buffer placed as close to the output pins as physically possible, and by using the shortest possible tracks between the WM2331 and this buffer. Noise levels at the output buffers, which may affect the analogue circuits within WM2331, increase with the digital supply voltage. Where possible, consider using the lowest DVDD that the application can tolerate. Use good layout practices when designing the application PCB to ensure that any off-chip return currents from the WM2331 digital outputs (and any other digital circuits on the PCB) do not return via the supplies to any sensitive analogue circuits. The WM2331 should be soldered directly to the PCB for best performance. Socketing the device will degrade performance by adding parasitic socket inductance and capacitance to all pins. USER TIPS FOR OBTAINING BEST PERFORMANCE FROM THE WM2331

• Choose differential input mode for best distortion performance.
• Choose a 2V ADC input span for best noise performance.
• Choose a 1V ADC input span for best distortion performance.
• Drive the clock input CLK from a low-jitter, fast logic stage, with a well-decoupled power supply and short PCB traces.

WOLFSON MICROELECTRONICS LTD PD Rev 1.4 April 2001 PACKAGE DIMENSIONS NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. DM022.ADT: 28 PIN TSSOP (9.7 x 4.4 x 1.0 mm) Symbols Dimensions (mm) MIN NOM MAX A ----- ----- 1.20 A1 0.05 ----- 0.15 A2 0.80 1.00 1.05 b 0.19 ----- 0.30 c 0.09 ----- 0.20 D 9.60 9.70 9.80 e 0.65 BSC E 6.4 BSC E1 4.30 4.40 4.50 L 0.45 0.60 0.75 θ 0 o ----- 8 o REF: JEDEC.95, MO-153 θ c L GAUGE PLANE 0.25 1528 E1 E eb 141 D SEATING PLANE A A2 A1 -C- 0.1 C