WM2148CFT/V

WM2148 WOLFSON | Alldatasheet

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14-bit 8MSPS Analogue-To-Digital Converter Production Data, February 2001, Rev 1.1 WOLFSON MICROELECTRONICS LTD Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk http://www.wolfson.co.uk Production Data datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics’ Terms and Conditions.  2001 Wolfson Microelectronics Ltd.

DESCRIPTION

The WM2148 is a 14-bit, 8 MSPS analogue to digital converter with an on-chip voltage reference, high bandwidth sample and hold amplifier and programmable gain. The analogue input is differential, giving excellent common- mode noise immunity and low distortion. The WM2148 is designed for use in highly integrated, low- power 3.3V systems. A high speed, microprocessor compatible parallel interface allows control of the ADC input gain, digital DC offset, internal / external reference and output data format. Both binary and two’s complement formats are supported. The device also features an out of range indicator pin to show when the input signal exceeds the converter’s full-scale range. In Power Down mode, all analogue circuitry is internally disconnected from the power supply, reducing total supply current to 20µA. The WM2148 is available in a 1mm thin 48-pin TQFP package in standard commercial and industrial temperature ranges.

FEATURES

• 14-bit resolution ADC
• 8 MSPS conversion rate
• Differential input
• 3.3V single supply
• Very low current power down mode - 20µA typical
• Microprocessor compatible parallel interface
• Internal or external voltage reference
• High bandwidth sample and hold amplifier - 140MHz full-power bandwidth
• Programmable Gain Amplifier (PGA)
• Programmable DC offset
• Binary or two’s complement output format
• Out of range indicator
• 48-pin TQFP package, body thickness 1mm

APPLICATIONS

• Communications
• xDSL Front ends
• Industrial control
• Instrumentation BLOCK DIAGRAM IN+ PARALLEL INTERFACE AND CONTROL LOGIC A[1:0] CSB WEB OEB ADC PGA -IN- D[13:0] OUTPUT BUFFERS REF+ REF- OVI CLK VBG WM2148 PRECISION REFERENCE

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001 PIN CONFIGURATION ORDERING INFORMATION DEVICE TEMP. RANGE PACKAGE WM2148CFT/V 0 to +70 oC WM2148IFT/V -40 to +85oC 48-pin TQFP 1 mm thick body IN- CSB DVDDCTRL A0 A1 NC NCIN+ AVDD2 AVSUB AGND1 AVDD1 D11 DGNDOP1 D10 DVDDOP1 DVDDOP3 WRB DVDDLOGIC CLK DGNDCLK DGNDCTRL OEB DGNDOP2 DVDDOP2 14 21 201918171615 24 232213 48 38 394041424344454647 37 DVDDCLK AGND2 AVDDREF VBG CML REF+ REF- AGNDREF VSUB DGNDLOGIC OVI D13 D12 PIN DESCRIPTION PIN NAME TYPE DESCRIPTION

1 IN- Analogue Input Negative Differential Analogue Input

2 AVDDREF Supply Positive Supply Voltage for Reference

3 VBG Analogue I/O Bandgap Voltage / External Reference

4 CML Analogue Output Reference Decoupling Point

5 REF+ Analogue Output Positive Reference Voltage

6 REF- Analogue Output Negative Reference Voltage

7 AGNDREF Supply Reference Block Ground

8 VSUB Supply Device Substrate

9 DGNDLOGIC Supply Digital Ground for Logic Block

10 OVI Digital Output Out of Range Indicator

11 D13 Digital I/O Data Bit 13

12 D12 Digital I/O Data Bit 12

13 D11 Digital I/O Data Bit 11

14 DVDDOP1 Supply Positive Supply for Output Drivers

15 DGNDOP1 Supply Ground for Output Drivers

16 D10 Digital I/O Data Bit 10

17 D9 Digital I/O Data Bit 9

18 D8 Digital I/O Data Bit 8

19 D7 Digital I/O Data Bit 7

20 DVDDOP3 Supply Positive Supply for Output Drivers

21 D6 Digital I/O Data Bit 6

22 D5 Digital I/O Data Bit 5

23 D4 Digital I/O Data Bit 4

24 D3 Digital I/O Data Bit 3

25 DGNDOP2 Supply Ground for Output Drivers

26 DVDDOP2 Supply Positive Supply for Output Drivers

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001 PIN NAME TYPE DESCRIPTION

27 D2 Digital I/O Data Bit 2

28 D1 Digital I/O Data Bit 1

29 D0 Digital I/O Data Bit 0

30 DVDDLOGIC Supply Positive Supply Voltage for Logic Block

31 DVDDCLK Supply Positive Supply Voltage for Clock

32 CLK Digital Input Sample Clock

33 DGNDCLK Supply Ground for Clock

34 DGNDCTRL Supply Ground for Control Pins

35 OEB Digital Input Output Enable (active low)

36 WRB Digital Input Write Signal (active low)

37 CSB Digital Input Chip Select (active low)

38 NC Test Output This pin must be left unconnected

39 NC Test Output This pin must be left unconnected

40 A1 Digital Input Address Bit 1

41 A0 Digital Input Address Bit 0

42 DVDDCTRL Supply Positive Supply for Control Pins

43 AVDD1 Supply Positive Supply for ADC

44 AGND1 Supply Ground for ADC

45 AVSUB Substrate ADC substrate

46 AGND2 Supply Positive Supply for ADC Op-amps

47 AVDD2 Supply Ground for ADC Op-amps

48 IN+ Analogue Input Positive Differential Analogue Input

Note: 1. It is recommended that each pair of supply pins, especially the analogue supplies, have a separate decoupling capacitor. The most critical are pins 46 and 47. The ADC substrate (pin 45) should be as noise free as possible.

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. As per JEDEC specifications A112 and A113, this product requires specific storage conditions prior to surface mount assembly. It has been classified as having a Moisture Sensitivity Level of 2 and as such will be supplied in vacuum-sealed moisture barrier bags. CONDITION MIN MAX Analogue Supply Voltage (AVDD to AGND) -0.3 4 V Digital Supply Voltage (DVDD to DGND) -0.3 4 V Reference Input Voltage Range (VBG) AGND -0.3V AV DD +0.3V Analogue Inputs Voltage Range AGND -0.3V AV DD +0.3V Digital Inputs Voltage Range DGND -0.3V DV DD +0.3V C suffix 0°C+ 7 0 °C Operating temperature range (TA) I suffix -40°C+ 8 5 °C Storage temperature -65°C +150 °C Lead temperature (soldering 10 seconds, 1.6 mm from package body) +260°C RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Supply Voltages (digital and analogue) AV DD , DVDD 3.0 3.3 3.6 V Reference Input Voltage VBG External reference 1.425 1.5 1.575 V Digital Input HIGH Level VIH 23 . 3 V Digital Input LOW Level VIL 00 . 8V Load Capacitance C L 51 5 p F Clock Frequency fCLK 0.1 8 8 MHz Clock Duty Cycle 40 50 60 % C Suffix 0 25 70 Operating Free-air Temperature TA I Suffix -40 25 85 °C

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001

ELECTRICAL CHARACTERISTICS

Electrical characteristics over recommended temperature range, AVDD = DVDD = 3.3V (unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Power Supplies Analogue Supply Current AI DD AV DD = 3.6V 81 90 mA Digital Supply Current DI DD DV DD = 3.6V 5 10 mA Power Consumption P AV DD = DVDD = 3.6V 270 360 mW Power Down Supply Current (sum of all supply currents) IPD = AIDD +DIDD Power down mode CLK signal stopped 20 µA DC Characteristics Resolution 14 bits Differential Nonlinearity DNL ± 0.6 ± 1 bits Integral Nonlinearity INL Best Fit ± 3 ± 5 bits Offset Error IN+ = IN-, 0dB gain 0.3 % of FSR Gain Error 0 dB gain 1 % of FSR AC Characteristics Analogue Input Bandwidth 140 MHz FIN = 100kHz -81 FIN = 1MHz -78Total Harmonic Distortion THD FIN = 4MHz -77 dB FIN = 1MHz 70 72Signal to Noise Ratio SNR FIN = 4MHz 71 dB FIN = 1MHz 69 70Signal to Noise plus DistortionSINAD FIN = 4MHz 70 dB FIN = 1MHz 73 80Spurious Free Dynamic Range SFDR FIN = 4MHz 80 dB Effective Number of Bits ENOB 11.2 11.5 bits Reference Voltage Bandgap Voltage V BG Internal reference 1.425 1.5 1.575 V Temperature Coefficient 40 ppm / °C Supply Voltage Coefficient 200 ppm / V VBG Input Impedance External reference 40 k Ω Positive Reference Voltage V REF+ VREF+ = VBG (1 + 2/3) 2.5 V Negative Reference Voltage V REF /c237 VREF+ = VBG (1 - 2/3) 0.5 V Reference Voltage Difference /c168/c57 REF /c168/c57 REF = VREF+ - VREF /c237 2.0 V Analog Inputs Positive Analogue Input Voltage V IN+ 0A V DD V Negative Analogue Input Voltage V IN/c237 0A V DD V Input Voltage Difference /c168/c57 IN /c168/c57 IN = VIN+ - VIN/c237 - /c168/c57 REF /c168/c57 REF V Input impedance Z IN 25 k Ω PGA Range 07 d B PGA Step Size 1d B PGA Gain Error ± 0.25 dB Digital Inputs Input LOW level V IL 0.8 V Input HIGH level V IH 2V Input current I IN ± 1 µA Input capacitance C IN 5p F

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001 PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Read Timing Address and Chip select Setup Time tsu(OE-ACS) C Load = 15pF 4 ns Output Enable ten C Load = 15pF 15 ns Output Disable tdis C Load = 15pF 10 ns Address Hold Time th(A) C Load = 15pF 1 ns Chip select Hold Time th(CS) C Load = 15pF 0 ns Note: 1. All timing parameters refer to a 50% level. WEB CSB XD[0:13] A[0:1] XDATA XX ADDRESS tsu(WE-CS) th(CS) tsu(DA) th(CS) Figure 3 Write Timing PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Write Timing Chip Select Setup Time tsu(WE /c237/c38/c54/c12 C Load = 15pF 4 ns Data and Address Setup Time tsu(DA) C Load = 15pF 29 ns Data and Address Hold Time th(DA) C Load = 15pF 0 ns Chip Select Hold Time th(CS) C Load = 15pF 0 ns Write Pulse Duration HIGH twH(WE) C Load = 15pF 15 ns Note 1. Data is written to the addressed register at the rising edge of WEB. All timing parameters refer to a 50% level.

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001 DEVICE DESCRIPTION INTRODUCTION The WM2184 is a fast, low-power 14-bit ADC designed for leading edge telecommunications applications such as xDSL front-ends. It consists of a high bandwidth programmable gain input stage, a high resolution ADC, a parallel control interface, and internal voltage reference circuitry. Its fully differential design gives it excellent noise immunity. The analogue signal first enters the programmable gain amplifier (PGA), whose gain can be controlled in 1dB steps between 0dB and 7dB, using the PGA gain register. The signal is then digitised with respect to the two reference voltages, V REF+ and V REF /c237 , in the ADC core. To compensate for DC offsets in the system, a programmable value of between -128 and +127 LSBs can be added to the digitised data. This is achieved by writing the offset value to the offset register and setting the DCO bit (bit 7) in the control register. Two different output formats are supported to suit the user’s needs. In unsigned binary format, an all- zero output represents the minimum analogue input level, while in two’s complement format it refers to the middle level between minimum and maximum (see Table 1, below). ANALOGUE INPUT DIGITAL OUTPUT (Unsigned Binary) DIGITAL OUTPUT (Two’s Complement) Minimum /c168/c57 IN = - /c168/c57 REF 0 -8192 Midrange /c168/c57 IN = 0 8192 0 Maximum /c168/c57 IN = /c168/c57 REF 16383 8191 Table 1 Unsigned Binary vs Two’s Complement Output Format The out-of-range indicator (OVI) output indicates that the analogue input signal is out of range. It is asserted whenever the differential input voltage /c168/c57 IN exceeds the differential reference voltage /c168/c57 REF or /c237/c168/c57 REF . This signal is updated simultaneously with the digital data outputs and is subject to the same pipeline delay. It can be used to adjust the gain of the internal PGA to prevent the ADC from clipping. The WM2148 incorporates a differential voltage reference circuit based on a 1.5V bandgap reference. The two reference voltages derived from the bandgap, V REF+ and VREF /c237 , are two-thirds above and below the bandgap voltage VBG , at 2.5V and 0.5V respectively. The analogue input range is between the two references. To use an external reference, the on-chip bandgap circuit is disabled by setting the REF bit (bit 12) in the control register. The external reference voltage can then be applied at the VBG pin. V REF+ and VREF /c237 are still buffered in the same by the internal reference amplifiers, such that:  +×=+ 21BGREF VV and   −×=− 21BGREF VV For best performance, VBG , VREF+ ,VREF /c237 and CML (reference midpoint, pin 4) should all be separately decoupled (see Recommended External Components). The WM2184 requires a single 3.3V supply voltage. In Power Down mode, the supply to all analogue circuitry in the device is switched off, reducing standby current to 20µA provided that the clock is stopped (a running clock will increase the power consumption of the digital sections). CONTROL INTERFACE All functions of the WM2184 are accessed through its parallel interface. There are four internal registers to retrieve the ADC conversion data, set the device gain and DC offset, and control other features such as Power Down, reference voltage and output format. The parallel interface of the WM2148 features three-state buffers for direct connection to a shared data bus. Driving the OEB pin low enables the output buffers.

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001 ADDRESS A1 A0 REGISTER 0 0 0 ADC Conversion Result 1 0 1 PGA gain 2 1 0 DC Offset 3 1 1 Control Table 2 WM2148 Internal Registers The ADC data register contains the result of the last analogue to digital conversion. It can also be used to reset the device to its default state by writing a ‘1’ to the LSB (D0). This will set all the bits in the gain, offset and control registers to ‘0’. All other bits should always be set to zero when writing to the ADC data register. The PGA gain is controlled using the last three bits of Address 1. The eight possible binary values of 000 to 111 (decimal 7) correspond to a gain of 0 to 7dB, respectively. The lower byte of Address 2 holds the offset value (in LSBs). This value is added to the ADC data if the DCO bit in the Control register is set. The offset is in Two’s complement format, providing a range of -128 to +127 LSB. R E G . / B I T D 1 3 D 1 2 D 1 1 D 1 0 D 9D 8D 7D 6D 5D 4D 3D 2D 1D 0 SR P G A G a i nXXXXXXXXXXX G 2 G 1 G 0 DC Offset X X X X X X MSB ……………… LSB C o n t r o l P W D R E F F O R T M 2 T M 1 T M 0 D C O XXXXXXX Table 3 WM2148 Register Map The Control register (address 3) has four bits to program the device’s operation and three test mode bits. Setting the Power Down bit (PWD) takes the device into Power Down mode. DCO enables the addition of the offset value held at Address 2 to the ADC output data. REF selects between internal and external reference voltages, and FOR between unsigned binary and Two’s complement output format. BIT DESCRIPTION 0 1 PWD Power Down Normal Operation Power Down REF Reference Select Internal Reference External Reference FOR Output Format Unsigned Binary Two ’s Complement DCO DC Offset Enable Disable SR Software Reset Normal Operation Reset X Reserved Always set to 0 when writing to any register. Table 4 Control Bits and Software Reset The ADC core can be tested by selecting one of six different test modes, which apply various voltages to the analogue inputs. This may be useful for calibration purposes. The test modes are controlled by the three test mode bits in the control register, TM0 to TM2 (see Table 5 below). TM2 TM1 TM0 FUNCTION 0 0 0 Normal Operation 0 0 1 Both inputs = REF-

010 I N + a t V ref/2, IN- at REF-

0 1 1 IN+ at REF+, IN- at REF- 1 0 0 Normal Operation 1 0 1 Both inputs = REF+ 1 1 0 IN+ at REF-, IN- at V ref/2 1 1 1 IN+ at REF-, IN- at REF+ Table 5 Test Modes

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001 10 100 1000 10000 Signal Frequency [kHz] at -1dB SNR [dB] Figure 10 Signal to Noise Ratio at 3MSPS 10 100 1000 10000 Signal Frequency [kHz] at -1dB SNR [dB] Figure 11 Signal to Noise Ratio at 8MSPS

APPLICATION INFORMATION

DRIVING THE ANALOGUE INPUT The WM2148 has a fully differential input. This is advantageous for signal to noise ratio, spurious free dynamic range, and harmonic distortion. It is recommended that the analogue input pins IN+ and IN- are connected as shown in Figure 12 below. DIFFERENTIAL ANALOGUE INPUT 100pF

22 Ohms

Figure 12 Recommended Input Configuration In this configuration, the ADC converts the difference /c168/c57 IN of the two input signals VIN+ and VIN/c237 . The resistors and capacitors on the inputs decouple the driving source output from the ADC and also serve as first order low pass filters to reduce out of band noise. The input range on both inputs is 0V to AV DD . The full-scale value is determined by the voltage reference. The positive full-scale output is reached when /c168/c57 IN equals /c168/c57 REF , and the negative full- scale output is reached when /c168/c57 IN equals -/c168/c57 REF . /c168/c57 IN OUTPUT -/c168/c57 REF - full scale /c168/c57 REF + full scale DIGITAL I/O The digital outputs of the WM2148 are 3V CMOS compatible. In order to avoid current feedback errors, the capacitive load on these outputs should be as low as possible (maximum 15pF). Adding 100Ω series resistors on the digital outputs cam improve system performance by limiting the current during output transitions (this reduces noise on the power supplies).

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001 RECOMMENDED EXTERNAL COMPONENTS C1 C2 C9C3 C4 C5 AGND AGND AGND AVDD AGND AVDD AGND AVDD AGND AGND OVI AVDD DVDD

48 IN+

45 AGND

D[0:13] A[0:1] OEB WRB CSB CONTROL BUS OUT OF RANGE INDICATOR DVDD DGND DVDD DGND DVDD DGND DVDD DGND DVDD DGND DVDD WM2148 AGND

4 CMLC16AGND

3 VBGC14 C15

6 REF-C19 C20AGND

5 REF+C17 C18

Figure 13 External Components Diagram

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001 COMPONENT REFERENCE SUGGESTED VALUE C1 10 µF Analogue Supply Decoupling C2 0.1 µF Supply Decoupling for Reference Block C3 470pF Supply Decoupling for Reference Block - place as close to the IC as possible C4 0.1 µF Supply Decoupling for ADC C5 470pF Supply Decoupling for ADC - place as close to the IC as possible C6 0.1 µF Supply Decoupling for ADC Op-amps C7 470pF Supply Decoupling for ADC Op-amps - place as close to the IC as possible (most critical for ADC performance) C8 10 µF Digital Supply Decoupling C9 0.1 µF Supply Decoupling Clock Buffers - place as close to the IC as possible to eliminate clock jitter C10 0.1 µF Supply Decoupling for Core Logic C11 0.1 µF Supply Decoupling for Control Block C12, C13 0.1 µF Supply Decoupling for Output Drivers C14, C17, C19 10 µF Reference Decoupling C15, C16, C18, C20 0.1 µf Reference Decoupling - place as close to the IC as possible Table 6 External Components Values and Description

WOLFSON MICROELECTRONICS LTD PD Rev 1.1 February 2001 PACKAGE DIMENSIONS NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = ABC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. DM004.CFT: 48 PIN TQFP (7 x 7 x 1.0 mm) Symbols Dimensions (mm) MIN NOM MAX A ----- ----- 1.20 A 2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 ----- 0.20 D 9.00 BSC D 1 7.00 BSC E 9.00 BSC E1 7.00 BSC e 0.50 BSC L 0.45 0.60 0.75 Θ 0o 3.5o 7o Tolerances of Form and Position ccc 0.08 REF: JEDEC.95, MS-026 2536 eb 121 D E1 E 2437 A A2 A1 SEATING PLANEccc C -C- Θ c L