WM2130

WM2130 WOLFSON | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 20

Technical content

10-bit 30MSPS Analogue-To-Digital Converter Production Data, April 2001, Rev 1.2 WOLFSON MICROELECTRONICS LTD Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk www.wolfsonmicro.com Production Data datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics’ Terms and Conditions.  2001 Wolfson Microelectronics Ltd.

DESCRIPTION

The WM2130 is a high speed 10-bit analogue-to-digital converter and operates with independent analogue and digital supplies of 3V to 5.5V. This device includes a high bandwidth sample and hold and internal voltage references. Conversion is controlled by a single clock input. The differential-input sample and hold input gives excellent common-mode noise immunity and low distortion. The device can also be driven in a single ended fashion. The device provides internal reference voltages for setting the ADC full-scale range without the requirement for external circuitry. The WM2130 can also accept external reference levels for applications where higher precision references are required. The WM2130 has also been designed to offer a speed upgrade to users of the AD876 and a replacement for the AD9200 and AD9202 devices. The WM2130 operates as an AD876 in those design slots but at speeds of up to 50% faster.

FEATURES

Wide input bandwidth (150 MHz full-power bandwidth) sample and hold input amplifier Independent analogue and digital supplies Adjustable internal voltage references Out of range indicator Low power: 87mW typical at 3V supplies Powerdown mode to 3mW typical 28-pin TSSOP package

APPLICATIONS

Set Top Box (STB) IF and Baseband Digitisation Medical Imaging High speed data acquisition BLOCK DIAGRAM WM2130 AIN PRECISION REFERENCE CIRCUITS SHA REFTS D[9:0] REFBF REFTF OVR REFBS OEB MODE REFSENSE POWER-DOWN CONTROL STBY AGND AVDD DGND DVDD M876B TIMING CONTROL CLK OUTPUT BUFFERS ADC

WOLFSON MICROELECTRONICS LTD PD Rev 1.2 April 2001 PIN CONFIGURATION

ORDERING INFORMATION

TEMP. RANGE PACKAGE WM2130CDT/V 0 to +70oC 28-pin TSSOP WM2130IDT/V -40 to +85oC 28-pin TSSOP DIO0 OVR OEB AGND DVDD REFTS REFBS REFBF REFTF MODE VREF AIN AVDD DIO8 REFSENSE DIO2 DIO3 DIO1 DIO7 AGND DIO6 DIO5 M876B DIO4 DIO9 DGND STBY CLK PIN DESCRIPTION PIN NAME TYPE Digital output bit 0 (lsb) DO1 Digital Output Digital output bit 1 DO2 Digital Output Digital output bit 2 DO3 Digital Output Digital output bit 3 DO4 Digital Output Digital output bit 4 DO5 Digital Output Digital output bit 5 DO6 Digital Output Digital output bit 6 DO7 Digital Output Digital output bit 7 DO8 Digital Output Digital output bit 8 DO9 Digital Output Digital output bit 9 (msb) OVR Digital Output Over-range output (tri-statable) DGND Ground Digital Ground CLK Digital Input Clock input STBY Digital Input Powerdown control OEB Digital Input Output enable bar – low to enable DO[9:0] and OVR REFSENSE Analogue Input/Output VREF mode control AGND Ground Negative Analogue Supply M876B Digital Input AD876 mode select REFTS Analogue Input Top reference sense REFTF Analogue Input/Output Top reference force MODE Digital Input Input mode select REFBF Analogue Input/Output Bottom reference force REFBS Analogue Input Bottom reference sense VREF Analogue Input/Output Internal reference output AIN Analogue Input Analog Input AVDD Supply Positive Analogue Supply

WOLFSON MICROELECTRONICS LTD PD Rev 1.2 April 2001 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. As per specifications IPC/JEDEC J-STD-020A and JEDEC A113-B, this product requires specific storage conditions prior to surface mount assembly. It has been classified as having a Moisture Sensitivity Level of 2 and as such will be supplied in vacuum-sealed moisture barrier bags. CONDITION MIN MAX Digital supply voltage, DVDD to DGND -0.3V +6.5V Analogue supply voltage, AVDD to AGND -0.3V +6.5V Supply voltage difference, AVDD to DVDD -6.5V +6.5V Ground difference, AGND to DGND -0.3V +0.3V Digital inputs voltage range (DO[9:0], STBY, OEB, M876B) DGND - 0.3V DVDD + 0.3V Voltage range analogue inputs (REFTS, REFBS, REFTF, REFBF, AIN, VREF, REFSENSE, CLK, MODE) AGND - 0.3V AVDD + 0.3V Storage temperature -65°C +150°C Soldering lead temperature, 1.6mm (1/16 inch) from package body for 10 seconds +300°C RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN NOM MAX UNIT Digital supply range DVDD 3.0 3.3 5.5 V Analogue supply range AVDD 3.0 3.3 5.5 V Clock frequency fCLK MHz Clock duty cycle WM2130C Operating Free Air Minimum Temperature TMIN WM2130I -40 WM2130C Operating Free Air Maximum Temperature TMAX WM2130I

WOLFSON MICROELECTRONICS LTD PD Rev 1.2 April 2001

ELECTRICAL CHARACTERISTICS

Test Conditions: AVDD = DVDD = 3.0V, fCLK = 30MHz, 50% Duty cycle, MODE = AVDD, REFTS = 2.5V, REFBS = 0.5V, TA = TMIN to TMAX, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DC Accuracy Integral nonlinearity INL ±1.0 ±2.0 LSB Differential nonlinearity DNL ±0.3 ±1.0 LSB Offset error 0.4 2.0 % of FS Gain error 1.4 3.5 % of FS Missing codes No missing codes guaranteed Analogue Input Signal to AIN pin MODE = AGND REFBS REFTS V MODE = AVDD / 2, VCMCS fixed VCMCS – VREF/2 VCMCS + VREF/2 V Input signal range MODE = AVDD REFBS REFTS V AIN voltage limits AGND AVDD V Switched input capacitance 1.2 pF Analogue input bandwidth 150 MHz DC leakage current ± Full-scale input ±60 µA Aperture delay tA ns Aperture jitter ps rms Conversion Characteristics Conversion frequency fCLK MHz Pipeline delay CLK cycles Aperture delay tA ns Aperture jitter ps rms Dynamic Performance fIN = 3.5MHz 8.4 fIN=3.5MHz, AVDD 5V fIN = 15MHz 7.8 Effective number of bits ENOB fIN=15MHz, AVDD 5V 7.7 dB fIN = 3.5MHz 60.6 fIN=3.5MHz, AVDD 5V 64.6 fIN = 15MHz 48.5 Spurious free dynamic range SFDR fIN=15MHz, AVDD 5V dB fIN = 3.5MHz -60 -56 fIN=3.5MHz, AVDD 5V -66.9 fIN = 15MHz -47.5 Total Harmonic Distortion THD fIN=15MHz, AVDD 5V -53.1 dB fIN = 3.5MHz fIN=3.5MHz, AVDD 5V fIN = 15MHz 53.1 Signal to noise ratio SNR fIN=15MHz, AVDD 5V 49.4 dB fIN = 3.5MHz 52.5 fIN=3.5MHz, AVDD 5V fIN = 15MHz 48.6 Signal to noise and distortion ratio SINAD fIN=15MHz, AVDD 5V 48.1 dB

WOLFSON MICROELECTRONICS LTD PD Rev 1.2 April 2001 Test Conditions: AVDD = DVDD = 3.0V, fCLK = 30MHz, 50% Duty cycle, MODE = AVDD, REFTS = 2.5V, REFBS = 0.5V, TA = TMIN to TMAX, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue Reference Inputs / Outputs in Top/Bottom Mode (MODE=AVDD) Bottom reference voltage applied to REFBS AVDD – 1 V Top reference voltage applied to REFTS AVDD V Differential reference input (REFTS – REFBS) VTB V Switched input capacitance on REFBS 0.6 pF Switched input capacitance on REFTS 0.6 pF REFBF output voltage (AVDD - VTB)/2 V REFTF output voltage (AVDD + VTB)/2 V Analogue Reference Inputs / Outputs in Centre-Span Mode (MODE=AVDD/2) Reference voltage derived or applied to VREF V REFBF output voltage (AVDD - VREF)/2 V REFTF output voltage (AVDD + VREF)/2 V Analogue Reference Inputs / Outputs in Full External Reference Mode (MODE=AGND) (Note 1) Differential reference voltage applied (REFTF – REFBF) V AVDD = 3.0V 1.3 1.5 1.7 V Reference input common mode (REFTF + REFBF) / 2 AVDD = 5.0V 2.0 2.5 3.0 V Reference input resistance 680 Ω VREF Input / Output specifications Internal 1V reference to VREF REFSENSE = VREF 0.95 1.0 1.05 V Internal 2V reference to VREF REFSENSE = AGND 1.9 2.0 2.1 V External reference applied to VREF pin in centre-span mode REFSENSE = AVDD, MODE = AVDD / 2 V Input impedance in centre-span mode REFSENSE = AVDD, MODE = AVDD / 2 kΩ Power Supplies AVDD = DVDD = 3V, MODE = AGND Operating supply current IAVDD + IDVDD AVDD = DVDD = 5V mA Standby Power PSTBY AVDD = DVDD = 3V, MODE = AGND mW Digital Logic Levels (CMOS Levels) Input LOW level VIL (Note 2) 0.2 x VDD V Input HIGH level VIH (Note 2) 0.8 x VDD V Notes In full external reference mode the REFTF and REFTS pins should be shorted together, and the REFBF and REFBS pins should be shorted together. Please refer to device operation examples in the device description section of the datasheet. Digital input and output levels refer to the supply used for the input/output buffer on the relevant pin. MODE refers to the AVDD supply, all other digital input/output refers to the DVDD supply.

WOLFSON MICROELECTRONICS LTD PD Rev 1.2 April 2001 Sample 1 Sample 5 Sample 4 Sample 3 Sample 2 tCLK tCL tCH Digital Output tD Pipeline Delay Sample 1 Sample 2 Note: All timing measurements are based on 50% of edge transition CLK Analogue Input at AIN Figure 1 Output Timing Test Conditions: AVDD = DVDD = 3.0V, fCLK = 30MHz, 50% duty cycle, MODE = AVDD, REFTS = 2.5V, REFBS = 0.5V, TA = TMIN to TMAX, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Clock Clock period tCLK ns Clock high time tCH 16.5 ns Clock low time tCL 16.5 ns Timing Pipeline delay CLK cycles Clock to data valid tD ns Output disable to hi-Z output tDZ ns Output enable to data valid tDEN ns

WOLFSON MICROELECTRONICS LTD PD Rev 1.2 April 2001 ANALOGUE-TO-DIGITAL CONVERTER Regardless of the reference configuration, VQ is digitised against ADC Reference Voltages REFTF and REFBF, full scale values of VQ being given by: REFBF REFTF VQFS and REFBF REFTF VQFS Attempts to convert VQ voltages outside the range of VQFS- to VQFS+ are signalled to the application by driving the OVR output pin high. If VQ is less than VQFS-, the ADC output code is 0. If VQ is greater than VQFS+, the output code is 1023. SIGNAL CHAIN SUMMARY Combining the above equations and referring back to the input, the positive and negative full-scale voltages at the AIN pin are: REFBF REFTF V V M INFS and REFBF REFTF V V M INFS Therefore the input signal span is given by: REFBF REFTF V V INFS INFS In order to match the ADC input range to the input signal amplitude, REFTF and REFBF should be set such that: + − INFS INFS V V REFBF REFTF ADC REFERENCE MODES The WM2130 supports three basic modes of reference generation, selected by the voltage applied to the MODE pin. These are summarised and explained in Table 1. In differential, Centre Span and Top/Bottom modes, the internally generated ADC references are intened solely for WM2130 internal use and REFTF and REFBF must not be used as voltage references for any other device in the application. MODE PIN MODE FUNCTION COMMENTS AGND Full external REFTS REFTF = REFBS REFBF = On-chip reference generator and reference buffer are not used. AVDD/2 Differential REF V AVDD REFTF REF V AVDD REFTF VREF can be internally or externally generated. REFTS and REFBS are joined together and connected either to the negative end of the input signal (true differential mode) or to the AIN mid-scale voltage (centre-span mode). AVDD Top/Bottom REFBS REFTS AVDD REFTF REFBS REFTS AVDD REFBF On-chip reference generator is not used. Reference buffer centers external reference voltages around AVDD/2. Table 1 WM2130 Reference Generation Modes

WOLFSON MICROELECTRONICS LTD PD Rev 1.2 April 2001 ON-CHIP REFERENCE VOLTAGE GENERATOR The On-chip Reference Generator (ORG) can provide a reference voltage on the VREF pin that is independent of temperature and supply voltage. External connections to the REFSENSE pin control the ORG’s output to VREF, as shown in Figure 14. REFSENSE CONNECTION ORG OUTPUT TO VREF VREF pin

1 Volt

2 Volts

(1 + RA/RB) Volts – see Figure 14 AVDD None (VREF becomes input pin) Table 2 Controlling the On-chip Reference Generator Connecting REFSENSE to AVDD powers the ORG down, saving power when the ORG function is not required. In differential mode (MODE = AVDD/2), the voltage on VREF determines the ADC reference voltages as follows: REF V AVDD REFTF REF V AVDD REFBF REF V REFBF REFTF When the ORG is enabled, the VREF pin should be decoupled to the circuit board’s analogue ground plane close to the WM2130 AGND pin via a 1µF tantalum capacitor and a 0.1µF ceramic capacitor. The ORG can source currents up to 1mA into external grounded loads when it is not used by the WM2130. Typical buffer load regulation is about 0.5Ω. INTERNAL REFERENCE BUFFER 1µF tantalum 0.1µF VREF = 1 + (RA/RB) REFSENSE AGND VBG RB RA MODE = AVDD/2 Figure 14 ORG Operating with External Divider (for Intermediate Reference Voltages)

WOLFSON MICROELECTRONICS LTD PD Rev 1.2 April 2001 POWER MANAGEMENT In power-sensitive applications (such as battery-powered systems) where the WM2130 ADC is not required to convert continuously, power can be saved between conversion intervals by placing the WM2130 into Power Down mode. This is achieved by pulling the Standby Mode Pin (STBY, pin 16) HIGH. In Power Down mode, the device typically consumes less than 3mW of power. Power down mode is exited by resetting control register bit 3 to 0. On power up from long periods of power down, the WM2130 typically requires 5ms of wake up time before valid conversion results are available. When REFSENSE is tied to AVDD, the reference generator is disabled and supply current reduced by approximately 1.2mA. DIGITAL OUTPUT FORMAT While the OEB pin is held low, ADC conversion results are output at the data output pins DO0 (LSB) to DO9 (MSB). The output data format is unsigned binary (output codes 0 to 1023). AD876 COMPATIBILITY MODE Pulling M876B (pin 20) low puts the WM2130 into AD876 compatibility mode. In this mode the device latency increases to 3.5 clock cycles and the OVR pin is tri-stated to avoid conflict with the DRGND connection present at pin 13 in AD876 slots. For best dynamic performance, use a 3 cycle latency operating mode if possible.

WOLFSON MICROELECTRONICS LTD PD Rev 1.2 April 2001 DIGITAL OUTPUT LOADING AND CIRCUIT BOARD LAYOUT The WM2130 outputs are capable of driving rail-to-rail with up to 20pF of load per pin at 30MHz clock and 3V digital supply. Minimising the load on the outputs will improve WM2130 signal-to-noise performance by reducing the switching noise coupling from the WM2130 output buffers to the internal analogue circuits. The output load capacitance can be minimised by buffering the WM2130 digital outputs with a low input capacitance buffer placed as close to the output pins as physically possible, and by using the shortest possible tracks between the WM2130 and this buffer. Noise levels at the output buffers, which may affect the analogue circuits within WM2130, increase with the digital supply voltage. Where possible, consider using the lowest DVDD that the application can tolerate. Use good layout practices when designing the application PCB to ensure that any off-chip return currents from the WM2130 digital outputs (and any other digital circuits on the PCB) do not return via the supplies to any sensitive analogue circuits. The WM2130 should be soldered directly to the PCB for best performance. Socketing the device will degrade performance by adding parasitic socket inductance and capacitance to all pins. USER TIPS FOR OBTAINING BEST PERFORMANCE FROM THE WM2130 Choose differential input mode for best distortion performance. Choose a 2V ADC input span for best noise performance. Choose a 1V ADC input span for best distortion performance. Drive the clock input CLK from a low-jitter, fast logic stage, with a well-decoupled power supply and short PCB traces.

WOLFSON MICROELECTRONICS LTD PD Rev 1.2 April 2001 PACKAGE DIMENSIONS NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. DM022.A DT: 28 PIN TSSOP (9.7 x 4.4 x 1.0 mm) Symbols Dimensions (mm) MIN NOM MAX A ----- ----- 1.20 0.05 ----- 0.15 0.80 1.00 1.05 b 0.19 ----- 0.30 c 0.09 ----- 0.20 D 9.60 9.70 9.80 e

0.65 BSC

E

6.4 BSC

4.30 4.40 4.50 L 0.45 0.60 0.75 θ o ----- o REF: JEDEC.95, MO-153 θ c L GAUGE PLANE 0.25 E e b D SEATING PLANE A -C- 0.1 C