WM1824 WOLFSON | Alldatasheet
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w WM1824 24-bit 192kHz Stereo DAC with 2Vrms Ground Referenced Line Output WOLFSON MICROELECTRONICS plc Production Data, December 2011, Rev 4.1 Copyright 2011 Wolfson Microelectronics plc
DESCRIPTION
The WM1824 is a stereo DAC with integral charge pump. This provides 2Vrms line driv er outputs using a single 3.3V power supply rail. The device features ground-referenced outputs and the use of a DC servo to eliminate t he need for line driving coupling capacitors and effectively eliminate power on pops and clicks. The device is controlled and configured via a hardware control interface. The device supports all common audio sampling rates between 8kHz and 192kHz using all common MCLK fs rates. The audio interface operates in slave mode. The WM1824 has a 3.3V tolerant digital interface, allowing logic up to 3.3V to be connected. The device is available in a 24-pin QFN.
FEATURES
High performance stereo DAC with ground referenced line driver Audio Performance 106dB SNR (‘A-weighted’) -89dB THD @ -1dBFS 120dB mute attenuation All common sample rates from 8kHz to 192kHz supported Hardware control mode Data formats: LJ, I S Maximum 1mV DC offset on Line Outputs Pop/Click suppressed Power Up/Down Sequencer AVDD, LINEVDD and DBVDD can operate at +3.3V ±10% allowing single supply 24-lead QFN package Operating temperature range: -40°C to 85°C
APPLICATIONS
Consumer digital audio applic ations requiring 2Vrms output Games Consoles Set Top Box A/V Receivers DVD Players Digital TV BLOCK DIAGRAM
w PD, Rev 4.1, December 2011 TABLE OF CONTENTS
w PD, Rev 4.1, December 2011 PIN CONFIGURATION NC NC LINEVDD NC NC CPCA 1 18 LINEGND CPCB CPVOUTN DBVDD MCLK BCLK DACDAT LRCLK NC AIFMODE NC MUTE VMID
17 AVDD
16 AGND
15 LINEVOUTL
13 LINEVOUTR
24-LEAD QFN (TOP VIEW)
ORDERING INFORMATION
WM1824CGEFL/V −40°C to +85°C 24-lead QFN (pb-free) MSL3 260 o C WM1824CGEFL/RV −40°C to +85°C 24-lead QFN (pb-free, tape and reel) MSL3 260 o C Note: Reel quantity = 3,500
w PD, Rev 4.1, December 2011 PIN DESCRIPTION PIN NO NAME TYPE DESCRIPTION
1 BCLK Digital In Digital audio interface bit clock
2 MCLK Digital In Master clock
3 DBVDD Supply Digital Buffer Supply
6 LINEVDD Supply Charge Pump supply
9 CPCA Analogue Out Charge Pump fly back capacitor pin
10 LINEGND Supply Charge Pump ground
11 CPCB Analogue Out Charge Pump fly back capacitor pin
12 CPVOUTN Analogue Out Charge Pump negative rail decoupling pin
13 LINEVOUTR Analogue Out Right line output
15 LINEVOUTL Analogue Out Left line output
16 AGND Supply Analogue ground
17 AVDD Supply Analogue supply
18 VMID Analogue Out Analogue midrail decoupling pin
19 MUTE ¯¯¯¯¯ Digital In 0 = Mute enabled
1 = Mute disabled 20 NC 21 NC
22 AIFMODE Digital In 1 = 24-bit Left Justified
0 = 24-bit I S
23 LRCLK Digital In Digital audio interface left/right clock
24 DACDAT Digital In Digital audio interface data input
w PD, Rev 4.1, December 2011 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactur ed on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD- 020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION MIN MAX AVDD, LINEVDD, DBVDD -0.3V +4.5V Voltage range digital inputs LINEGND -0.3V LINEVDD +0.3V Voltage range analogue inputs AGND -0.3V AVDD +0.3V Temperature range, TA -40°C +125°C Storage temperature after soldering -65°C +150°C Notes 1. Analogue grounds must always be within 0.3V of each other. 2. LINEVDD and AVDD must always be within 0.3V of each other. RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue supply range AVDD, LINEVDD 2.97 3.3 3.63 V Ground AGND, LINEGND 0 V Digital Buffer supply range DBVDD 1.62 3.63 V
w PD, Rev 4.1, December 2011
ELECTRICAL CHARACTERISTICS
LINEVDD=AVDD=DBVDD=3.3V, LINEGND=AGND=0V, TA=+25 C, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Analogue Output Levels Output Level 0dBFS 2.04 2.1×AVDD
2.14 Vrms
A k Ω Load Capacitance No external RC filter 300 pF With filter shown in Figure 15 1 µF DAC Performance Signal to Noise Ratio SNR RL = 10kΩ A-weighted 106 dB RL = 10kΩ Un-weighted 104 dB Dynamic Range DNR RL = 10kΩ A-weighted 104 dB Total Harmonic Distortion THD -1dBFS -89 dB 0dBFS -86 dB AVDD + LINEVDD Power Supply Rejection Ratio PSRR 100Hz 54 dB 1kHz 54 dB 20kHz 50 dB Channel Separation 1kHz 100 dB 20Hz to 20kHz 95 dB System Absolute Phase 0 degrees Channel Level Matching 0.1 dB Mute Attenuation -120 dB DC Offset at LINEVOUTL and LINEVOUTR -1 0 1 mV Digital Logic Levels Input HIGH Level VIH 0.7 LINEVDD V Input LOW Level VIL 0.3 LINEVDD V Input Capacitance 10 pF Input Leakage -0.9 0.9 A Note: 1. To prevent over-current protecti on shutdown of the device, ensure that the load impedance is never less than 100Ω. If a load impedance of less than 100Ω is presented to either LINEVOUTL or LINEVOUTR, the device may go into a protective shutdown state where the charge pump will stop running and the device will shut down. It will take a hardware reset to come out of this state (recycle the power supplies or hold /MUTE low for 1024 LRCLK cycles after the low impedance load condition has been removed). TERMINOLOGY 1. Signal-to-Noise Ratio (dB) – SNR is a measure of the difference in level bet ween the maximum theoretical full scale output signal and the output with no input signal applied. 2. Total Harmonic Distortion (dB) – THD is the level of the rm s value of the sum of harmonic distortion products relative to the amplitude of the measured output signal. 3. All performance measurements carried out with 20kHz low pa ss filter, and where noted an A-weighted filter. Failure to use such a filter will result in higher THD and lower SNR readi ngs than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 4. Mute Attenuation – This is a measur e of the difference in level between the full scale output signal and the output with mute applied.
w PD, Rev 4.1, December 2011 POWER CONSUMPTION MEASUREMENTS Test Conditions LINEVDD=AVDD=DBVDD=3.3V, LINEGND=AGND=0V, TA=+25°C, quiescent (no signal) TEST CONDITIONS IAVDD (mA) ILINEVDD (mA) DBVDD (mA) TOTAL (mA) Off No clocks applied 0.8 1.0 0.0 1.8 fs=48kHz, MCLK=256fs Standby MUTE ¯¯¯¯¯ = 0 0.2 2.1 0.02 2.32 Playback MUTE ¯¯¯¯¯ = 1 4.7 6.0 0.02 10.72 fs=96kHz, MCLK=256fs Standby MUTE ¯¯¯¯¯ = 0 0.2 2.7 0.03 2.93 Playback MUTE ¯¯¯¯¯ = 1 5.2 8.5 0.03 13.73 fs=192kHz, MCLK=128fs Standby MUTE ¯¯¯¯¯ = 0 0.2 2.7 0.04 2.94 Playback MUTE ¯¯¯¯¯ = 1 5.2 8.4 0.04 13.64
w PD, Rev 4.1, December 2011 SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING Figure 1 System Clock Timing Requirements Test Conditions LINEVDD=AVDD=DBVDD=2.97~3.63V, LINEGND=AGND=0V, TA=+25°C PARAMETER SYMBOL MIN TYP MAX UNIT Master Clock Timing Information MCLK cycle time tMCLKY 27 500 ns MCLK high time tMCLKH 11 ns MCLK low time tMCLKL 11 ns MCLK duty cycle (tMCLKH/tMCLKL) 40:60 60:40 %
w PD, Rev 4.1, December 2011 AUDIO INTERFACE TIMING – SLAVE MODE Figure 2 Digital Audio Data Timing – Slave Mode Test Conditions LINEVDD=AVDD=DBVDD=2.97~3.63V, LINEGND=AGND=0V, TA=+25 C, Slave Mode PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 27 ns BCLK pulse width high tBCH 11 ns BCLK pulse width low tBCL 11 ns LRCLK set-up time to BCLK rising edge tLRSU 7 ns LRCLK hold time from BCLK rising edge tLRH 5 ns DACDAT hold time from LRCLK rising edge tDH 5 ns DACDAT set-up time to BCLK rising edge tDS 7 ns Table 1 Slave Mode Audio Interface Timing Note: BCLK period should always be greater than or equal to MCLK period.
w PD, Rev 4.1, December 2011 On power down, PORB is asserted low whenever LINEVDD or AVDD drop below the minimum threshold Vpora_low. Test Conditions LINEVDD = AVDD = DBVDD = 3.3V AGND = LINEGND = 0V, TA = +25 o C PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Power Supply Input Timing Information VDD level to POR defined (LINEVDD/AVDD rising) Vpora Measured from LINEGND 158 mV VDD level to POR rising edge (VMID rising) Vpord_hi Measured from LINEGND 0.63 0.8 1 V VDD level to POR rising edge (LINEVDD/AVDD rising) Vpora_hi Measured from LINEGND 1.44 1.8 2.18 V VDD level to POR falling edge (LINEVDD/AVDD falling) Vpora_lo Measured from LINEGND 0.96 1.46 1.97 V Table 2 Power on Reset Note: All values are simulated results
w PD, Rev 4.1, December 2011 DEVICE DESCRIPTION INTRODUCTION The WM1824 provides high fidelity, 2V rms ground referenced stereo line output from a single supply line with minimal external components. The integrated DC servo eliminates the requirement for external mute circuitry by minimising DC transients at the output during power up/down. The device is well-suited to both stereo and multi-channel systems. The device supports all common audio samp ling rates between 8kHz and 192kHz using common MCLK fs rates, with a slave mode audio interface. The WM1824 supports a simple hardware contro l mode, allowing access to 24-bit LJ and I S audio interface formats, as well as a mute contro l. An internal audio interface clock monitor automatically mutes the DAC output if the BCLK is interrupted. DIGITAL AUDIO INTERFACE The digital audio interface is used for inputti ng audio data to the WM1824. The digital audio interface uses three pins: DACDAT: DAC data input LRCLK: Left/Right data alignment clock BCLK: Bit clock, for synchronisation The WM1824 digital audio interface operates as a slave as shown in Figure 5. Figure 5 Slave Mode INTERFACE FORMATS The WM1824 supports two different audio data formats: Left justified I S Both of these modes are MSB first. They ar e described in Audio Data Formats on page 13. Refer to the “Electrical Characteristics” section for timing information.
w PD, Rev 4.1, December 2011 The DAC supports MCLK to LRCLK ratios of 128fs to 1152fs and sampling rates of 8kHz to 192kHz. Table 3 shows typical master clock fr equencies and sampling rates supported by the WM1824 DAC. Sampling Rate LRCLK MASTER CLOCK FREQUENCY (MHz) 128fs 192fs 256fs 384fs 512fs 768fs 1152fs 48kHz Unavailable Unavailable 12.288 18.432 24.576 36.864 Unavailable 96kHz 12.288 18.432 24.576 36.864 Unavailabl e Unavailable Unavailable 176.4kHz 22.5792 33.8688 Unavailable Unavailable U navailable Unavailable Unavailable 192kHz 24.576 36.864 Unavailable Unavailable U navailable Unavailable Unavailable Table 3 MCLK Frequencies and Audio Sample RatesHardware Control Interface The device is configured according to logic le vels applied to the hardware control pins as described in Table 4. PIN NAME PIN NUMBER MUTE¯¯¯¯¯ 19 Mute Control 0 = Mute 1 = Normal operation AIFMODE 22 Audio Interface Mode 1 = 24-bit LJ 0 = 24-bit I S Table 4 Hardware Control Pin Configuration MUTE The MUTE¯¯¯¯¯ pin controls the DAC mute to both left and right channels. When the mute is asserted a softmute is applied to ramp the signal down in 800 samples. When the mute is de-asserted the signal returns to full scale in one step.
w PD, Rev 4.1, December 2011 POWER UP AND DOWN CONTROL The MCLK, BCLK and MUTE¯¯¯¯¯ pins are monitored to cont rol how the device powers up or down, and this is summarised in Figure 8 below. Off Standby Enabled BCLK Enabled MUTE=1 MUTE=0 BCLK Disabled MCLK Disabled MCLK Enabled BCLK Enabled MUTE=0 MCLK Enabled BCLK Enabled MUTE=1 MCLK Disabled Figure 8 Hardware Power Sequence Diagram Off to Enable To power up the device to enabled, start MCLK and BCLK and set MUTE¯¯¯¯¯ = 1. Off to Standby To power up the device to standby, start MCLK and BCLK and set MUTE¯¯¯¯¯ = 0. Once the device is in standby mode, BCLK can be di sabled and the device will remain in standby mode. Standby to Enable To transition from the standby state to the enabled state, set the MUTE¯¯¯¯¯ pin to logic 1 and start BCLK. Enable to Standby To power down to a standby state leaving the charge pump running, either set the MUTE¯¯¯¯¯ pin to logic 0 or stop BCLK. MCLK must cont inue to run in these situations. The device will automatically mute and power down quietly in either case. Note: It is recommended that the device is placed in standby mode before sample rate change if the sample rate changes more than once in 1026 LRCLK periods, as detailed in Digital Audio Data Sampling Rates on page 13. Enable to Off To power down the device completely, stop MCLK at any time. It is recommended that the device is placed into standby mode as described above before stopping MCLK to allow a quiet shutdown. For the timing of the off state to enabled stat e transition (power on to audio out timing), and the enabled state to standby state transiti on (the shutdown timing), please refer to WTN0302.
w PD, Rev 4.1, December 2011 POWER DOMAINS Figure 9 Power Domain Diagram Power Domain Name Blocks Using This Domain Domain Description DAC Power Supplies 3.3V ± 10% AVDD Line Driver DAC DC Servo Analogue Supply 3.3V ± 10% LINEVDD Charge Pump Digital LDO Digital Pad buffers Analogue Supply 1.8V – 3.3V ± 10% DBVDD Digital Input Pins Digital Buffer Supply Internally Generated Power Supplies and References 1.65V ± 10% VMID DAC, LDO Ext decoupled resistor string -3.3V ± 10% CPVOUTN Line Driver Charge pump generated voltage Table 5 Power Domains
w PD, Rev 4.1, December 2011 DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC Filter – 256fs to 1152fs Passband 0.1dB 0.454fs Passband Ripple 0.1 dB Stopband 0.546fs Stopband attenuation f > 0.546fs -50 dB Group Delay 10 Fs DAC Filter – 128fs and 192fs Passband 0.1dB 0.247fs Passband Ripple 0.1 dB Stopband 0.753fs Stopband attenuation f > 0.753fs -50 dB Group Delay 10 Fs TERMINOLOGY 1. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated 2. Pass-band Ripple – any variation of t he frequency response in the pass-band region
w PD, Rev 4.1, December 2011 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS MCLK BCLK LRCLK DACDAT DACDAT LRCLK BCLK MCLK MUTE MUTE AIFMODEAIFMODE AVDD LINEVDD CPVOUTN LINEVOUTR LINEVOUTL CPCA CPCB LINEVDD LINEGND AGND VMID C1 C2 C3 C4 * AVDD 1uF 4.7uF 4.7uF 2.2uF 1uF WM1824 DBVDD 4.7uF3 2.2uF * Alternative VMID decoupling to AVDD Figure 14 Recommended External Components Notes: 1. Wolfson recommend using a single, common ground plane. Where this is not possible, care should be taken to optimise split ground configuration for audio performance. 2. Charge Pump fly-back capacitor C5 should be placed as close to WM1824 as possible, followed by Charge Pump decoupling capacitor C1, then LINEVDD and VMID decoupling capacitors. 3. Capacitor types should be chosen carefully. Capac itors with very low ESR are recommended for optimum performance.
w PD, Rev 4.1, December 2011 RECOMMENDED ANALOGUE LOW PASS FILTER LINEVOUT 2.7nF 560Ω Figure 15 Recommended Analogue Low Pass Filter (one channel shown) An external single-pole RC filter is recommended if the device is driving a wideband amplifier. Other filter architectures may provide equally good results. The filter shown in Figure 15 has a -3dB cut-off at 105.26kHz and a droop of 0.15dB at 20kHz. The typical output from the WM1824 is 2.1Vrms – when a 10k Ω load is placed at the output of this recommended filter the amplitude across this load is 1.99Vrms. RELEVANT APPLICATION NOTES The following application notes may provide additional guidance for use of the WM1824. DEVICE PERFORMANCE: WAN0129 – Decoupling and Layout Methodology for Wolfson DACs, ADCs and CODECs WAN0144 – Using Wolfson Audio DACs and CODECs with Noisy Supplies GENERAL: WAN0108 – Moisture Sensitivity Classification and Plastic IC Packaging WAN0109 – ESD Damage in Integrated Circuits: Causes and Prevention WAN0158 – Lead-Free Solder Profiles for Lead-Free Components WAN0161 – Electronic End-Product Design for ESD If you require more information or require technical support, pleas e contact the nearest Wolfson Microelectronics regional office: http://www.wolfsonmicro.com/contact or one of our global distributors: http://www.wolfsonmicro.com/distribution
w PD, Rev 4.1, December 2011 PACKAGE DIMENSIONS FL: 24 PIN QFN PLASTIC PACKAGE 4 X 4 X 0.75 mm BODY, 0.50 mm LEAD PITCH INDEX AREA (D/2 X E/2) TOP VIEW D E NOTES: 1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.2 mm AND 0.30 mm FROM TERMINAL TIP. 2. FALLS WITHIN JEDEC, MO-220. 3. ALL DIMENSIONS ARE IN MILLIMETRES. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JEDEC 95-1 SPP-002. 5. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 6. REFER TO APPLICATIONS NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING . 7. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. A b7 1 BCbbb M A BOTTOM VIEW Caaa2 X Caaa2 X C SEATING PLANE DETAIL 1 C0.08 Cccc A SIDE VIEW EXPOSED GROUND PADDLE DETAIL 1 Symbols MIN NOM MAX NOTE A 0.70 0.75 0.80 0.050.350
0.203 REF
b D E e L 0.300.20
4.00 BSC
2.62.502.4
0.50 BSC
0.35 0.40 0.45 2.62.502.4 0.1 aaa bbb ccc REF: 0.1 0.1 JEDEC, MO-220 Tolerances of Form and Position 0.25 0.65G G b Exposed lead DM070.A L e
w PD, Rev 4.1, December 2011 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and s pecifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer app lications, the customer must use adequate design and operating safeguards to minimise inherent or proc edural hazards. Wolfson is not liable fo r applications assistance or customer product design. The customer is solely responsible for its se lection and use of Wolfson products . Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to re sult in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or pr ocess in which its products or services might be or are used. Any prov ision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is per missible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other not ices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties giv en, and/or liabilities accepted by any pers on which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS Wolfson Microelectronics plc Westfield House
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Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
w PD, Rev 4.1, December 2011
REVISION HISTORY
DATE REV ORIGINATOR CHANGES PAGE 24/03/10 3.1/ 4.0 BT Removed MCLK Jitter Spec in System Clock Timing table, page 8 BT Removed maximum line load from electrical characteristics BT Updated power state diagram to show all transitions, page 15 BT Added note in Power up and down control section to recommend putting the device in standby mode if more than 1 sample rate change occurs in 1026 LRCLK cycles, page 15 BT Added reference to WTN0302 in Power up and down control section, page 15 BT Added paragraph in Digital Audio Data Sampling Rates section to recommend putting the device in standby or off mode if more than 1 sample rate change occurs in 1026 LRCLK cycles, page 13 BT Changed RC value of recommended output filter 20 BT Added 100Ω minimum load impedance to prevent over-current shutdown note to electrical characteristics table 6 24/11/10 4.0 JMacD Updated to Production Data status 05/12/12 4.1 JMacD Order codes changed from WM1824GEFL/R and WM1824GEFL/RV to WM1824CGEFL/R and WM1824CGEFL/RV to reflect change to copper wire bonding. 15/12/12 4.1 JMacD Relevant Application Note section updated 20
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