WM0834 WOLFSON | Alldatasheet
Document overview
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- PDF pages: 16
Technical content
Features
- Functionally Equivalent to National Semiconduc- tor ADC0834 and ADC0838 without the Internal Zener Regulator Network
- 4-input (WM0834) or 8-input (WM0838) MUX options
- Reference input operates ratiometrically or with a fixed reference
- Input range 0 to Vcc with Vcc Reference
- 5V and 3.3V variants
- Total Unadjusted Error: ± 1 LSB
- 8-bit resolution
- Low Power
- 32 µµµµµs conversion time at fclock = 250 kHz
- Serial I/O interface
- WM0834 packages: 14 pin SO & DIP WM0838 packages: 20 pin wide-body SO & DIP
Applications
- Embedding with remote sensors
- Equipment health monitoring
- Automotive
- Industrial control CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM AGND VREF DI CLK CS Notes: 1. Internally tied to AGND for WM0834 2. Not available on WM0834 WM0834
4 Inputs
8 Inputs
WM0834, WM0838 Ordering InformationPin Configuration Top View WM0834 : N(DIP) and D (SO) packages WM0838: N(DIP) and DW (SO) packages DEVICE TEMP . RANGE PACKAGE WM0834CN 0 oC to 70oC 14 pin plastic DIP WM0834CD 0 oC to 70oC 14 pin plastic SO WM0834IN -40 oC to 85oC 14 pin plastic DIP WM0834ID -40 oC to 85oC 14 pin plastic SO WM0838CN 0 oC to 70oC 20 pin plastic DIP WM0838CDW 0 oC to 70oC 20 pin plastic SO WM0838IN -40 oC to 85oC 20 pin plastic DIP WM0838IDW -40 oC to 85oC 20 pin plastic SOWM0834 WM0838 Absolute Maximum Ratings (note 1) Input voltage range: Operating temperature range, TA . . . . TMIN to TMAX oC to +70oC Soldering Information: Lead Temperature 1.6 mm (1/16) from case oC Recommended Operating Conditions (5V) SYMBOL MIN NOMINAL MAX UNIT Supply voltage V CC 4.5 5 5.5 V High level input voltage V IH 2V Low level input voltage V IL 0.8 V Clock frequency f clock 10 600 KHz Clock duty cycle (see Note 4) D clk 40 60 % Pulse duration CS high t wH(CS) 220 ns Operating free-air temperature C suffix T A 07 0 oC I Suffix T A -40 85 DEVICE TEMP. RANGE P ACKAGE WM0834LCN 0 oC to 70oC 14 pin plastic DIP WM0834LCD 0 oC to 70oC 14 pin plastic SO WM0834LIN -40 oC to 85oC 14 pin plastic DIP WM0834LID -40 oC to 85oC 14 pin plastic SO WM0838LCN 0 oC to 70oC 20 pin plastic DIP WM0838LCDW 0 oC to 70oC 20 pin plastic SO WM0838LIN -40 oC to 85oC 20 pin plastic DIP WM0838LIDW -40 oC to 85oC 20 pin plastic SO 5V devices 3.3V devices
WM0834, WM0838 Electrical Characteristics (5V) VCC = 5.0V, VREF = 5V, fCLK = 250 KHz, TA = TMIN to TMAX , tr = tf = 20ns, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Inputs High level output voltage VOH VCC = 4.75 V, IOH = -360 mA 2.4 V VCC = 4.75 V, IOH = -10 mA 4.5 V Low level output voltage VOL VCC = 5.25 V, IOH = 1.6 mA 0.4 V High level input current IIH VIH = 5 V 0.005 1 µ A Low level input current I IL VIL = 0 V -0.005 -1 µA High level output (source) IOH VOH = 0 V -6.5 -24 mA current Low level output (sink) current I OL VOL = VCC 82 6 m A High impedance-state I OZ VO = 5 V 0.01 3 µ A output current (DO) V O = 0 V -0.01 -3 µ A Input capacitance C i 5p F Output capacitance C o 5p F Converter and Multiplexer Total unadjusted error TUE V REF = 5 V. (note 7) ±1 LSB Differential Linearity (note 8) 8 Bits Supply voltage variation error Vs(error) VCC = 4.75 V to 5.25 V ±1/16 ±1/4 LSB Common mode error Differential mode ±1/16 ±1/4 LSB Common mode input voltage VICR (note 9) GND-0.05 V range V CC +0.05 Standby input leakage I I(stdby) On-channel VI = 5 V at ON ch. 1 µA current (note 10) Off-channel VI = 0 V at OFF ch. -1 µA On-channel VI = 0 V at ON ch. -1 µA Off-channel VI = 5 V at OFF ch. 1 µA Conversion time tconv Excluding MUX addressing time 8 clock periods Reference Inputs Input resistance to R i(REF) 1.3 2.4 5.9 k Ω reference ladder Total device Supply current I CC 0.6 1.25 mA Timing Parameters Setup time, CS low or t su 350 ns data valid before clock Hold time, data valid after th 90 ns clock Propagation delay time, MSB data first. C L = 100 pF 1500 ns output data after clock tpd LSB data first. CL = 100 pF 600 ns Output disable time, DO t dis C L = 10 pF , RL = 10 kΩ 125 250 ns after CS CL = 100 pF, RL = 2 kΩ 500 ns
WM0834, WM0838 Recommended Operating Conditions (3.3V) SYMBOL MIN NOMINAL MAX UNIT Supply voltage V CC 2.7 3.3 3.6 V High level input voltage V IH 2V Low level input voltage V IL 0.8 V Clock frequency (Vcc = 3.3V) f clock 10 600 KHz Clock duty cycle (see Note 4) D clk 40 60 % Pulse duration CS high t wH(CS) 220 ns Operating free-air temperature C suffix T A 07 0 oC I Suffix T A -40 85
WM0834, WM0838 Electrical Characteristics (3.3V) VCC = 3.3V, fCLK = 250 KHz, TA = TMIN to TMAX , tr = tf = 20ns, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Digital Inputs High level output voltage VOH VCC = 3.0 V, IOH = -360 mA 2.4 V VCC = 3.0V, IOH = -10 mA 2.8 V Low level output voltage VOL VCC =3.0V, IOH = 1.6 mA 0.4 V High level input current IIH VIH = 3.6V 0.005 1 µ A Low level input current I IL VIL = 0 V -0.005 -1 µA High level output (source) IOH VOH = 0 V, TA = 25oC6 . 5 1 5 m A current Low level output (sink) current I OL VOL = VCC , TA = 25oC8 1 6 m A High impedance-state I OZ VO = 3.3 V, TA = 25oC 0.01 3 µ A output current (DO) V O = 0 V, TA = 25oC -0.01 -3 µ A Input capacitance C i 5p F Output capacitance C o 5p F Converter and Multiplexer Total unadjusted error TUE V REF = 3.3 V. (note 7) ±1 LSB Differential Linearity (note 8) 8 Bits Supply voltage variation error Vs(error) VCC = 3.0 V to 3.6 V ±1/16 ±1/4 LSB Common mode error Differential mode ±1/16 ±1/4 LSB Common mode input voltage VICR (note 9) GND-0.05 V range V CC +0.05 Standby input leakage I I(stdby) On-channel VI =3.3 V at ON ch. 1 µA current (note 10) Off-channel VI = 0 V at OFF ch. -1 µA On-channel VI = 0 V at ON ch. -1 µA Off-channel VI =3.3V at OFF ch 1 µA Conversion time tconv Excluding MUX addressing time 8 clock periods Reference Inputs Input resistance to R i(REF) 1.3 2.4 5.9 k Ω reference ladder Total device Supply current I CC 0.2 0.75 mA Timing Parameters Setup time, CS low or t su 350 ns data valid before clock Hold time, data valid after th 90 ns clock Propagation delay time, MSB data first. C L = 100 pF 500 ns output data after clock tpd LSB data first. CL = 100 pF 200 ns Output disable time, DO t dis C L = 10 pF , RL = 10 kΩ 80 ns after CS CL = 100 pF, RL = 2 kΩ 250 ns
WM0834, WM0838 Notes: 1. Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. De- vice functional operating range limits are given under Recommended Operating Conditions. Guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. 2. All voltage values, except differential voltages are with respect to the ground. 3. When the input voltage V IN at any pin exceeds the power supply rails (GND > VIN > VCC ) the absolute value of current at that pin should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA supply current to four. 4. A clock duty cycle range of 40% to 60% ensures correct operation at all clock frequencies. For a clock with a duty cycle outside these limits, the minimum time the clock is high or low must be at least 666 ns, with the maximum time for clock high or low being 60 ms. 5. All typical values are at V CC = 5 V, TA = 25oC for 5V devices and VCC = 3.3 V, TA = 25oC for 3.3V devices. Electrical Characteristics (continued) 6. All parameters are measured under open-loop conditions with zero common mode input voltage (unless otherwise stated). 7. Total Unadjusted Error (TUE) is the sum of integral lin- earity error, zero code error and full scale error over the output code range. 8. A Differential linearity of "n" bits ensures a code width exist to "n" bits. Hence a Differential Linearity of 8 bits for an 8 bit ADC guarantees no missing codes. 9. For V IN(-) greater than or equal to VIN(+) the digital out- put code will be 00 Hex. Connected to each analogue input are two diodes which will forward conduct for a diode drop outside the supply rails, V CC and GND. If an analogue input voltage does not exceed the supply volt- age by more than 50 mV, the output code will be cor- rect. To use an absolute input voltage range of 0 to V CC a minimum VCC - 0.05 V is required for all variations of temperature. Care should be exercised when testing at low VCC levels with a maximum analogue voltage as this can cause the input diode to conduct, especially at high temperature, and cause errors for analogue inputs near full scale. 10. Standby input leakage currents, are currents going in or out of the on or off channels when the ADC is not performing conversion and the clock input is in a high or low steady-state condition.
WM0834, WM0838 Test Circuits and Waveforms Output Disable Time Voltage Waveforms and Test Circuits Standby Leakage Current Test Circuit Detailed Timing Diagrams Data Input Timing Data Output Timing Vcc Vcc Vcc GND GND GND tsu tsu thth 50% 50% 50% 50% 50% 50% 50% 2V 2V 0.4V 0.4V 0.4V CLK CLK CS DI (Data In) tpdtpd tsu Vcc Vcc Vcc GND GND GND (Data Out) DO SE
WM0834, WM0838 Functional Timing Diagrams WM0834 Timing WM0838 Timing
WM0834, WM0838 WM0834 Pin Name Type Function
1 NC No connection
2 CS Digital Chip Select
(active low)
3 CH0 Analogue input Channel 0 input
to multiplexer (MUX)
4 CH1 Analogue input Channel 1 input
to multiplexer (MUX)
5 CH2 Analogue input Channel 2 input
to multiplexer (MUX)
6 CH3 Analogue input Channel 3 input
to multiplexer (MUX)
7 DGND Supply Digital ground pin
8 AGND Supply Analogue ground pin
REF Analogue input Voltage reference input
10 DO Digital output Data output
11 SARS Digital output Successive
12 CLK Digital input Clock input
13 DI Digital input Data input
1 CH0 Analogue input Channel 0 input
to multiplexer (MUX)
2 CH1 Analogue input Channel 1 input to
multiplexer (MUX)
3 CH2 Analogue input Channel 2 input to
multiplexer (MUX)
4 CH3 Analogue input Channel 3 input to
multiplexer (MUX)
5 CH4 Analogue input Channel 4 input to
multiplexer (MUX)
6 CH5 Analogue input Channel 5 input to
multiplexer (MUX)
7 CH6 Analogue input Channel 6 input to
multiplexer (MUX)
8 CH7 Analogue input Channel 7 input to
multiplexer (MUX)
9 COM Analogue input Common input for
10 DGND Supply Digital ground pin
11 AGND Supply
12 VREF Analogue input Voltage reference
13 SE Digital input Shift enable control
line (active low)
14 DO Digital output Data Output
15 SARS Digital output Successive
16 CLK Digital input Clock input
17 DI Digital input Data input
18 CS Digital Chip Select
(active low)
19 NC No connection
20 VCC Supply Positive supply
Multiplexer / Package Options Device Number of Analogue Channels Number of No Single Ended Differential Package Pins WM0834 4 2 14 WM0838 8 4 20
WM0834, WM0838 Functional Description Multiplexer Operation and Addressing WM0834 and WM0838 use an input multiplexer scheme thet provides multiple analogue channels, configurable for single-ended or differential operation and also for WM0838, a pseudo-differential mode that will perform an analogue to digital (A/D) conversion of the voltage difference between any analogue input and a common terminal (COM). WM0834/8 uses a successive approximation routine to perform A/D conversion that employs a sample data comparator structure which always performs conversion on a differential voltage. Conversion takes place on the voltage difference between assigned "+" and "-" inputs and the converter expects the "+" input to be the most positive. If the "+" input is more negative than "-" then the converter gives an all zeros output. Assignment of inputs is made for a single-ended signal between an "+" input and analogue ground (AGND) or COM for WM0838, or for differential inputs between adjacent pairs of inputs of either polarity. The COM input of WM0838 acts as the "-" input for pseudo- differential "+" inputs and can be an arbitrary voltage such as an analogue common not at ground potential in single supply applications. Prior to the start of every conversion the input configuration is assigned during the MUX addressing sequence achieved by serially shifting data into the Data Input (DI) on the rising edges of the clock input. The MUX address selects which analogue inputs are enabled, either single-ended, differential or pseudo- differential (WM0838). For differential inputs the polarity of the selected pairs of adjacent inputs are also assigned. Differential inputs can only be assigned to adjacent channel pairs. The MUX addressing tables give full details of input assignments. Initiating Conversion and the Digital Interface WM0834 and WM0838 are controlled from a processor via a serial interface comprising Data In (DI) and Data Out (DO), Chip Select (CS) and Clock (CLK) inputs and a SAR Status (SARS) output. A conversion is initiated by pulling the chip select (CS) line low. CS must be kept low for an entire conversion. The start bit and the MUX assignment bits on DI are clocked in on the rising edges of the clock input, which may be generated by the processor or run continuously. WM0834 uses three MUX assignment bits and WM0838 uses four. When the logic "1" start bit is clocked into the start conversion location of the multiplexer input register, the analogue MUX inputs are selected. After 1/2 a clock period delay to allow for the selected MUX output to settle, the conversion commences using the successive approximation technique. At this time, the SARS output goes high to indicate a conversion is in progress and the DI input is disabled. When conversion begins, the A/D conversion result from the output of the SARS comparator appears at the DO output on each falling edge of the clock (see Functional Timing Diagrams). With the successive approximation A/D conversion routine, the analogue input is compared with the output of a digital to analogue converter (DAC) for each bit by the SARS comparator and a decision made on whether the analogue input is higher or lower than the DAC output. Successive bits, MSB to LSB are input to the DAC and remain in its input if the analogue comparison decides the analogue input is higher than the DAC output. If not, the bit is removed from the DAC input. The output from the SARS comparator forms the resulting input to the DAC and the A/D conversion output, and is read by the processor as conversion takes place in MSB to LSB order. After 8 clock periods, the conversion is complete and this is indicated by SARS being brought low a 1/2 clock period later. All bits of the conversion are stored in an output shift register after a conversion has completed and MSB first data has been output. For WM0838, the commencement of output data in a LSB first format can be controlled by use of the SE input. If the SE input is held high, the LSB output will remain on the DO output. When SE is brought low, LSB first data output will begin on DO. After 8-bits of LSB first data have been output, the DO output goes low and remains low until CS is brought high, when outputs (DO & SARS) go into a high impedance state.
WM0834, WM0838 Functional Description (continued) WM0834 MUX Addressing MUX Address Channel Number SGL/DIF ODD/EVEN Select bit 0 1 2 3 Differential MUX Mode (Between adjacent pairs of points) 00 0 + - 00 1 + - 01 0 - + 01 1 - + Single Ended MUX Mode (between selected input(s) and AGND) 10 0 + 10 1 + 11 0 + 11 1 + Note: Analogue common input 'COM' used with single ended mode is internally tied to AGND All internal registers are cleared when CS is high. To initiate another conversion, CS must make a high to low transition and MUX address assignments input to DI. The DI inpit and DO output can be tied together and controlled via a bidirectional processor I/O bit line. Reference Input The analogue input voltage range Vmax to Vmin for differential and pseudo-differential input is defined by the voltage applied to the reference input with respect to AGND. WM0834/8 can be used in ratiometric appliacations or those requiring absolute accuracy. A ratiometric input is typically the Vcc and is the same supply used to power analogue input circuitry and sensors. In such systems under a given input condition, the same code will be output with variations in supply voltage, because the same ratio change occurs in both the analogue and reference input to the A/D. When used in applications requiring ab- solute accuracy, a suitable time and temperature stable voltage reference source should be used. The voltage source used to drive the reference input should be capable of driving the 2.4kΩ typical of the SAR resistor ladder. The maximum input voltage to the reference input is the Vcc supply voltage. The minimum can be as least as low as 1V to allow for direct conversion of sensor outputs with output voltage ranges less than 5V. Analogue Inputs While sampling the analogue inputs, short spikes of current enter a "+" input and flow out of the corresponding "-" input at the clock edges during conversion. This current does not cause errors as it decays rapidly and the internal comparator is strobed at the end of a clock period. Care should be exercised if bypass capacitors are used at the inputs as an apparant offset error can be caused by the capacitor averaging the input current and developing a volt- age across the source resistance. Bypass capacitors should not be used with a source resistance greater than 1kΩ. In considering error sources, input leakage current will also cause a voltage drop across the source resistance and hence, high impedance sources should be buffered. In differential mode, there is a 1/2 clock period interval between sampling the "+" and the "-" inputs. If there is a change in common mode voltage during this interval, an errorcould notionally result. For a sinusoidal common mode signal, the error is given by: VERROR = VPEAK (2 πfCM) (1/(2fCLK)) Where V PEAK = peak common mode voltage fCM = common mode signal frequency fCLK = clock frequency
WM0834, WM0838 WM0838 MUX Addressing MUX Address SGL/ ODD/ Select biits Channel Number DIF EVEN 1 0 0 1 2 3 4 5 6 7 COM Differential MUX Mode (between adjacent pairs of inputs) 00 0 0 + - 00 0 1 + - 00 1 0 + - 00 1 1 + - 01 0 0 - + 01 0 1 - + 01 1 0 - + 01 1 1 - + Single Ended MUX Mode (between selected input(s) and 'COM' pseudo analogue ground) 10 0 0 + - 10 0 1 + - 10 1 0 + - 10 1 1 + - 11 0 0 + - 11 0 1 + - 11 1 0 + - 11 1 1 + -
WM0834, WM0838 Performance Data Test conditions: VDD = 5V, VREF = 5V, Temp = 25oC, FCLK = 250kHz WM0834: Total Unadjusted Error -0.75 -0.5 -0.25 0.25 0.5 0.75 0 32 64 96 128 160 192 224 256 Code Error (lsbs) WM0838: Total Unadjusted Error -0.75 -0.5 -0.25 0.25 0.5 0.75 0 32 64 96 128 160 192 224 256 Code Error (lsbs)
WM0834, WM0838 Package Descriptions Plastic Small-Outline Package Notes: A. Dimensions in millimeters. B. Complies with Jedec standard MS-012. C. This drawing is subject to change without notice. D. Body dimensions do not include mold flash or protrusion. E. Dimension A, mould flash or protrusion shall not exceed 0.15mm. Body width, interlead flash or protrusions shall not exceed 0.25mm. NM i n M a x 8 4.80 5.00 14 8.55 8.75 16 9.80 10.00 Dimension 'A' Variations D - 8 pins shown 0.51 0.33 1.75 1.35 0.25
0.10 Pin spacing
1.27 B.S.C. 1.27 0.40 0 to 8 OO 0.25 0.19 0.50 0.25 x 45 NOM O 6.20 5.80 4.00 3.80 A Rev. 1 November 96
WM0834, WM0838 Package Description Wide body Plastic Small-Outline Package 1,27 B.S.C. 0,51 0,33 0,25 M 916 7,60 7,40 10,65 10,00 A 2,65 2,35 0,30 0,10 1,27 0,40 Gauge Plane 0o - 8o 0,10 Notes: A. Dimensions in millimeters. B. Complies with Jedec standard MS-013. C. This drawing is subject to change without notice. D. Body dimensions do not include mold flash or protrusion. E. Dimension A, mould flash or protrusion shall not exceed 0.15mm. Body width, interlead flash or protrusions shall not exceed 0.25mm. DW - 16 pin shown DIM A MIN A MAX PINS** 10,50 13,00 10,10 12,60 15,60 15,20 18,10 17,70 0.75 x 450 0.25 x 450 Rev. 1 November 96 0,33 0,23
WM0834, WM0838 Package Descriptions Notes: A. Dimensions are in inches B. Falls within JEDEC MS-001( 20 pin package is shorter than MS-001) C. N is the maximum number of terminals D. All end pins are partial width pins as shown, except the 14 pin package which is full width. Dimension 'A' Variations Dual-In-Line Package N or P Rev. 1 November 96 NM i n M a x 8 0.355 0.400 14 0.735 0.775 16 0.735 0.775 20 0.940 0.975 0.210 Max. 0.070 Max. 0.045 0.030 0.022 0.014 0.015 Min. 0.150 0.115 0.005 Min. Pin spacing 0.100 B.S.C. N Seating plane 0.280 0.240 0.325 0.290 0.014 0.008 105 O O N/2 A