WL9005 WPMTEK | Alldatasheet
Document overview
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Technical content
Features
Low Power Consumption: 0.3 µA (Typ) Maximum Output Current: 500mA Low Dropout Voltage: 100mV@100mA (VOUT=3.3V) Operating Voltage Range: 2.0V ~ 7.0V Output Voltage Accurate: ± 1.5% High PSRR: 70dB @1kHz Good Transient Response Integrated Short-Circuit Protection Over-Temperature Protection Output Current Limit Low Temperature Coefficient Stable with Ceramic Capacitor RoHS Compliant and Lead (Pb) Free -40°C to +85°C Operating Temperature Range Special Request: Any Voltagebetween 0.8V and 5.0V under specific business agreement Available in Green SOT23-3,SOT23-5,SOT89-3,DFN1X1-4L,DFN2X2-6L Packages
Applications
Battery-powered equipment Wireless Communication Equipment Reference voltage sources Audio/Video Equipment Low Power Microcontrollers Portable games Ver1.51 - 1 - www.wpmtek.com
Figure 1. WL9005 Typical Application Circuit
Pin No. SOT23-5 SOT23-3 SOT89-3 DFN1010-4L DFN2020-6L S5 S3 P3 D4 D6 Pin Name Pin Function 1 3 2 4 3 VIN Power Input 2 1 1 2 2 GND Ground 3 ----- ----- 3 1 EN Enable Control Input 5 2 3 1 4 VOUT Output Voltage 4 ----- ----- ----- 5、6 NC No Connect EP / TAB In PCB layout, prefer to use large copper area to cover this pad for better thermal dissipation Order Information WL9005①②-③④ Designator Symbol Description ①② S3 , S5 , P3 , D4 , D6 SOT23-3L , SOT23-5L , SOT89-3L , DFN1X1-4L , DFN2X2-6L 7V ,0.3μA IQ ,High PSRR ,500mA Low-Dropout LDOPart NO. Description Package T/R Qty WL9005S3-XX SOT23-3L 3,000 PCS WL9005S5-XX SOT23-5L 3,000 PCS WL9005P3-XX SOT89-3L 1,000 PCS WL9005D4-XX DFN1X1-4L 10,000 PCS WL9005D6-XX DFN2X2-6L 5,000 PCS Marking Information For marking information, contact our sales representative directly All WPMtek parts are Pb-Free and adhere to the RoHS directive. WL9005 7V, 0.3μA IQ, High PSRR, 500mA Low-Dropout LDO Ver1.51 - 3 - www.wpmtek.com
Supply Input Voltage V IN -0.3 ~ 9 V EN to GND V EN -0.3 ~ 9 V Regulated Output Voltage V OUT -0.3 ~ 5 V Output Current I OUT Internally limited mA SOT23-3L 450 SOT23-5L 500 SOT89-3L 700 DFN1X1-4L 530 Power Dissipation PD @TA=+25℃ DFN2X2-6L PD 750 mW SOT23-3L 275 SOT23-5L 250 SOT89-3L 180 DFN1X1-4L 235 Thermal Resistance (Junction to air) DFN2X2-6L θJA 165 °C /WHuman Body Model (HBM) ±4000 V Charged Device Mode (CDM) ±2000 V Machine Mode (MM) 200 V Storage Temperature Range T STG -65 ~ +150 °C Operating Junction Temperature T J +150 °C Lead Temperature (Soldering 10s) T LEAD +260 °C Note： 1、Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended period may affect device reliability. 2、Ratings apply to ambient temperature at +25°C. 3、The package thermal impedance is calculated in accordance to JESD 51-7. Recommended Operating Conditions Item Min Max Unit Operating Ambient Temperature -40 +85 °C Input Voltage 2.0 7.0 V Output Voltage 0.8 5.0 V WL9005 7V, 0.3μA IQ, High PSRR, 500mA Low-Dropout LDO Ver1.51 - 4 - www.wpmtek.com
Electronic Characteristics Test Conditions: VIN = VOUT +1V,CIN=COUT=1uF,TA=25℃, unless otherwise specifi Note : All limits specified at room temperature (TA = 25°C) unless otherwise specified. All room temperature limits are 100% production tested. All limits at temperature extremes are ensured through correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Parameter Symbol Test Conditions Min Typ Max Unit Input Voltage VIN 2.0 —— 7.0 V Quiescent Current IQ VIN >VOUTNOM , VIN=EN IOUT =0mA —— 0.3 0.5 µA Shutdown Current ISHDN EN=0 V , VOUT =0 V 0 0.1 µA Output Voltage VOUT VIN = VOUTNOM +1V IOUT =10mA VOUT x 0.985 —— VOUT x 1.015 V Output Current IOUT VIN = VOUTNOM +1V 500 —— —— mA IOUT =100mA —— 100 ——Dropout Voltage VOUT =3.3V VDROP IOUT =500mA —— 600 750 mV Line Regulation Δ VLINE IOUT =10mA VOUTNOM +1.0V ≦ VIN ≦7V —— 0.05 —— % / V Load Regulation Δ VLOAD VIN = VOUTNOM +1V 1mA≦ IOUT ≦100mA —— 5 20 mV VCEH CE“High”Voltage 1.2 —— —— VEN Threshold Voltage VCEL CE“Low”Voltage —— —— 0.4 V EN PIN Current IEN —— 0.01 —— µA Current Limit ILIMIT —— 650 —— mA Short Current ISHORT VOUT = GND —— 100 —— mA Output Noise Voltage VON VOUT=3.3V , IOUT =200mA BW = 100Hz~10KHz, —— 100 —— µVrms f=1kHz —— 70 —— dBPower Supply Rejection Rate PSRR IOUT =100mA, VOUT =3.3V f=10kHz —— 65 —— dB Temperature Coefficient Δ VOUT / Δ T * VOUT IOUT =30mA , TA=0~70°C —— ± 100 —— ppm/°C Thermal Shutdown Temperature TSHDN —— —— 160 —— °C Thermal Shutdown Hysteresis ΔTSHD —— —— 20 —— °C WL9005 7V, 0.3μA IQ, High PSRR, 500mA Low-Dropout LDO Ver1.51 - 5 - www.wpmtek.com
Functional Block DiagramFigure 2. WL9005 Block Diagram WL9005 7V, 0.3μA IQ, High PSRR, 500mA Low-Dropout LDO Ver1.51 - 6 - www.wpmtek.com
Typical Performance Characteristics (VIN = EN =4.3V ,VOUT=3.3V,CIN=COUT=1uF,TA=25℃) Output Voltage vs TEMP Input Voltage vs. IQ (Note about IQ ) Load Regulation Line Regulation Dropout Voltage vs.Load Curren PSRR vs. Frequency WL9005 7V, 0.3μA IQ, High PSRR, 500mA Low-Dropout LDO Ver1.51 - 7 - www.wpmtek.com
Load Transient Response Short Output & Over-Current Response Power-On Power-Off Enable Disable WL9005 7V, 0.3μA IQ, High PSRR, 500mA Low-Dropout LDO Ver1.51 - 8 - www.wpmtek.com
Note about IQ: IQ refers to the working current when the chip is no-load, only when Vin >Vout The chip will have a very low working current, the above diagram is for Vout 1.5v Measured Curve, when Vin<Vout, the chip is in an abnormal state that can not reach the intended output, therefore, the operating current will increase significantly. For applications where IQ requirements are strict, make sure the chip stops working when Vin <Vout. Application Guideline Input Capacitor A ≥ 1μF ceramic capacitor is recommended to connect between VIN and GND pins to decouple input power supply glitch and noise. The amount of the capacitance may be increased without limit. This input capacitor must be located as close as possible to the device to assure input stability and less noise. For PCB layout, a wide copper trace is required for both VIN and GND. Output Capacitor An output capacitor is required for the stability of the LDO. The recommended output capacitance is ≥1μF, ceramic capacitor is recommended, and temperature characteristics are X7R or X5R. Higher capacitance values help to improve load/line transient response. The output capacitance may be increased to keep low undershoot/overshoot. Place output capacitor as close as possible to VOUT and GND pins. Load Transient VIN=EN=5V Load Transient VIN=EN=5V IOUT(DC)=0 to 180mA (100mA/div) , TR=TF=1ms IOUT(DC)=0 to 360mA (100mA/div) , TR=TF=1ms VOUT(AC)=( 100mV/div) , VOUT(AC)=( 100mV/div) , WL9005 7V, 0.3μA IQ, High PSRR, 500mA Low-Dropout LDO Ver1.51 - 9 - www.wpmtek.com
The dropout voltage refers to the voltage difference between the VIN and VOUT pins while operating at specific output current. The dropout voltage V DROP also can be expressed as the voltage drop on the pass-FET at specific output current (IRATED) while the pass-FET is fully operating at ohmic region and the pass-FET can be characterized asan resistance RDS(ON). Thus the dropout voltage can bedefined as (VDROP = VIN − VOUT = RDS(ON) x IRATED). Fornormal operation, the suggested LDO operating range is (VIN > VOUT + V DROP) for good transient response and PSRR ability. Vice versa, while operating at the ohmic region will degrade the performance severely. Thermal Application For continuous operation, do not exceed the absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated as below: TA=25°C, AISIS DEMO PCB, The max PD= (Tj − TA) / θJA. Power dissipation (P D) is equal to the product of the output current and the voltage drop across the output pass element, as shown in the equation below: PD = (VIN – VOUT) × IOUT Layout Consideration By placing input and output capacitors on the same side of the PCB as the LDO, and placing them as close as is practical to the package can achieve the best performance. The ground connections for input and output capacitors must be back to the WL9005 ground pin using as wide and as short of a copper trace as is practical.Connections using long trace lengths, narrow trace widths, and/or connections through via must be avoided. These add parasitic inductances and resistance that results in worse performance especially during transient conditions. WL9005 7V, 0.3μA IQ, High PSRR, 500mA Low-Dropout LDO Ver1.51 - 10 - www.wpmtek.com WPMtek reserves the right to make changes to the product specification and data in this document without notice. WPMtek makes no warranty, representation or guarantee regarding the suitability of its products for any particu lar purpose, nor does WPMtek assume any liability arising from the application or use of any products or circuits, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Any enquiry ,please write to sales@wpmtek.com for futher information.