W3020 AGERE | Alldatasheet
Document overview
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Technical content
Features
n 2.7 V operation, low power consumption n Integrated receive, transmit, and synthesizer functions n IF frequency and transmit offset frequency generated from the same LO n Integrated dual LNAs and mixers n Minimizes PCB design work between systems n Surface-mount, 64-pin TQFPT package
Applications
n GSM dual-band hand portables: — GSM900/1800 — GSM900/1900 n GSM single-band hand portables: — GSM900 — GSM1800 — GSM1900 GSM1800/1900
540 MHz VCO
Φ ÷ 2 Φ ÷ 2 ÷ 3Σ W3000 FREQUENCY SYNTHESIZER DAC ADC ADC GSM900 900: 925 MHz—960 MHz 1800: 1805 MHz—1880 MHz 1900: 1930 MHz—1990 MHz 900: 880 MHz—915 MHz 1800: 1710 MHz—1785 MHz 1900: 1850 MHz—1910 MHz 900: 1150 MHz—1230 MHz 1800: 1530 MHz—1610 MHz 1900: 1660 MHz—1730 MHz 1800/1900: 180 MHz TX IF VCO SAW IF
270 MHz
& AGC CONTROL RX I RX Q TX I TX Q Note: shaded area is off-chip. PA SWITCHED DIVIDER LO2 PLL 900: 270 MHz GSM1800/1900 GSM900 Figure 1 . W3020 Circuit Block Diagram
Table 18. T4: Receive IF Duty Cycle Corrector Table 19. T3: Divide-by-3 Duty Cycle Corrector Table 25. T0: TX IF Duty Cycle Corrector Disable . 24 Table 38. C3: Receive LO1 Buffer Mode During dc Table 40. C1: 540 MHz LO2 Phase Detector Table 43. Initialize CONFIG Register Table 45. Settle PLL to GSM1800 Band for Receive Table 47. Settle PLL in GSM1800 Band for Table 48. Basic GSM1800 Transmit Burst Table 50. GSM1800/GSM1900 LNA Table 51. Receive IF Amplifier Input Table 52. Receive IF Amplifier Input Table 54. Transmit IF Input to Up-Conversion Table 55. Transmit RF Output from Up-Conversion
W3020 GSM Multiband RF Transceiver December 1999 4 Lucent Technologies Inc.
Description
The W3020 is a highly integrated GSM transceiver designed to operate in dual-band handsets or in single-band handsets operating at 900, 1800, and
1900 MHz frequency bands (1900 MHz performance
is not verified in production). The IC architecture allows the RF designer to provide solutions for three different frequency bands with very few PCB changes, thereby providing faster time to market and reduced development time. The W3020 RF transceiver and W3000 PLL have been designed in conjunction with the SC1 (radio interface and DSP) to provide a complete GSM cellular solution. The W3020 interfaces to the W3000 UHF high-performance PLL IC. The W3020, in combination with the W3000, provides the transmitter, receiver, and frequency synthesizer. Adding a power amplifier(s), filters, and VCO modules completes the radio channel. The baseband modulated signal is applied to the I/Q double-balanced mixer in a differential manner. The ±45° phase-shifted local oscillator requires no trim to achieve the required modulation spectral mask. Also, I/Q input signals require no dc offset calibration to achieve high phase accuracy signal. The IF signal outputs from the I/Q mixers are summed and brought out to an external filter that reduces the noise that could be intermodulated into the receive band. This signal is then applied to the low noise up-conversion mixer and brought to the RF output. The received signal is amplified through the low-noise amplifier, which, combined with the preceding filter, dominates the receiver sensitivity. The signal is then passed through another external filter to attenuate the image frequency to an acceptable level. The signal passes through the RF down-conversion mixer to the IF frequency. It is then filtered by an external surface acoustic wave (SAW) filter to bring the in-band blocking signals to an acceptable level. The signal is amplified in the IF strip of the receiver. The IF strip contains digital gain control (DGC) amplifiers at both the IF and baseband frequencies and precision low- pass filters. This allows the signal to be amplified while in-band blocking signals are removed. The precision I/Q demodulator splits the signal into its in- phase and quadrature signals. The I/Q signals are low- pass filtered and further amplified. The I/Q amplifier contains integrated dc offset calibration circuitry. The outputs (I/Q) are fed to the ADC for further signal processing. The second local oscillator (LO2), comprising a buffer for the external voltage-controlled oscillator (VCO) and a phase-locked loop (PLL), feeds the IF portions of both the modulator and the receiver. An external reference source, voltage-controlled crystal oscillator (VCXO), is divided from 13 MHz to 1 MHz through a counter. The 1 MHz is called the comparison frequency. The VCO frequency of 540 MHz is also divided down to 1 MHz. Both signals are fed into a phase detector, and the resultant error signal is fed through an external low-pass filter to the control input of the VCO. The RF receive and transmit mixers are driven by two band-switchable external VCO modules and buffered internally on the IC. The VCOs are both controlled by a single W3000 PLL synthesizer and loop filter. Fast band-locking is achieved using a proprietary scaling technique integrated in the W3000 PLL.
December 1999 W3020 GSM Multiband RF Transceiver Lucent Technologies Inc. 5 Description (continued) Detailed Block Diagram GNDS1 DL1P DL1N GNDL1 GL1P GL1N V SS CLK DAT LAT LD GNDS2 LO2 LOCK LNA 1800 LNA 900 RF MIXERS GSM
1800 GSM
2 OR 3
EEL[1:3] EEL[1:3] TIP TQNTQPTIN LO2 BUFFER
540 MHz
G[0:6] GND V CC GND V CC GND V CCM V CC V CC GND GND EEGND V CC V CC GND V CCB GND BIAS V CCB V CCB B s s s s B TX MIXER MUX V CC GND GNDS3 RIP RIN RQP RQN V DD B GNDB TQN TQP TIN TIP V DD I GNDI IFIP IFIN TEST TEST B GNDS4 CP2 EEL2 DLNAI EEL3 GLNAI TIFIP TIFIN V DD L 2 L2P L2N V DD C 2 GNDC2 GNDL2 GNDP2 V DD P2 8 dB MCI MCG V DD L1 s LO2 PLL V DD CONTROL LOGIC/ SERIAL BUS V CC GND V DD GND EEL1 DLNAO GNDL GLNAO TOV TOUT V DD R 1 DMIP MIN GMIP EER1 TIFOP TIFON RMON RMOP V DD R 249 Figure 2 . IC Block Diagram with Pinout
W3020 GSM Multiband RF Transceiver December 1999 6 Lucent Technologies Inc. Pin Information Table 1 . Pin Assignment Pin Symbol Type Pin Description
1 EEL2 Input* LNA Emitter Ground
2 DLNAI Input GSM1800/1900 Band LNA Signal Input
3 EEL3 Input* LNA Emitter Ground
4 GLNAI Input GSM900 Band LNA Signal Input
5 TIFIP Input TX IF Input to Mixer
6 TIFIN Input TX IF Input to Mixer
7 GNDS4 Ground Substrate Ground
8 GNDP2 Ground LO2 PLL Ground
9 V DD P2 Supply LO2 PLL Voltage Supply
10 V DD C2 Supply LO2 Charge Pump Supply
11 CP2 Output Charge Pump LO2 Output
12 GNDC2 Ground LO2 Charge Pump Ground
13 V DD L2 Supply LO2 Buffer Supply
14 L2P Input LO2 Positive Input (540 MHz)
15 L2N Input LO2 Negative Input (on-chip ac ground)
16 GNDL2 Ground LO2 Buffer Ground
17 GNDS1 Ground Substrate Ground
18 MCI Input Master Clock Input
19 MCG Input Master Clock Negative Input (ac ground)
20 V DD L1 Supply V DD Supply for LO1
21 DL1P Input GSM1800/1900 LO1 Positive Input
22 DL1N Input GSM1800/1900 LO1 Negative Input (on-chip ac ground)
23 GNDL1 Ground LO1 Ground
24 GL1P Input GSM900 LO1 Positive Input
25 GL1N Input GSM900 LO1 Negative Input (on-chip ac ground)
26 V DD Supply Voltage Supply for All Digital Circuits
27 V SS Ground Ground for All Digital Circuits
28 CLK Input Clock Input for Serial Bus
29 DAT Input Data Input for Serial Bus
30 LAT Input Latch Enable Input for Serial Bus
31 LD Output LO2 Synthesizer Lock Indicator Output
32 GNDS2 Ground Substrate Ground
*The emitters are considered critical inputs that need to be carefully grounded externally.
Table 1. Pin Assignment (continued)
33 Test Output Production Test Output
34 IFIN Input IF DGC Amplifier Input Negative
35 IFIP Input IF DGC Amplifier Input Positive
36 GNDI Ground Ground for IF Amplifier
37 V DD I Supply Voltage Supply IF Amplifier
38 TIP Input TX In-Phase Positive Input
39 TIN Input TX In-Phase Negative Input
40 TQP Input TX Quadrature Positive Input
41 TQN Input TX Quadrature Negative Input
42 GNDB Ground Baseband RX Ground
43 V DD B Supply Baseband RX V DD Supply
44 RQN Output RX Quadrature Phase Negative Output
45 RQP Output RX Quadrature Phase Positive Output
46 RIN Output RX In-Phase Negative Output
47 RIP Output RX In-Phase Positive Output
48 GNDS3 Ground Substrate Ground RF dc Supply
49 V DD R2 Supply RF RX/TX Voltage Supply
50 RMOP Output RX Mixer Output Positive
51 RMON Output RX Mixer Output Negative
52 TIFON Output TX IF Output from Modulator Negative
53 TIFOP Output TX IF Output from Modulator Positive
54 EER1 Input* RX Mixer Emitter Ground
55 GMIP Input GSM900 Mixer Input Positive
56 MIN Input RF Mixer Input Negative (ac ground)
57 DMIP Input GSM1800 Mixer Input Positive
58 V DD R1 Supply RF RX Voltage Supply
59 TOUT Output Transmit Mixer Output
60 TOV Output Transmit Mixer Output
61 GLNAO Output GSM Band LNA Output
62 GNDL Ground LNA Substrate Ground
63 DLNAO Output GSM1800 Band LNA Output
64 EEL1 Input* LNA Emitter Ground
*The emitters are considered critical inputs that need to be carefully grounded externally.
W3020 GSM Multiband RF Transceiver December 1999 8 Lucent Technologies Inc. Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. Exposure to maximum ratings for extended periods can adversely affect device reliability. Parameter Symbol Min Max Unit Ambient Operating Temperature T A –30 85 °C Storage Temperature T stg –65 150 °C Lead Temperature (soldering, 10 s) — — 300 °C Positive Supply Voltage V DD 0 4.5 V Power Dissipation P D — 550 m W ac Peak-to-Peak Input Voltage Vp-p 0 V DD V Digital Voltages — 0 V DD V ESD Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent Technologies Microelectronics Group employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance = 1500 Ω , capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters: Parameter Method Rating Unit ESD Threshold Voltage HBM 1500 V ESD Threshold Voltage (corner pins) CDM 1000 V ESD Threshold Voltage CDM 500 V Operating Range The device is fully functional within the following operation ranges. No claims of parametric performance are stated within this range. For parametric performance, refer to the individual specifications and operating conditions. Parameter Symbol Min Max Unit Operating Temperature T A –30 85 °C Nominal Operating Voltage V DD 2.7 3.6 V
December 1999 W3020 GSM Multiband RF Transceiver Lucent Technologies Inc. 9 Digital Serial Inputs Parameter Symbol Min Max Unit Logic High Voltage V IH 0.7 * V DD — V Logic Low Voltage V IL — 0.3 * V DD V Logic High Current (V IH = 3.0 V) |I IH | — 10 µA Logic Low Current ( V IL = 0.0 V) |I IL | — 10 µA Clock Input Frequency (V DD = 2.7 V) f CLK — 10 MHz Digital Outputs Parameter Symbol Min Max Unit Logic High Voltage V OH V DD – 0.4 — V Logic Low Voltage V OL — 0.4 V Logic High Current (V OH ≥ V DD – 0.4) |I OH | 2 — mA Logic Low Current (V OL ≤ 0.4 V) |I OL | 2 — mA Enable Time V DD = 2.7 Vdc; T A = 25 °C ± 3 °C. Parameter Min Typ Max Unit Logic Powerup/down Time — — 4.0 µs Supply Currents V DD = 2.7 Vdc; T A = 25 °C ± 3 °C. System Mode Min Typ Max Unit Powerdown (V DD = 3.0 Vdc)* — 2 50 µA PLL RX Settling — 33 — mA RX Mode (LNA = ON) — 68 — mA RX Mode (LNA = OFF) — 64 — mA PLL TX Settling — 33 — mA TX Mode — 92 — mA *This current does not include LO2 charge pump supply current. (See LO2 specification for details.)
W3020 GSM Multiband RF Transceiver December 1999 10 Lucent Technologies Inc. LNA The W3020 contains two on-chip LNAs, one to operate in the GSM900 band and one to operate in the GSM1800/1900 bands. The GSM900 operation is combined with the GSM1800 band operation in a dual-band terminal. Only one LNA operates at a time. The two on-chip LNAs with external matching networks are 50 Ω single-ended input, single-ended output type. Switching between the LNAs is determined by the band bit B and the gain control bit G0 in the TR register, as described in the Programming Information section. Table 2 . GSM900 LNA Performance V DD = 2.7 Vdc; T A = 25 °C ± 3 °C. Parameter Min Typ Max Unit RF Input Band 925 — 960 MHz Current Consumption (collector current) — 3.5 — mA Noise Figure* — 2.0 — dB Power Gain (942 MHz)* — 20 — dB Input 1 dB Compression Level –20 –15 — dBm Input Return Loss — 14 — dB Off-state Gain — –51 — dB * All gain and NF include matching losses. Not tested in production. Table 3 . GSM1800/1900 LNA Performance V DD = 2.7 Vdc; T A = 25 °C ± 3 °C. Parameter Min Typ Max Unit RF Input Band: GSM1800 1805 — 1880 MHz GSM1900 1930 — 1990 MHz Current Consumption (collector current) — 3.5 — mA Noise Figure* — 3.0 — dB Power Gain (1842 MHz)* — 19 — dB Input 1 dB Compression Level –20 –16.5 — dBm Input Return Loss — 15 — dB Off-state Gain — –38 — dB * All gain and NF include matching losses. Not tested production.
December 1999 W3020 GSM Multiband RF Transceiver Lucent Technologies Inc. 11 RF Mixer The W3020 contains two mixers: one for GSM900 band operation and one for GSM1800/1900 band operation. The RF mixers are double-balanced mixers that can be used in various modes of operation. The ac-grounded input (pin 56) requires grounding at both the RF and the IF frequencies. If grounding is not placed close to the device, the RF performance will be compromised. At the output, the mixer is connected to a balanced IF SAW filter. Table 4 . RF Performance: GSM900 V DD = 2.7 V; T A = 25 °C ± 3 °C. F IN = 942 MHz Parameter Min Typ Max Unit RF Input Band 925 — 960 MHz Output IF Frequency — 270 — MHz LO Frequency Range 1195 — 1230 MHz Noise Figure (SSB) — 9 12 dB Mixer Power Gain* 7 dB I/P 1 dB Compression –10 –5 — dBm *LO1 level = –6 dBm, F LO = 1212 MHz, F IF = 270 MHz. Table 5 . RF Performance: GSM1800/1900 V DD = 2.7 V; T A = 25 °C ± 3 °C. F IN = 1842 MHz Parameter Min Typ Max Unit RF Input Band: GSM1800 1805 — 1880 MHz GSM1900 1930 — 1990 MHz Output IF Frequency — 270 — MHz LO Frequency Range: GSM1800 1535 — 1610 MHz GSM1900 1660 — 1720 MHz Noise Figure (SSB) — 9.5 12 dB Mixer Power Gain* 4 6 — dB I/P 1 dB Compression –12 –7 — dBm *LO1 level = –6 dBm, F LO = 1572 MHz, F IF = 270 MHz
December 1999 W3020 GSM Multiband RF Transceiver Lucent Technologies Inc. 13 IF/Baseband Amplifier (continued) Table 6 . IF/Baseband Amplifier Performance V DD = 2.7 V; T A = 25 °C ± 3 °C. Parameter Min Typ Max Unit Total Voltage Gain (referred to 50 Ω input)* 60 65 68 dB Demodulator Gain — 4 — dB Absolute Gain Accuracy † –2.0 — 2.0 dB Relative Gain Step Accuracy ‡ –1.0 — 1.0 dB Noise Figure (matched to 50 Ω ) § — 6.2 12 dB O/P 1 dB Compression Point (0 dB gain setting) O/P 1 dB Compression Point (>16 dB baseband gain setting) 12 — — dBm(V) ** Output Load Capacitance (differential) — — 10 pF Output Load Capacitance (single-end to ground) — — 10 pF Output Load Resistance (differential) 20 — — k Ω Output Load Resistance (single-end to ground) 40 — — k Ω IF Enable Time — — — µs I/Q Output Current ±50 — — µA I/Q Phase Accuracy § — 3.5 — degrees I/Q Amplitude Mismatch § –1 ±0.1 1 dB I/Q Differential Offset Voltage (corrected) § ,†† — 5 ± 50 mV Offset Correction Decay Rate § — 2 — mV/s IF Input Impedance (diffferential) 32 dB gain setting 0 dB gain setting 114 – j497 92 – j497 Ω Ω * 64 dB DGC setting. This voltage gain is measured from the input of the IF strip to either the I or Q channel output. † The absolute accuracy refers to the total gain variation from the nominal condition over temperature (–30 °C to +85 °C) af ter gain calibration at nominal temperature. ‡ The relative gain step accuracy is determined after the 32 dB gain stage has been calibrated at nominal temperature. The total gain step accuracy at any of the possible gain conditions should not vary more than the specified amount within a 20 dB measurement window. § At 64 dB gain setting. ** This is a voltage and specified in dBm as if the voltage were across a 50 Ω load. ††Offset tested in coarse dc-correction mode only.
W3020 GSM Multiband RF Transceiver December 1999 14 Lucent Technologies Inc. IF/Baseband Amplifier (continued) Table 7 . Low-Pass Rejection Characteristics V DD = 2.7 V; T A = 25 °C ± 3 °C; high bandwidth. Parameter Min Typ Max Unit Corner Frequency* 130 168 226 kHz Group Delay Distortion (0 kHz—75 kHz) — 61 — ns Attenuation: 75 kHz — 0.4 — dB 100 kHz — 0.8 — dB 200 kHz — 4.7 — dB 400 kHz — 18 — dB 600 kHz — 28 — dB 800 kHz — 35 — dB
1.6 MHz — 53 — dB
3.0 MHz — 69 — dB
- After filter tuning. (See FilterTune and dc Offset Correction Tuning section.)
December 1999 W3020 GSM Multiband RF Transceiver Lucent Technologies Inc. 15 Modulator The modulator uses an indirect I/Q modulator architecture that is ideal for multiband operation. The IF modulation improves EVM effects due to improved carrier feedthrough. The series transmit IF filters allow improved wideband noise, which enables duplexer removal. The I/Q modulator requires no amplitude or phase calibration to achieve high phase accuracy. The modulator can be altered between GSM900 transmit mode (TX IF = 270 MHz) and GSM1800/1900 transmit mode (TX IF = 180 MHz) by the band bit setting in the TR register. Table 8 . Modulator Performance Parameter Min Typ Max Unit I/Q Signal Path Bandwidth — 450 — kHz I/Q Input Resistance to Ground 25 — — k Ω I/Q Input Capacitance to Ground — — 10 pF I/Q Input Resistance (differential) 10 — — k Ω I/Q Input Capacitance (differential) — — 10 pF I/Q Common-mode Range 1.5 — V DD – 1.05 V I/Q Input Differential Signal for Max Output 0.8 1 1.2 Vp-p RF Output Band: GSM900 GSM1800 GSM1900 880 1710 1850 915 1785 1910 MHz MHz MHz Output Power: GSM900 (LO1 at 1167 MHz) GSM1800 (LO1 at 1567 MHz) –4.5 dBm dBm Powerup Time* — — 4 µs RMS Phase Accuracy †: GSM900 GSM1800 2.0 2.5 °rms °rms GMSK Modulation Spectrum (max) (offset from carrier): 100 kHz @30 kHz RBW — — 0.5 dBc 200 kHz — — –30 dBc 250 kHz — — –33 dBc 400 kHz — — –60 dBc 1.8 MHz—3.0 MHz @100 kHz RBW — — –65 dBc 3.0 MHz—6.0 MHz — — –65 dBc >6.0 MHz — — –73 dBc Wideband Noise IF Modulator GSM900: |f – f 0 | ≥ 10 MHz — –140 — dBc/Hz |f – f 0 | ≥ 20 MHz (PM) — –140 — dBc/Hz GSM1800: |f – f 0 | ≥ 20 MHz (PM) — –140 — dBc/Hz Wideband Noise RF Mixer (See Figure 6 .): GSM900: |f – f 0 | ≥ 10 MHz — –154 — dBc/Hz |f – f 0 | ≥ 20 MHz (PM) — –154 — dBc/Hz GSM1800: |f – f 0 | ≥ 20 MHz (PM) — –153 — dBc/Hz * From the programming latch going high to power available at RF output, Including TX IF filter group delay. † Including contributions from LO1, LO2, and modulator.
W3020 GSM Multiband RF Transceiver December 1999 16 Lucent Technologies Inc. Modulator (continued) IL = 3 dB REJECTION = 34 dB @ 20 MHz OFFSET OUTPUTΦ I Q LO1 LO2 ÷ 2 ÷ 3 Figure 6 . IF Filtering Requirements for Wideband Noise Performance
December 1999 W3020 GSM Multiband RF Transceiver Lucent Technologies Inc. 17 LO2 Specification The W3020 contains an input buffer for an external VCO and a PLL for generation of a second LO signal at 540 MHz. The output of the buffer is fed to the receive and transmit circuits, where the signal is divided to the IF frequency. The phase noise includes contributions from VCO buffers to the transmit and receive circuits. Table 9 . LO2 Performance V DD = 2.7 V; T A = 25 °C ± 3 °C. Parameter Min Typ Max Unit Charge Pump Supply (V DD C2) 2.7 2.85 3.0 V Frequency — 540 — MHz LO2 Input Level –6 –3 0 dBm Clock Reference Frequency — 13.0 — MHz Clock Input Level 0.4 1 — Vp-p Reference Frequency (at phase detector) — 1.0 — MHz Phase Accuracy (loop bandwidth 10 kHz) — 1.3 — °rms Phase Detector Gain (V DD = 2.85 V) — 200 — µA/cycle Powerdown Charge Pump Supply Current (V DD C2) — — 1 mA Phase Detector Voltage 0.5 1.3 V DD C2 – 0.5 V Note: Reference sidebands determined by external loop filter components. LO1 Input Buffer Specification Table 10 . LO1 Performance V DD = 2.7 V; T A = 25 °C ± 3 °C. Parameter Min Typ Max Unit Frequency Range: GSM900 1150 — 1230 MHz GSM1800 1530 — 1610 MHz GSM1900 1660 — 1730 MHz Input Power Level –6 –3 — dBm Input Noise Figure — 8 10 dB
W3020 GSM Multiband RF Transceiver December 1999 18 Lucent Technologies Inc. Programming Information The W3020 and W3000 transceiver mode (IC RX/TX) and the gain and band settings are programmed using a standard three-wire bus (CLOCK, DATA, LATCH). The W3020 and W3000 registers are addressable so the two ICs can share the same data, clock, and latch times. The LATCH line initiates download and execution of the current DATA word. W3000 W3020 TR REGISTER CONFIG REGISTER MAIN REGISTER REF REGISTER MAIN REGISTER SC1 PARALLEL LATCH SERLE1 SERCK SERDA SERIAL SHIFT ADDRESS DECODER ADDRESS DECODER PARALLEL LATCH A[0:2] CLK DAT SERIAL SHIFT A[0:2] LAT DAT CLK LAT Figure 7 . Diagram of W3020, W3000, and SC1 Interconnection
December 1999 W3020 GSM Multiband RF Transceiver Lucent Technologies Inc. 19 Programming Information (continued) Serial Bus Timing Information tCS tCH tLWH tLS V MSB LSBMSB – 1 DAT CLK t L L tCWHtCWL LAT OR LAT t Figure 8 . Serial Bus Timing Diagram Table 11 . Serial Bus Timing Information V DD = 2.7 V; T A = 25 °C ± 3 °C Symbol Parameter Min Typ Max Unit T CS Data to Clock Setup Time 33 — — ns T CH Data to Clock Hold Time 10 — — ns T CWH Clock Pulse Width High 33 — — ns T CWL Clock Pulse Width Low 33 — — ns T LS Clock Falling Edge to Latch High Setup Time 0 — — ns T LWH Latch Pulse Width 50 — — ns T LL Latch to Clock Setup Time 33 — — ns F CLK Clock Input Frequency — — 10 MHz
W3020 GSM Multiband RF Transceiver December 1999 20 Lucent Technologies Inc. Programming Information (continued) The Data Word The W3020 and W3000 chips are addressed through the bit content of the 24-bit serial word. Some words for time-critical interactions address both W3020 and W3000 at the same time, while some words for initialization address W3020 and W3000 separately. The W3020 gets all of its control information via a three-wire serial bus from the baseband IC. Serial data transfers always consist of 24 bits: 3 bits of address to select one of five control registers, and up to 21 bits of data. The data is shifted first into a shift register and then parallel-loaded into the proper control register after the completion of the transfer when the latch enable signal goes high. The last bit is that which immediately precedes a low-to-high latch input transition occurring while the CLOCK input is low. Bit 24 is loaded first, and bit 1 is loaded last. The four control registers are defined as follows: n TR: Transmit/receive register for W3020. Contains bits for setting various transmit and receive modes, setting receive gain, etc. It is expected that this register would be written several times during a frame. n CONFIG: Contains bits to control various options for dc offset correction, filter-tuning, lock detect, and overload outputs, etc. It is expected that this register would be written once at initialization and then rarely updated. Since it is not affected by the power-on reset circuit, a write to this register should be the first operation performed when accessing the W3020 chip. Also, it is advisable never to update the configuration register while a critical operation is in progress. n MAIN: Main counter and prescaler values for W3000 chip. Used to set mode and band bit functions for the W3020 while programming the W3000. n REF: Reference counter values for W3000. Not relevant to W3020. Table 12 . Register Addressing A2 A1 A0 Register Device 1 0 0 TR W3020 1 0 1 CONFIG W3020 1 1 0 RESERVED W3020 1 1 1 RESERVED W3020
0 X 0 M MAIN W3000
0 X 1 M REF W3000
Note: X indicates that the bit does not affect addressing for the given combination of A2 and A0 that addresses the W3000. In the W3000, the A1 bit is used for data content.
December 1999 W3020 GSM Multiband RF Transceiver Lucent Technologies Inc. 21 Programming Information (continued) TR Register The TR register is the transmit/receive register for W3020. It contains bits for setting various transmit and receive modes, setting receive gain, etc. It is expected that this register would be written several times during a frame. Last bit in serial sequence First bit in serial sequence Bit No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Bit A0=0 A1=0 G0 G1 G2 G3 G4 G5 G6 T0 T1 T2 DS DP FTR T3 T4 T5 T6 MO1 MO2 MO3 B A2=1 Table 13 . TR Register Bit Number Bit SC1 Standard Setting Function
24 A2 1 Address Bit
23 B 0 Band Select (See Table 14 .) MO3 MO2 MO1 — RX, TX, Synthesizer Mode (See Table 15 .) 19 T6 0 Disable LO2 Circuitry in All Modes (See Table 16 .) 18 T5 0 Disable LO1 Circuitry (W3000 excluded) (See Table 17 .) 17 T4 0 RX IF Duty Cycle Corrector Disable (See Table 18 .)
16 T3 0 GSM1800 TX IF LO Divide-by-3 Duty Cycle Corrector Disable (See
Table 19 .) 15 FTR 1 LPF Tune Filter Request (See Table 20 .) 14 DP 0 dc Precharge Only (See Table 21 .) 13 DS 0 dc Correction Skip (See Table 22 .) 12 T2 0 LO2 Divide by 2 or Divide-by-3 Select for TX IF (See Table 23 .) 11 T1 0 TX IF LO Divide-by-6 Select (See Table 24 .) 10 T0 0 TX IF Duty-Cycle Corrector Disable (See Table 25 .) — Digital Gain Control RX IF/IQ-Baseband (See Table 26 .) 3 G0 1 Digital Gain Control LNA On/Off (See Table 26 .) Address Bits Note: The TR register is reset to an all-zero state after the reset bit in the CONFIG register has been set high.
- Note that bits T2 and T1 also affect the transmitter
0 GSM900 Path On
1 GSM1800/1900 Path On
updates it in W3000, and vice versa. Table 15. The corresponding typical supply current for the I/Q modulator and up-conversion mixer. CONFIG register (see Table 38 ). mentioned above for the receive burst.
December 1999 W3020 GSM Multiband RF Transceiver Lucent Technologies Inc. 23 Programming Information (continued) TR Register (continued) Table 15 . MO[3:1]: Mode Control MO3 MO2 MO1 Function Bit 22 Bit 21 Bit 20 0 0 0 Sleep: All Modules Powerdown 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 TX PLL Settling Mode (LO1, LO2, TX LO1, and TX LO2 buffers on) 1 0 1 RX PLL Settling Mode (LO1, LO2, RX LO1, and RX LO2 buffers on) 1 1 0 TX ON (TX modulator and mixer, LO1, LO2, TX LO1, and TX LO2 buffers on) 1 1 1 RX ON (RX mixer; LNA, if enabled; IF amplifier; LO1; LO2; RX LO1; and RX LO2 buffers on)* *If MO bits are set to 111 with the dc correction skip bit low, a dc offset calibration cycle is performed automatically. Table 16 . T6: LO2 Disable If this bit is set high, the 540 MHz LO2 input buffer and LO2 PLL will be turned off. This bit will also disable the 13 MHz clock buffer going to the baseband amplifier correction circuits. This bit is provided for testing purposes. Bit 19 Function
0 LO2 Circuit Enabled
1 LO2 Circuit Disabled
Table 17 . T5: LO1 Disable The T5 bit disables the LO1 circuitry including the UHF LO1 buffer and bias circuit. This bit is provided for testing purposes. Bit 18 Function
0 LO1 Circuitry Enabled
1 LO1 Circuitry Disabled
Table 18 . T4: Receive IF Duty Cycle Corrector Disable When high, disables duty cycle correction circuit in the LO2 divide-by-2 circuit for the receive IF demodulator. This is provided for testing purposes. Bit 17 Function
0 Divide-by-2 Duty Cycle Corrector Enabled
1 Divide-by-2 Duty Cycle Corrector Disabled
Table 19 . T3: Divide-by-3 Duty Cycle Corrector Disable When high, disables duty cycle correction circuit in the GSM1800/1900 transmit IF LO divide-by-3 circuit. This is provided for testing purposes. Bit 16 Function
0 Divide-by-3 Duty Cycle Corrector Enabled
1 Divide-by-3 Duty Cycle Corrector Disabled
W3020 GSM Multiband RF Transceiver December 1999 24 Lucent Technologies Inc. Programming Information (continued) TR Register (continued) Table 20 . FTR: LPF Tune Filter Request This requests tuning operation of baseband low-pass filter (see the Low-Pass Filter Tuning section for details). If the filter tune is enabled in CONFIG register, the FTR bit must be programmed high before the first following receive mode is active. Filter tune can only be done in a mode where LO2 is active, e.g., receive mode. FTR Bit 15 Function
0 Use Default Tuning Value
1 Perform New Tuning
Table 21 . DP: dc Precharge Only When dc offset calibration is performed, only the precharge portion is done. This reduces the amount of time required for dc offset calibration, but gives higher levels of dc offset. (See the dc Offset Calibration section for details.) DP Bit 14 Function
0 Standard dc Offset Correction Cycle
Table 22 . DS: dc Correction Skip DS Bit 13 Function
0 Insert dc Correction Cycle (See Table
41 .)
1 Skip dc Offset Calibration (with retained
dc correction setting) Table 23 . T2: TX IF LO Division Select Switch Reverses the LO2 frequency division factor in the transmitter for both bands. This is provided for testing purposes. This bit works with the band bit B as follows. Bit 12 B Bit 23 Function 0 0 Divide by 2 (270 MHz): Normal GSM900 Division 0 1 Divide by 3 (180 MHz): Normal GSM1800/1900 Division 1 0 Divide by 3 (180 MHz): Reversed Band 0 Division 1 1 Divide by 2 (270 MHz): Reversed Band 1 Division Table 24 . T1: TX IF LO Divide-by-6 Select This bit will change the divide-by-3 circuit to a divide- by-6 circuit. This bit is provided for testing purposes. Bit 11 Function
0 Divide by 3 when 1/3 Path Is Active
1 Divide by 6 when 1/3 Path Is Active
Table 25 . T0: TX IF Duty Cycle Corrector Disable When high, disables duty cycle correction circuit into the transmit IF phase splitter. This bit is provided for testing purposes. Bit 10 Function
0 TX IF LO Duty Cycle Corrector Enabled
1 TX IF LO Duty Cycle Corrector Disabled
December 1999 W3020 GSM Multiband RF Transceiver Lucent Technologies Inc. 25 Programming Information (continued) TR Register (continued) Table 26 . G[0:6]: Digital Gain Control Digital RX gain control with bits defined as follows: G0: When high, enables GSM900 or GSM1800/1900 LNA according to which band is selected by band bit B. (See Table 14 .) G4: IF gain: 0 = 0 dB, 1 = 32 dB. G1: 0 = add 0 dB to baseband gain, 1 = add 4 dB to baseband gain in second amplifier. G2: 0 = add 0 dB to baseband gain, 1 = add 8 dB to baseband gain in first amplifier. G3: 0 = add 0 dB to baseband gain, 1 = add 16 dB to baseband gain in first amplifier. G5: 0 = add 0 dB to baseband gain, 1 = add 21 dB to baseband gain in second amplifier. G6: 0 = add 0 dB to baseband gain, 1 = add 4 dB to baseband gain in first amplifier. The nominal demodulator mixer conversion gain is 4 dB; hence, total gain is always 4 dB higher than the DGC setting . Voltage gain is differential assuming input matching network to 50 Ω source impedance. (See Table 6 .) G6 G5 G4 G3 G2 G1 DGC Gain Total Gain Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 (dB) (dB) 0 0 0 0 0 0 0 4 1 0 0 0 0 0 4 8 0 0 0 0 1 0 8 12 1 0 0 0 1 0 12 16 0 0 0 1 0 0 16 20 1 0 0 1 0 0 20 24 0 0 0 1 1 0 24 28 1 0 0 1 1 0 28 32 0 0 1 0 0 0 32 36 1 0 1 0 0 0 36 40 0 0 1 0 1 0 40 44 1 0 1 0 1 0 44 48 0 0 1 1 0 0 48 52 1 0 1 1 0 0 52 56 0 0 1 1 1 0 56 60 1 0 1 1 1 0 60 64 1 0 1 1 1 1 64 68 0 1 0 0 0 0 21 25* 1 1 1 1 1 0 81 85* 1 1 1 1 1 1 85 89* * Not tested or recommended for use. 32/0 6 16/0 8/0 4/0 21/0 4/0 G4 G3 G2 G6* G5* G1LPF1 LPF2 *Not tested. Figure 9 . IF and I/Q Gain Distribution (dB)
W3020 GSM Multiband RF Transceiver December 1999 26 Lucent Technologies Inc. Programming Information (continued) CONFIG Register The CONFIG register contains bits to control various options for dc offset correction, filter-tuning, lock detect, and overload outputs, etc. It is expected that this register would be written once at initialization and then rarely updated. Since it is not affected by the power-on reset circuit, a write to this register should be the first operation performed when accessing the W3020 chip. Also, it is advisable never to update the configuration register while a critical operation is in progress. Last bit in serial sequence First bit in serial sequence Bit No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Bit A0=1 A1=0 RS DT0 DT1 DT2 C1 C2 C3 C4 C5 C6 C7 LD2 C8 VO C9 OLD C10 F1 F2 F3 F4 A2=1 Table 27 . CONFIG Register Bit No. Bit SC1 Standard Setting Function
24 A2 1 Address Bit 2
19 C10 1 Enable of LO2 PLL (See Table 28 .) 18 OLD 0 Disable of Overload Pin Output Signal, When High (See Table 29 .)
17 C9 0 Force RF Mixer On When RX LO1 Buffer Is On, When High (See
Table 30 .) 16 VO 1 Reserved; Always High (See Table 31 .)
15 C8 0 LO2 Charge Pump Output Off (high impedance), When High (See
Table 32 .) 14 LD2 1 Enable LO2 Lock Detect Output, When High (See Table 33 .) 13 C7 0 Select dc Offset Correction/Fine Tune, When High (See Table 34 .)
12 C6 0 Disable LP Filter Bandwidth Tune and Use Default Value, When High
(See Table 35 .)
11 C5 0 Disable dc Offset Correction and Use Default Setting, When High (See
Table 36 .) 10 C4 1 High Bandwidth Setting of Baseband Path, When High (See Table 37 .) 9 C3 0 RX LO1 Buffer On During dc Calibration When High (See Table 38 .) 8 C2 0 LNA On During dc Calibration, When High (See Table 39 .)
7 C1 1 LO2 Phase Detector Polarity, Positive Slope, When High (See
Table 40 .) DT[2] DT[1] DT[0] dc Offset Correction Time (See Table 41 .) 3 RS 1* Resets Bit Content in Other Registers, When High (See Table 42 .)
2 A1 0 Address Bit 1
1 A0 1 Address Bit 0
- It is recommended that a reset be progr ammed after power-on. Reset does not affect the content of the CONFIG register.
December 1999 W3020 GSM Multiband RF Transceiver Lucent Technologies Inc. 27 Programming Information (continued ) CONFIG Register (continued) Table 28 . C10: LO2 PLL Enable When low, disables counters, phase detector, and charge pump of the LO2 PLL. This mode is provided for applications utilizing an external programmable IF PLL. C10 Bit 19 Function
0 LO2 PLL Disabled
1 LO2 PLL Operational (normal)
Table 29 . OLD: Overload Output Disable When high, forces overload output pin to be a logic low level. Otherwise, overload pin indicates overload. OLD Bit 18 Function
0 Overload Detect Output for IF/Baseband Enabled
1 Overload Detect Output for IF/Baseband Disabled
Table 30 . C9: RF Mixer On During Settling When high, enables receive RF mixer during receive PLL settling mode. In default operation, this bit should be set to 0. If there were a problem with the VCO kicking when going from settling mode to full receive mode, it could be set high. Bit 17 Function
0 Default: RX Mixer Off During RX Settling Mode (MO[3:1] = 101)
1 RX Mixer On During RX Settling Mode (MO[3:1] = 101)
Table 31 . VO: LO1 Buffer Mode VO Bit 16 Function
0 Not Allowed
1 LO1 Buffer Mode
Table 32 . C8: LO2 Charge Pump Off Bit 15 Function
0 Normal LO2 Charge Pump Operation
1 Charge Pump Off (high impedance) or CP2 Test Mode
W3020 GSM Multiband RF Transceiver December 1999 28 Lucent Technologies Inc. Programming Information (continued ) CONFIG Register (continued) Table 33 . LD2: Lock Detect Enable LD2 Bit 14 Function
0 Lock Detect Output for LO2 Disabled
1 Lock Detect Output for LO2 Enabled
Note: When disabled, the lock detect output is a logic level high. When lock detect is enabled but 540 MHz PLL is not locked, LD output is pulsing low. When lock detect is enabled and 540 MHz PLL is locked, LD output is high. Table 34 . C7: dc Coarse/Fine Correction When this bit is low, coarse offset calibration is done such that the SC1's offset calibration can be done simultaneously. When this bit is high, a fine calibration is done, but this is not compatible with the SC1. Bit 13 Function
0 Coarse dc Correction Tuning (for interface with baseband with calibration function) with Output
Buffer dc Connection Retained
1 Fine Tune (no baseband calibration required), No Output Available During Calibration
Table 35 . C6: Filter Tune Disable Disable LP filter bandwidth tune and use default value. Bit 12 Bandwidth Setting Function
0 Use Calibration Requires LPF Tune Request Cycle to Be Executed
1 Use Default Always Use Default Noncorrected Value (less accurate)
Table 36 . C5: dc Correction Disable Bit 11 Function
0 Correction Cycle Before Each RX
1 Always Use Default Noncorrected Value
Table 37 . C4: Low-Pass Filter Bandwidth Bit 10 Function
0 Low Bandwidth (115 kHz)*
1 High Bandwidth (168 kHz) for Use with SC1, etc. * Not tested or recommended for use.
December 1999 W3020 GSM Multiband RF Transceiver Lucent Technologies Inc. 29 Programming Information (continued ) CONFIG Register (continued) Table 38 . C3: Receive LO1 Buffer Mode During dc Calibration Bit 9 Function
0 RX LO1 Buffer Off During dc Offset Calibration
1 RX LO1 Buffer On During dc Offset Calibration
Table 39 . C2: LNA Mode During dc Calibration Bit 8 Function
0 LNA Off During dc Offset Calibration*
1 LNA On During dc Offset Calibration
*Recommended to meet GSM sensitivity requirement. Table 40 . C1: 540 MHz LO2 Phase Detector Polarity Bit 7 Function (See Figure 10 .)
0 Negative Charge Pump Polarity (VCO2 Frequency Decrease with CP2 Voltage)
1 Positive Charge Pump Polarity (VCO2 Frequency Increase with CP2 Voltage)
C1 STATE = 1 C1 STATE = 0 VCO INPUT CONTROL VOLTAGE Figure 10 . Programming the LO2 Phase Detector Slope
W3020 GSM Multiband RF Transceiver December 1999 30 Lucent Technologies Inc. Programming Information (continued ) CONFIG Register (continued) Table 41 . DT[2:0]: dc Correction Time Total dc offset calibration time is determined according to the table below. For further information, see the discussion in the dc Offset Calibration section. DT[2] Bit 6 DT[1] Bit 5 DT[0] Bit 4 T (RX_Valid) (µs) 0 0 0 72 0 0 1 131 0 1 0 190 0 1 1 249 1 0 0 309 1 0 1 368 1 1 0 427 1 1 1 486 X X X 42 (DP = 1)* * See Table 21 . Table 42 . RS: Reset Bit Content When set high, all registers except for the CONFIG register are reset to 0. When set low, no action occurs. RS Bit 3 Function
0 No Function
1 Reset Other Registers One Time
Last bit in serial sequence First bit in serial sequence Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Bit No. A0=0 x x x x x x x x x x x x x x x x x x MO1 MO2 MO3 B A2=0 Note: Bits designated x do not apply to W3020. Programming the MAIN register affects the states of both the W3000 and the W3020. The MO bits (see Table 15 ) and band bit B (see Table 14 ) have the same functions as described in the TR Register section. The W3020 state is determined by the most recent programming event to either the MAIN register or the TR register.
December 1999 W3020 GSM Multiband RF Transceiver Lucent Technologies Inc. 31 Programming Information (continued ) Filter Tune and dc Offset Correction Timing Low-Pass Filter Tuning The W3020 has an internal calibration to improve the accuracy of the low-pass filter bandwidth. The filter tune operation should be performed each time supply voltage is applied to the device and after restart. The low-pass filter tuning operation is controlled by 3 bits in the control logic: n FTR: filter tune request, in the TR register n C4: low-pass filter bandwidth, in the CONFIG register n C6: filter tune disable, in the CONFIG register If the filter tune disable bit (C6) is programmed high, the filter bandwidth is set to the programmed (nominal) value (see Table 35 ), and any request for filter tuning from the FTR bit is ignored. The accuracy of the filter bandwidth can be improved by performing a filter tune calibration. A filter tune can be performed by setting the filter tune request (FTR) bit in the TR register high and the filter tune disable bit (C6) in the CONFIG register low. This enables a 13/4 MHz (3.25 MHz) clock to the filter tuning state machine, which then runs until the tuning is complete and the new filter tune values are stored. The filter tune operation itself takes 16.5 cycles of the 3.25 MHz clock, or 5.1 µs. The filter tune operation should be done in receive mode. The receive mode needs to be held active for at least 20 µs to allow for bias start-up. The dc offset calibration, if requested, is performed after the filter tune is complete. The filter tune operation adds 5.1 µs to the total calibration time when requested at the same time as a dc offset calibration. If a filter tune is requested while the MOD bits are not set to 111, only the receive bias circuitry is turned on; the rest of the receive channel remains powered down.
W3020 GSM Multiband RF Transceiver December 1999 32 Lucent Technologies Inc. Programming Information (continued ) Filter Tune and dc Offset Correction Timing (continued) dc Offset Calibration The dc offset calibration operation is controlled by several bits in the CONFIG and TR registers: n DS: dc correction skip, in the TR register n DP: dc precharge only, in the TR register n C5: dc correction disable, in the CONFIG register n C7: dc coarse/fine correction, in the CONFIG register n DT: dc correction time, in the CONFIG register When the dc correction disable bit (C5) in the CONFIG register is written high, the dc offset correction circuitry charges to a default value, corresponding to 0 dc offset, and any request for dc offset calibration is ignored. If dc correction disable = 0, the dc offset calibration is initiated by writing the MO bits in the TR (or MAIN) register to a value of 111 while dc correction skip (DS) and dc precharge only (DP) are both low. As in the case of the filter tune, start of dc offset calibration is held off for about 15 µs while the bias circuits and input clock buffer start-up. If the FTR bit was also written high coincident with entering RX mode, a filter tune is performed first, after which dc offset calibration begins automatically. The dc offset calibration runs for a time determined by the dc offset correction time bits DT[0:2] in the CONFIG register. There are three of these bits, giving the user a choice of eight different correction times. Upon completion of the dc offset calibration, the 3.25 MHz baseband clock stops and full receive mode is entered automatically, with the LO1 buffer and LNA (if G0 = 1) being enabled automatically. If RX mode is entered with dc precharge only (DP = 1) set high, dc offset circuitry runs through a much shorter calibration routine, after which normal receive mode is entered automatically. The precharge-only operation functions much the same as the normal calibration operation in that the LO1 buffer and LNA is disabled until completion of the precharge operation. The 15 µs bias start-up time is still incurred. The receive circuitry conditions during dc calibration are also controlled by two other bits in the CONFIG register: n C2: LNA on during dc calibration, when high n C3: receive LO1 buffer on during dc, calibration when high For both the standard dc offset calibration cycle and the dc precharge-only operation, it is possible to perform dc offset calibration with the LNA and/or LO1 buffer on by setting the C2 and C3 bits in the CONFIG register.
December 1999 W3020 GSM Multiband RF Transceiver Lucent Technologies Inc. 33 Programming Example This programming example shows how the W3020 can be programmed after power-on and how it can be programmed prior to receive and transmit bursts. The reference register for the W3000 is initialized separately with the reference divider ratio, as described in the W3000 data sheet. Table 43 . Initialize CONFIG Register (Reset W3020) To reset all registers to their default state and put the device into a low-power sleep mode, one write to the CONFIG register is necessary. This will also reset W3000 if it is connected on the same three-wire bus. Normally, the device will be both reset and configured in the same programming as follows: CONFIG register: reset device, set dc calibration time to max value (486 µs), set phase detector polarity for the positive slope VCO, use high BW and coarse dc offset tune. Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Bit No. A0 A1 RS DT0 DT1 DT2 C1 C2 C3 C4 C5 C6 C7 LD2 C8 VO C9 OLD C10 F1 F2 F3 F4 A2 Setting 1 0 1 1 1 1 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 Note: Hex value = 84827d. Table 44 . Initialize TR Register The reset operation will set the TR register to the following content: Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Bit No. A0 A1=0 G0 G1 G2 G3 G4 G5 G6 T0 T1 T2 DS DP FTR T3 T4 T5 T6 MO1 MO2 MO3 B A2 Setting 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Note: Hex value = 800000. A filter tune request with this TR content, setting FTR = 1 and MO[1:3] = 111, could be done as a second initialize followed by a third programming that powers the IC in idle mode. Table 45 . Settle PLL to GSM1800 Band for Receive Mode (W3020/W3000) Main register: switch to W3020 receive settling mode to allow LO2 to settle; band bit B = 1 for GSM1800. (W3000 is programmed at the same time to settle LO1 to 1572 MHz frequency with N = 7860 to receive at 1842 MHz.) Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Bit No. A0=0 A1 A2 A3 A4 A5 A6 A7 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 MO1 MO2 MO3/EN B A1=0 Setting 0 0 0 1 0 1 1 0 0 1 0 1 1 1 1 0 0 0 0 1 0 1 1 0 Notes: Hex value = 687A68. Italics indicate W3000 bits.
W3020 GSM Multiband RF Transceiver December 1999 34 Lucent Technologies Inc. Programming Example (continued) Table 46 . Perform Receive (W3020) TR register: full receive mode; set DGC gain to 60 dB gain setting with LNA on (G0 = 1) and with normal dc offset calibration; band bit B = 1. Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Bit No. A0 A1 G0 G1 G2 G3 G4 G5 G6 T0 T1 T2 DS DP FTR T3 T4 T5 T6 MO1 MO2 MO3 B A2 Setting 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 Note: Hex value = f8407C. To change gain settings and remain in receive mode without redoing dc offset calibration, repeat the bus transaction above with dc skip bit high (DS = 1). It should be noted that as dc offset is gain-dependent, dc skip mode can be used only for receive signal levels where dc offset is insignificant. Table 47 . Settle PLL in GSM1800 Band for Transmit Mode (W3020/W3000) MAIN register: switch W3020 to transmit settling mode to allow LO2 to settle; band bit B = 1. (W3000 is programmed at the same time to settle LO1 to 1567 MHz frequency with N = 7835 to transmit at 1747 MHz.) Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Bit No. A0 A1 A2 A3 A4 A5 A6 A7 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 MO1 MO2 MO3/EN B A1 Setting 0 1 1 0 1 1 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 1 1 0 Notes: Hex value = 607A36. Italics indicate W3000 bits. Table 48 . Basic GSM1800 Transmit Burst (W3020) TR register: full transmit mode; band bit B = 1. Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Bit No. A0 A1=0 G0 G1 G2 G3 G4 G5 G6 T0 T1 T2 DS DP FTR T3 T4 T5 T6 MO1 MO2 MO3 B A2 Setting 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Note: Hex value = f00000. To change to the GSM900 MHz band for the example above, band bit B must be changed to B = 0 and the appropriate channel programming must be set up for the W3000 synthesizer.
December 1999 W3020 GSM Multiband RF Transceiver Lucent Technologies Inc. 35
Application Information
V CC = 3.0 Vdc; T A = 25 °C ± 3 °C. 0.0 –0.2 inf 5.0 2.0 1.0 –0.5 –2.0 –5.0 0.2 0.5 1.95 dB 2.2 dB 2.7 dB –1.0 NF = 1.7 dB Figure 11 . GSM900 Smith Chart Noise Circles
W3020 GSM Multiband RF Transceiver December 1999 36 Lucent Technologies Inc. Application Information (continued) S-Parameters (continued) V CC = 3.0 Vdc; T A = 25 °C ± 3 °C. 0.0 –0.2 inf 5.0 2.0 1.0 –0.5 –2.0 –5.0 0.2 0.5 –1.0 NF = 2.2 dB 3.2 2.7 2.45 Figure 12 . GSM1800 Smith Chart Noise Circles
December 1999 W3020 GSM Multiband RF Transceiver Lucent Technologies Inc. 37 Application Information (continued) S-Parameters (continued) Table 49 . GSM900 LNA S-Parameters V CC = 3.0 Vdc; T A = 25 °C ± 3 °C. Frequency (MHz) S11 M S11 A ( °°) S21 M S21 A ( °°) S12 M S12 A ( °°) S22 M S22 A ( °°)
W3020 GSM Multiband RF Transceiver December 1999 38 Lucent Technologies Inc. Application Information (continued) S-Parameters (continued) Table 50 . GSM1800/GSM1900 LNA S-Parameters V CC = 3.0 Vdc; T A = 25 °C ± 3 °C. Frequency (MHz) S11 M S11 A ( °°) S21 M S21 A ( °°) S12 M S12 A ( °°) S22 M S22 A ( °°)
December 1999 W3020 GSM Multiband RF Transceiver Lucent Technologies Inc. 39 Application Information (continued) S-Parameters (continued) Table 51 . Receive IF Amplifier Input (0 dB Setting) Port 1 = IFIN (pin 34). Port 2 = IFIP (pin 35). Frequency (MHz) S11 M S11 A (º) S21 M S21 A (º) S12 M S12 A (º) S22 M S22 A (º) Table 52 . Receive IF Amplifier Input (32 dB Setting) Port 1 = IFIN (pin 34). Port 2 = IFIP (pin 35). Frequency (MHz) S11 M S11 A (º) S21 M S21 A (º) S12 M S12 A (º) S22 M S22 A (º)
W3020 GSM Multiband RF Transceiver December 1999 40 Lucent Technologies Inc. Application Information (continued) S-Parameters (continued) Table 53 . Transmit Modulator IF Output Port 1 = TIFON (pin 52). Port 2 = TIFOP (pin 53). Frequency (MHz) S11 M S11 A (º) S21 M S21 A (º) S12 M S12 A (º) S22 M S22 A (º)
December 1999 W3020 GSM Multiband RF Transceiver Lucent Technologies Inc. 41 Application Information (continued) S-Parameters (continued) Table 54 . Transmit IF Input to Up-Conversion Mixer Port 1 = TIFIP (pin 5). Port 2 = TIFIN (pin 6). Frequency (MHz) S11 M S11 A (º) S21 M S21 A (º) S12 M S12 A (º) S22 M S22 A (º)
W3020 GSM Multiband RF Transceiver December 1999 42 Lucent Technologies Inc. Application Information (continued) S-Parameters (continued) Table 55 . Transmit RF Output from Up-Conversion Mixer Port 1 = TOV (pin 60). Port 2 = TOUT (pin 59). Frequency (MHz) S11 M S11 A (º) S21 M S21 A (º) S12 M S12 A (º) S22 M S22 A (º)
December 1999 W3020 GSM Multiband RF Transceiver Lucent Technologies Inc. 43 Outline Diagram 64-Pin TQFPT Dimensions are in millimeters. DE TAIL A 0.5 0 T YP 1.2 0 MA X SE AT ING PLAN E 0.08 DETA IL B 0.05/ 0.15 1.00 ± 0 .05 10.00 ± 0 .20 12.00 ± 0 .20 64 49 17 32 10.00 ± 0. 20 12.00 ± 0. 20 PIN #1 IDENTIFIER ZON E DET AIL B 0.17/ 0.27 0.08 M 0.09/ 0.20 DE TA IL A 0.45/ 0.75 GA GE PLANE SE ATING PLANE 1.0 0 REF 0.25 5-3080.a
W3020 GSM Multiband RF Transceiver December 1 999 For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447 , FAX 610-712-4106 (In CANADA: 1-800-553-2448 , FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies S ingapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833 , FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P.R. China Tel. (86) 21 6440 0468, ext. 316 , FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600 , FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368 , FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: ( 34) 1 807 1441 (Madrid) Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright © 1999 Lucent Technologies Inc. All Rights Reserved Printed in U.S.A. December 1999 DS98-070WTEC Manufacturing Information This device will be assembled in one of the following locations: assembly codes K or M. Evaluation Board Note The EVB3020A Evaluation Board is available for customer demonstration (see Ordering Information) of device performance characteristics. The board allows full characterization with RF laboratory bench equipment. Various applications of the device can be demonstrated on the evaluation board.
Ordering Information
Device Code Description Package Comcode LUCW3020CCS GSM Transceiver 64TQFPT Bulk 108417734 LUCW3020CCS-DB 64TQFPT Dry Pack 108417742 EVB3020A Evaluation Board Evaluation Board 108100611 EVB3020A-IFBD Interface Board Interface Kit 108100629 Note: Contact your Lucent Technologies Microelectronics Group Account Manager for minimum order requirements.