TMPR28051

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August 5, 1999 TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 5 of the Device Register Architecture (RA) Map RA-1. Reset Bit The software reset bit (bit 0) of register 0x00 is not functional. RA-2. Transmit Path AIS Insert Bit The TXPAISINS bit (bit 5) of register 0x01 produces both AIS-P and AIS-L. RA-3. STS-1 Loss of Pointer Mask Bit The STS1LOPMSK bit (bit 2) of register 0x04 masks both STS1LOP and STS1LOF. RA-4. STS-1 Loss of Frame Mask Bit The STS1LOFMSK bit (bit 1) of register 0x04 is not functional. RA-5. VTLABCOM and VTRFIRDICOM Interrupt Bits Occasionally, it might require multiple reads to clear the composite interrupt bits VTLABCOM (bit 2 of register 0x05) and VTRFIRDICOM (bit 4 of register 0x05). Error Insertion (EI) EI-1. DS1/E1 Alarm Indication Signal The device does not insert DS1/E1 AIS towards the STS-1 if there is an LOC condition in the incoming DS1/E1 signal. EI-2. LOC Condition in E1 Loopback Mode In the absence of an input clock, the device detects an LOC condition and generates TU-AIS upstream, even if the loopback path is selected (the loopback signal is overwritten by TU-AIS).

Lucent T echnologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright © 1999 Lucent T echnologies Inc. All Rights Reserved August 5, 1999 AY99-025SONT (Must accompany DS99-068SONT) For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, P A 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA P ACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent T echnologies (China) Co., Ltd., A-F2, 23/F , Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P . R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAP AN: Microelectronics Group, Lucent T echnologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, T okyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DA T ALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 T echnical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), IT AL Y: (39) 02 6608131 (Milan), SP AIN: (34) 1 807 1441 (Madrid) TMPR28051 STS-1/AU-3 (STM-0 ) Mapper Advisor y Device Advisory for Version 5 of the Device Au gust 5, 1999 Error Insertion (EI) (continued) EI-3. False S-BIP , L-BIP, and P-BIP Error Insertion The device transmits S-BIP, L-BIP, and P-BIP errors when configured for automatic insertion of REI, and certain STS-1 error conditions such as LOS, LOF, LOP-P, S-BIP, L-BIP, and P-BIP are inserted. VT Alarms (VT ) VT-1. VT Path Payload Label Mismatch The device reports PLM-V when it detects three consecutive consistent new values for the VT label. This is in com- VT-2. Failure in the Detection of VT Loss of Pointer Defects The device also apparently fails to detect an LOP-V defect when it continuously receives a VT pointer word of 6C68 (i.e., a value indicating a VT1.5 with an offset of 104 bytes, versus a maximum valid offset of 103 bytes). In this case, the device inserts the required DS1 AIS downstream, but does not subsequently declare an LOP-V fail- ure (nonconformance to GR 253, R6-71). VT-3. Inappropriate Termination of VT Loss of Pointer Defect Condition After the device has detected an LOP-V defect, it inappropriately terminates that defect upon receiving two pointer words containing the same value as the previous valid pointer. According to GR 253, an LOP-V defect must not be terminated unless a valid pointer is received in three consecutive VT superframes (nonconformance to GR 253, R6-75). VT-4. Inappropriate Termination of VT Alarm Indication Signal Defect Condition After the device has detected an AIS-V defect, it inappropriately terminates that defect upon receiving two pointer words containing the same value as the previous valid pointer and without a set NDF (e.g., with the N bits set to 0110). According to GR 253, an AIS-V defect must not be terminated unless a normal valid pointer is received in three consecutive VT superframes, or a valid pointer with a set NDF is received in one VT superframe (nonconfor- mance to GR 253, R6-183).

TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 2 of the Device Advisory, Rev. 2 August 5, 1999 Re gister Architecture (RA ) Map RA-1. Reset Bit The software reset bit (bit 0) of register 0x00 is not functional. RA-2. Transmit Path AIS Insert Bit The TXPAISINS bit (bit 5) of register 0x01 produces both AIS-P and AIS-L. RA-3. STS-1 Loss of Pointer Mask Bit The STS1LOPMSK bit (bit 2) of register 0x04 masks both STS1LOP and STS1LOF. RA-4. STS-1 Loss of Frame Mask Bit The STS1LOFMSK bit (bit 1) of register 0x04 is not functional. RA-5. VTLABCOM and VTRFIRDICOM Interru pt Bits Occasionally, it might require multiple reads to clear the composite interrupt bits VTLABCOM (bit 2 of register 0x05) and VTRFIRDICOM (bit 4 of register 0x05). Error Insertion (EI) EI-1. DS1/E1 Alarm Indication Signal The device does not insert DS1/E1 AIS towards the STS-1 if there is an LOC condition in the incoming DS1/E1 signal. EI-2. LOC Condition in E1 Loopback Mode In the absence of an input clock, the device detects an LOC condition and generates TU-AIS upstream, even if the loopback is selected (the loopback signal is overwritten by TU-AIS).

TMPR28051 STS-1/AU-3 (STM-0) Mapper Advisory, Rev. 2 Device Advisory for Version 2 of the Device August 5, 1999 2 Lucent T echnologies Inc. Error Insertion (EI) (continued) EI-3. False S-BIP , L-BIP, and P-BIP Error Insertion The device transmits S-BIP, L-BIP, and P-BIP errors when configured for automatic insertion of REI, and certain STS-1 error conditions such as LOS, LOF, LOP-P, S-BIP, L-BIP, and P-BIP are inserted. EI-4. Forcing AIS Condition In order to force AIS using the VTDROP bits, a value of 0x1D must be programmed for DS1 AIS, and a value of 0x1E must be programmed for E1 AIS. VT Ma pping (VT ) VT-1. VT Path Payload Label Mismatch The device reports PLM-V when it detects three consecutive consistent new values for the VT label. This is in com- VT-2. Failure in the Detection of VT Loss of Pointer Defects ■ The device fails to detect an LOP-V defect or insert the required DS1/E1 AIS downstream when it receives VT pointer words with the N bits continuously set to 1001 (i.e., with a continuously set NDF). ■ The device also apparently fails to detect an LOP-V defect when it continuously receives a VT pointer word of 6C68 (i.e., a value indicating a VT1.5 with an offset of 104 bytes, versus a maximum valid offset of 103 bytes). In this case, the device inserts the required DS1 AIS downstream, but does not subsequently declare an LOP-V failure (nonconformance to GR 253, R6-71). VT-3. Inappropriate Termination of VT Loss of Pointer Defect Condition After the device has detected an LOP-V defect, it inappropriately terminates that defect upon receiving two pointer words containing the same value as the previous valid pointer. According to GR 253, an LOP-V defect must not be terminated unless a valid pointer is received in three consecutive VT superframes (nonconformance to GR 253, R6-75). VT-4. Inappropriate Termination of VT Alarm Indication Signal Defect Condition After the device has detected an AIS-V defect, it inappropriately terminates that defect upon receiving two pointer words containing the same value as the previous valid pointer and without a set NDF (e.g., with the N bits set to 0110). According to GR 253, an AIS-V defect must not be terminated unless a normal valid pointer is received in three consecutive VT superframes, or a valid pointer with a set NDF is received in one VT superframe (nonconfor- mance to GR 253, R6-183).

Advisory, Rev. 2 TMPR28051 STS-1/AU-3 (STM-0) Mapper August 5, 1999 Device Advisory for Version 2 of the Device 3Lucent Technologies Inc. VT Ma pping (VT ) (continued) VT-5. C-Bit Decoding In the presence of a receive SONET/SDH bit error rate, the device may destuff the DS1 from the VT1.5 incorrectly. This is the result of an error in the VT1.5 C-bit decoding process. The C-bit decoding process should be capable of correcting single errors to the C bits. Because of this error, an error in the first or second C bit for position 2 will be incorrectly decoded if the first C-bit position is calling for a stuff and the second C-bit position is not. The end result of this error is that both positions will call for a stuff, resulting in a bit being removed from the DS1 data stream. This will force downstream equipment to experience a reframe. The minimum time to false decode severity is as shown in Table VT-5 (in terms of seconds to false decode). Table VT-5. Minimum Time (in Seconds) to False Decode Severity of the C Bit In the absence of an external bit error rate, the algorithm decodes these C bits correctly. Test Pattern (TP ) Generator/Monitor TP-1. Test Pattern Insert The transmitted test pattern comes out on the opposite edge with respect to the jitter-attenuated data. TP-2. Test Pattern Drop The test pattern detector always inverts the clock coming into the block before retiming the data. Jitter Attenuation (JA ) JA-1. Jitter Attenuator The digital jitter attenuator buffers are not functional. The DJACTL bit in register 0x01 should be set to 0 in this device. Putting the device in the jitter attenuator mode (DJACTL = 1) causes loss of transmission. BER Theoretical Actual 10–3 125 0.25 10–4 12500 2.5 10–5 1250000 25 10–6 1.25e+8 250 10–7 1.25e+10 2500 10–8 1.25e+12 2.5e+4 10–9 1.25e+14 2.5e+5 10–10 1.25e+16 2.5e+6

Lucent T echnologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright © 1999 Lucent T echnologies Inc. All Rights Reserved August 5, 1999 AY99-026SONT -2 (Replaces AY99-026SONT and must accompany DS99-068SONT) For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, P A 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA P ACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent T echnologies (China) Co., Ltd., A-F2, 23/F , Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P . R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAP AN: Microelectronics Group, Lucent T echnologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, T okyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DA T ALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 T echnical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), IT AL Y: (39) 02 6608131 (Milan), SP AIN: (34) 1 807 1441 (Madrid) TMPR28051 STS-1/AU-3 (STM-0) Mapper Advisory, Rev. 2 Device Advisory for Version 2 of the Device August 5, 1999 STS Path Overhead (POH ) POH-1. False H4LOMF Indication Forcing a SONET/SDH line level decrement (H1, H2) from a value of either 348 or 347 results in false H4LOMF indications. Loss of Data (LOD ) LOD-1. Loss of DS1/E1 Data Simultaneously forcing VT pointer adjustments while forcing SONET/SDH decrements from values of 348 and 347 results in loss of DS1/E1 data. AY99-026SONT-2 Re places AY99-026SONT to Incorporate the Following Updates Added issues RA-5 and EI-3 to the document.

TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 3 of the Device Advisory, Rev. 2 August 5, 1999 Re gister Architecture (RA ) Map RA-1. Reset Bit The software reset bit (bit 0) of register 0x00 is not functional. RA-2. Transmit Path AIS Insert Bit The TXPAISINS bit (bit 5) of register 0x01 produces both AIS-P and AIS-L. RA-3. STS-1 Loss of Pointer Mask Bit The STS1LOPMSK bit (bit 2) of register 0x04 masks both STS1LOP and STS1LOF. RA-4. STS-1 Loss of Frame Mask Bit The STS1LOFMSK bit (bit 1) of register 0x04 is not functional. RA-5. VTLABCOM and VTRFIRDICOM Interru pt Bits Occasionally, it might require multiple reads to clear the composite interrupt bits VTLABCOM (bit 2 of register 0x05) and VTRFIRDICOM (bit 4 of register 0x05). Error Insertion (EI) EI-1. DS1/E1 Alarm Indication Signal The device does not insert DS1/E1 AIS towards the STS-1 if there is an LOC condition in the incoming DS1/E1 signal. EI-2. LOC Condition in E1 Loopback Mode In the absence of an input clock, the device detects an LOC condition and generates TU-AIS upstream, even if the loopback is selected (the loopback signal is overwritten by TU-AIS).

TMPR28051 STS-1/AU-3 (STM-0) Mapper Advisory, Rev. 2 Device Advisory for Version 3 of the Device August 5, 1999 2 Lucent T echnologies Inc. Error Insertion (EI) (continued) EI-3. False S-BIP , L-BIP, and P-BIP Error Insertion The device transmits S-BIP, L-BIP, and P-BIP errors when configured for automatic insertion of REI, and certain STS-1 error conditions such as LOS, LOF, LOP-P, S-BIP, L-BIP, and P-BIP are inserted. EI-4. Forcing AIS Condition In order to force AIS using the VTDROP bits, a value of 0x1D must be programmed for DS1 AIS, and a value of 0x1E must be programmed for E1 AIS. VT Ma pping (VT ) VT-1. VT Path Payload Label Mismatch The device reports PLM-V when it detects three consecutive consistent new values for the VT label. This is in com- VT-2. Failure in the Detection of VT Loss of Pointer Defects ■ The device fails to detect an LOP-V defect or insert the required DS1/E1 AIS downstream when it receives VT pointer words with the N bits continuously set to 1001 (i.e., with a continuously set NDF). ■ The device also apparently fails to detect an LOP-V defect when it continuously receives a VT pointer word of 6C68 (i.e., a value indicating a VT1.5 with an offset of 104 bytes, versus a maximum valid offset of 103 bytes). In this case, the device inserts the required DS1 AIS downstream, but does not subsequently declare an LOP-V failure (nonconformance to GR 253, R6-71). VT-3. Inappropriate Termination of VT Loss of Pointer Defect Condition After the device has detected an LOP-V defect, it inappropriately terminates that defect upon receiving two pointer words containing the same value as the previous valid pointer. According to GR 253, an LOP-V defect must not be terminated unless a valid pointer is received in three consecutive VT superframes (nonconformance to GR 253, R6-75). VT-4. Inappropriate Termination of VT Alarm Indication Signal Defect Condition After the device has detected an AIS-V defect, it inappropriately terminates that defect upon receiving two pointer words containing the same value as the previous valid pointer and without a set NDF (e.g., with the N bits set to 0110). According to GR 253, an AIS-V defect must not be terminated unless a normal valid pointer is received in three consecutive VT superframes, or a valid pointer with a set NDF is received in one VT superframe (nonconfor- mance to GR 253, R6-183).

Advisory, Rev. 2 TMPR28051 STS-1/AU-3 (STM-0) Mapper August 5, 1999 Device Advisory for Version 3 of the Device 3Lucent Technologies Inc. VT Ma pping (VT ) (continued) VT-5. C-Bit Decoding In the presence of a receive SONET/SDH bit error rate, the device may destuff the DS1 from the VT1.5 incorrectly. This is the result of an error in the VT1.5 C-bit decoding process. The C-bit decoding process should be capable of correcting single errors to the C bits. Because of this error, an error in the first or second C bit for position 2 will be incorrectly decoded if the first C-bit position is calling for a stuff and the second C-bit position is not. The end result of this error is that both positions will call for a stuff, resulting in a bit being removed from the DS1 data stream. This will force downstream equipment to experience a reframe. The minimum time to false decode severity is as shown in Table VT-5 (in terms of seconds to false decode). Table VT-5. Minimum Time (in Seconds) to False Decode Severity of the C Bit In the absence of an external bit error rate, the algorithm decodes these C bits correctly. Test Pattern (TP ) Generator/Monitor TP-1. Test Pattern Insert The transmitted test pattern comes out on the opposite edge with respect to the jitter-attenuated data. TP-2. Test Pattern Drop The test pattern detector always inverts the clock coming into the block before retiming the data. Device Version (DV ) DV-1. Device Version Report The device version register, 0x16, reports the device version as 0x02. BER Theoretical Actual 10–3 125 0.25 10–4 12500 2.5 10–5 1250000 25 10–6 1.25e+8 250 10–7 1.25e+10 2500 10–8 1.25e+12 2.5e+4 10–9 1.25e+14 2.5e+5 10–10 1.25e+16 2.5e+6

Lucent T echnologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright © 1999 Lucent T echnologies Inc. All Rights Reserved August 5, 1999 AY99-027SONT -2 (Replaces AY99-027SONT and must accompany DS99-068SONT) For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, P A 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA P ACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent T echnologies (China) Co., Ltd., A-F2, 23/F , Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P . R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAP AN: Microelectronics Group, Lucent T echnologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, T okyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DA T ALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 T echnical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), IT AL Y: (39) 02 6608131 (Milan), SP AIN: (34) 1 807 1441 (Madrid) TMPR28051 STS-1/AU-3 (STM-0) Mapper Advisory, Rev. 2 Device Advisory for Version 3 of the Device August 5, 1999 AY99-027SONT-2 Re places AY99-027SONT to Incorporate the Following Updates Added issues RA-5 and EI-3 to the document.

TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 4 of the Device Advisory, Rev. 2 August 5, 1999 Re gister Architecture (RA ) Map RA-1. Reset Bit The software reset bit (bit 0) of register 0x00 is not functional. RA-2. Transmit Path AIS Insert Bit The TXPAISINS bit (bit 5) of register 0x01 produces both AIS-P and AIS-L. RA-3. STS-1 Loss of Pointer Mask Bit The STS1LOPMSK bit (bit 2) of register 0x04 masks both STS1LOP and STS1LOF. RA-4. STS-1 Loss of Frame Mask Bit The STS1LOFMSK bit (bit 1) of register 0x04 is not functional. RA-5. VTLABCOM and VTRFIRDICOM Interru pt Bits Occasionally, it might require multiple reads to clear the composite interrupt bits VTLABCOM (bit 2 of register 0x05) and VTRFIRDICOM (bit 4 of register 0x05). Error Insertion (EI) EI-1. DS1/E1 Alarm Indication Signal The device does not insert DS1/E1 AIS towards the STS-1 if there is an LOC condition in the incoming DS1/E1 signal. EI-2. LOC Condition in E1 Loopback Mode In the absence of an input clock, the device detects an LOC condition and generates TU-AIS upstream, even if the loopback is selected (the loopback signal is overwritten by TU-AIS).

TMPR28051 STS-1/AU-3 (STM-0) Mapper Advisory, Rev. 2 Device Advisory for Version 4 of the Device August 5, 1999 2 Lucent T echnologies Inc. Error Insertion (EI) (continued) EI-3. False S-BIP , L-BIP, and P-BIP Error Insertion The device transmits S-BIP, L-BIP, and P-BIP errors when configured for automatic insertion of REI, and certain STS-1 error conditions such as LOS, LOF, LOP-P, S-BIP, L-BIP, and P-BIP are inserted. VT Ma pping (VT ) VT-1. VT Path Payload Label Mismatch The device reports PLM-V when it detects three consecutive consistent new values for the VT label. This is in com- VT-2. Failure in the Detection of VT Loss of Pointer Defects ■ The device fails to detect an LOP-V defect or insert the required DS1/E1 AIS downstream when it receives VT pointer words with the N bits continuously set to 1001 (i.e., with a continuously set NDF). ■ The device also apparently fails to detect an LOP-V defect when it continuously receives a VT pointer word of 6C68 (i.e., a value indicating a VT1.5 with an offset of 104 bytes, versus a maximum valid offset of 103 bytes). In this case, the device inserts the required DS1 AIS downstream, but does not subsequently declare an LOP-V failure (nonconformance to GR 253, R6-71). VT-3. Inappropriate Termination of VT Loss of Pointer Defect Condition After the device has detected an LOP-V defect, it inappropriately terminates that defect upon receiving two pointer words containing the same value as the previous valid pointer. According to GR 253, an LOP-V defect must not be terminated unless a valid pointer is received in three consecutive VT superframes (nonconformance to GR 253, R6-75). VT-4. Inappropriate Termination of VT Alarm Indication Signal Defect Condition After the device has detected an AIS-V defect, it inappropriately terminates that defect upon receiving two pointer words containing the same value as the previous valid pointer and without a set NDF (e.g., with the N bits set to 0110). According to GR 253, an AIS-V defect must not be terminated unless a normal valid pointer is received in three consecutive VT superframes, or a valid pointer with a set NDF is received in one VT superframe (nonconfor- mance to GR 253, R6-183).

Advisory, Rev. 2 TMPR28051 STS-1/AU-3 (STM-0) Mapper August 5, 1999 Device Advisory for Version 4 of the Device 3Lucent Technologies Inc. VT Ma pping (VT ) (continued) VT-5. C-Bit Decoding In the presence of a receive SONET/SDH bit error rate, the device may destuff the DS1 from the VT1.5 incorrectly. This is the result of an error in the VT1.5 C-bit decoding process. The C-bit decoding process should be capable of correcting single errors to the C bits. Because of this error, an error in the first or second C bit for position 2 will be incorrectly decoded if the first C-bit position is calling for a stuff and the second C-bit position is not. The end result of this error is that both positions will call for a stuff, resulting in a bit being removed from the DS1 data stream. This will force downstream equipment to experience a reframe. The minimum time to false decode severity is as shown in Table VT-5 (in terms of seconds to false decode). Table VT-5. Minimum Time (in Seconds) to False Decode Severity of the C Bit In the absence of an external bit error rate, the algorithm decodes these C bits correctly. Device Version (DV ) DV-1. Device Version Report The device version register, 0x16, reports the device version as 0x03. AY99-028SONT-2 Re places AY99-028SONT to Incorporate the Following Updates Added issues RA-5 and E1-3 to the document. BER Theoretical Actual 10–3 125 0.25 10–4 12500 2.5 10–5 1250000 25 10–6 1.25e+8 250 10–7 1.25e+10 2500 10–8 1.25e+12 2.5e+4 10–9 1.25e+14 2.5e+5 10–10 1.25e+16 2.5e+6

Lucent T echnologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright © 1999 Lucent T echnologies Inc. All Rights Reserved August 5, 1999 AY99-028SONT -2 (Replaces AY99-028SONT and must accompany DS99-068SONT) For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, P A 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA P ACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent T echnologies (China) Co., Ltd., A-F2, 23/F , Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P . R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAP AN: Microelectronics Group, Lucent T echnologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, T okyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DA T ALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 T echnical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), IT AL Y: (39) 02 6608131 (Milan), SP AIN: (34) 1 807 1441 (Madrid) TMPR28051 STS-1/AU-3 (STM-0) Mapper Advisory, Rev. 2 Device Advisory for Version 4 of the Device August 5, 1999

TMPR28051 STS-1/AU-3 (STM-0) Mapper

Features

■ Maps signals in one of the following ways: — Maps up to 28 asynchronous DS1 signals to SONET STS-1 via VT Groups, or SDH AU-3 via TUG-2. — Maps up to 21 asynchronous E1 signals to SDH AU-3 via TUG-2, or SONET STS-1 via VT Groups. — Maps any valid combination of DS1/E1 signals at the VT Group/TUG-2 level. ■ PLL-free receive operation using built-in digital jit- ter attenuators. ■ High-speed microprocessor interface configurable to operate with most commercial microprocessors. ■ Inserts valid B1, B2, and B3 bit interleaved parity (BIP) in the transmit direction. ■ Detects and counts B1, B2, and B3 BIP-8 errors on either a bit or block basis for performance monitor- ing in the receive direction. ■ Detects and counts V5 BIP-2 errors on either a bit or block basis for performance monitoring. ■ Configurable continuous B1, B2, B3, and V5 BIP-2 error insertion. ■ Configurable remote error indication (REI) inser- tion for B2, B3, and V5 BIP-2 errors. ■ Detects and counts remote errors. ■ Built-in test pattern insertion and drop for setup and maintenance. ■ Configurable VT1.5/TU-11 slot selection for DS1 insertion and drop. ■ Configurable VT2/TU-12 slot selection for E1 insertion and drop. ■ Detects STS-1 path loss of pointer (LOP-P), loss of H4 multiframe (H4LOMF), path alarm indication signal (AIS-P), and path remote defect indication (RDI-P). ■ Automatic receive monitor functions include VT/TU remote defect indication (RDI-V), VT/TU remote error indication (REI-V), BIP-2 errors, VT/TU AIS (AIS-V), and VT/TU loss of pointer (LOP-V). ■ Automatic receive monitoring functions can be configured to provide an interrupt to the control system, or the device can be operated in a polled mode. ■ User configurable for VT/TU label, AIS-V, RDI-V, REI-V, force BIP-2 errors, or unequipped tributary insertion. ■ Typical 3.3 V operation with 5 V TTL tolerant I/O and boundary scan. ■ –40 °C to +85 °C temperature range. ■ 208-pin shrink quad flat pack (SQFP) package. ■ Provides alarm and control features to easily implement the latest release of the following stan- dards: GR253-CORE (12/97 with the exception of T1.105.03A-1995, T1.105.07-1996, A pplications ■ SONET/SDH path termination multiplexers ■ SONET/SDH add/drop multiplexers ■ SONET/SDH cross connects ■ Digital access cross connects ■ DS1/E1 broadcast ■ SONET/SDH test equipment

Description

The Lucent Technologies Microelectronics Group TMPR28051 device is designed to map any valid combination of DS1 and E1 signals into a stream at a rate of 51.84 Mbits/s. This device provides all of the functions necessary to insert and drop any valid com- bination up to 28 asynchronous DS1 signals or 21 asynchronous E1 signals into an SPE.

TMPR28051 STS-1/AU-3 (STM-0) Mapper August 1999 2 Lucent T echnologies Inc. Table of Contents Contents Page

or equivalent, using the internal digital jitter attenuator buffer for PLL-free operation. user programmability for VT slot insertion and drop provide maximum flexibility for DS1/E1 I/O configuration. Note: “n” represents 28 or 21 for DS1 or E1, respectively. Figure 1. Block Diagram

Figure 2. Pin Diagram of 208-Pin SQFP

Table 1. Pin Descriptions tolerate 5 V at their inputs. internal 20 kΩ pull-up resistor. E1 signals can only occupy RCLK [1:21]. nal 20 kΩ pull-up resistor. E1 signals can only occupy RDATA [1:21]. times this rate when using the digital jitter attenuator. times this rate when using the digital jitter attenuator.

Table 1. Pin Descriptions (continued) tolerate 5 V at their inputs. (separate) address and data signals. and a combined read/write control. cessor to initiate a read cycle. to indicate a read cycle or asserted low to indicate a write cycle. address bus inputs are latched into the internal registers. low, the address bus inputs are latched into the internal registers. Modes section on page2 0). This pin has an internal 100 kΩ pull-up resistor. microprocessor registers 4 and 6. asserted low to indicate the device has completed a read or write operation. become the multiplexed address/data bus. address bus for the microprocessor interface registers. processor to initiate a write cycle. latches the signal on the data bus into internal registers. section on page3 7). This pin has an internal 20 kΩ pull-up resistor. 184 TCK Iu Boundar y-Scan Clock. This pin has an internal 20 kΩ pull-up resistor.

tolerate 5 V at their inputs. 189 TDO O Boundar y-Scan Output Data. input data, or 19.44 MHz or 6.48 MHz for byte-wide data. 8 kHz only or a composite of J0J1V1 for 2 kHz.

91 TSTS1SERIAL/

mode, this pin provides TSTS1DATA7.

88 TSTS1CLKOUT O Transmit STS-1 Out

input data, or 19.44 MHz or 6.48 MHz for byte-wide data. has an internal 100 kΩ pull-up resistor. parity. This pin has an internal 100 kΩ pull-up resistor. SS I Ground Reference for Digital Circuitry. VDD I Power Supply for Digital Circuitry.

TMPR28051 STS-1/AU-3 (STM-0) Mapper August 1999 10 Lucent T echnologies Inc. Nomenclature Assum ptions The mapping methods (VT1.5, VT2, and VT Group in ANSI nomenclature; TU-11, TU-12, and TUG-2 in ITU nomenclature) are analogous, and for the rest of this document will be referred to as VT1.5, VT2, or VT Group. STS-1 and AU-3 are also analo gous with a few minor differences. For the remainder of this document, the 51.84 Mbits/s signals are referred to as STS-1. DS1/E1 to STS-1 Block Descriptions In the descriptions of the block diagram of Figure 1, some of the control bits exist for each of the DS1/E1 or VT si gnals. Upon start-up, the device will set all of the input data types (DS1 or E1) based on the level of the DS1_E1N pin (pin 102). DS1_E1N controls the value transmitted in the unused overhead bytes and the value of the transmitted spare bits (SS ) in the H1 byte. If this pin is high, then all of the VT Groups are populated with DS1 signals. If this pin is low, then all of the VT Groups are populated with E1 signals. This default selection can be overridden by setting TOVERRIDE and ROVERRIDE bits in registers 0x88 (bit 0) and 0x89 (bit 0), respectively. The seven VT Groups can then be individually programmed to carry LOC and AIS Monitor The incoming DS1/E1 signal is first checked for loss of clock (LOC ). LOC is reported to the microprocessor via the DS1/E1LOC[1:21] and DS1LOC[22:28] bit (LOC = 1, 0 otherwise) in registers 0x17—0x32 (bit 6) and also via the AISLOCCOM composite bit in register 0x05 (bit 1). If LOC is present, the device inserts DS1/ E1 AIS towards the STS-1 using the blue signal clock. The incoming DS1/E1 data (RDATA [28:1]) is retimed immediately by the associated DS1/E1 clock (RCLK [28:1]). The edge of the clock that is used to retime the data is user-provisionable at the device level to either the risin g edge (RXDS1EDGE = 1 ) in register 0x02 (bit 1) or falling edge (RXDS1EDGE = 0 ) in regis- ter 0x02 (bit 1). After being retimed, the incoming data stream is checked for AIS. The device will declare AIS if the input data is at lo gic 1 for 3 ms. The device will withstand up to eight errors in the 3 ms period. AIS is reported to the microprocessor via the AISLOCCOM composite bit in register 0x05 (bit 1) and the individual DS1/E1AIS[1:21] and DS1AIS[22:28] bits in registers 0x17—0x32 (bit 7). The blue signal clock input signal to the device can be at the exact DS1/E1 rate (1.544/2.048 MHz) or at 16 times the DS1/E1 rate (24.704/32.768 MHz), with a tol- erance of 32 ppm or 50 ppm for DS1 or E1, respec- tivel y. This allows users of the Lucent Technologies T7698FL3/T7693 devices to reuse the XCLK on the board. The TMPR28051 is provisioned to accept the exact DS1 rate b y default (BLUECLKSEL = 0 in bit 2 of register 0x00), but can be changed to perform the divide-by-16 function (BLUECLKSEL = 1 in bit 2 of reg- ister 0x00). The duty cycle of the clock can be 45%/ 55% because the data is retimed internally in the device. The duty cycle requires a much tighter toler- ance when used for XCLK as described earlier. DS1/E1 Loopback Select Logic The first stage after retiming the signal into the device is selection of the externally received DS1/E1 (DS1/E1LB [1:21] or DS1LB[22:28] = 0) or the looped back DS1/E1 (DS1/E1LB [1:21] or DS1LB[22:28] = 1). This selection is provisionable per DS1/E1 input in reg- isters 0x17—0x32 (bit 5). Input Select Logic Once the DS1/E1 data sources have been selected, the DS1/E1 for each VT tributary is selected. This selection requires 5 bits per slot to determine which DS1/E1 input to use by provisioning DS1/E1INS[4:0]_[1:21] or DS1INS[4:0]_[22:28] bits in registers 0x17—0x32 (bits 4 through 0). The range [1:28] following the _ refers to the target VT #. Refer to Table 8 on page 15 and Table 10 on page 15 for details on the VT locations within the SPE. The numbering scheme for the five provisioned bits ranges from 00001 to 11100 where the binary value of the 5 bits corresponds to the DS1/E1 input. For instance, the value 00001 corresponds to selectin g DS1/E1 #1. The unused value of 00000 results in VT unequipped being transmitted. This is the default value for all the VT slots at powerup. VT unequipped has a valid pointer and all-zero payload. The unused values of 11101—11110 will cause AIS-V to be inserted for that VT slot.

test pattern to be inserted for that VT slot. VT1.5 slots can select the same DS1 input). (see Test Pattern Insert section on page1 9). ± 130 ppm with up to ±5 unit intervals peak jitter. put pointer value of decimal 78 in all the VT1.5 slots. for the V1 and V2 bytes within the VT1.5 superframe. VT overhead byte, V5, is shown in Table 2. Table 2. VT1.5 Overhead Byte Format (V5) ing VTAISINS[1:28] = 1 in registers 0x4F—0x6A (bit 3). Table 3. The automatic insertion mode may not meet Table 3. RFI-V, RDI-V Description

10 V T p a

11 V T u n e quipped

12 Lucent T echnologies Inc. insert field forces errors on both BIP-2 bits. Table 4. VT1.5 Superframe Table 5. VT2 Superframe

low, the device will transmit 1 in each of the O bits. The R bits are always set to 1. (when REI_EN = 1 in bit 7 of register 0x01). Table 6. STS-1 Overhead Byte Allocation BIP-8 even parity bytes into the STS-1 overhead. B[1:3]ERRINS = 1 in bit 6 through bit 4 of register 0x00. (F2INS-[7:0]) in register 0x10. indicating VT structured STS-1 SPE. ter 0x01). Valid values for these 4 bits are 0000—1000. Table 7. G1 Path Condition/Performance Byte

TMPR28051 STS-1/AU-3 (STM-0) Mapper August 1999 14 Lucent T echnologies Inc. DS1/E1 to STS-1 Block Descriptions (continued) STS-1/AU-3 Generate (continued) Path remote error indicator (REI-P) reports the number of remote errors. The four REI-P bits contain the num- ber of B3 BIP-8 errors detected in the current frame when REI_EN = 1 (bit 7 of register 0x01). Valid values for these 4 bits are 0000—1000. The path remote defect indicator (RDI-P) bits report back such condi- tions as receive AIS-P , signal failure, and path trace mismatch. These bits, 5 through 8 of the G1 byte (G1INS-[5:8] in register 0x11), are user programmable by the microprocessor and are not inserted automati- cally by the device. The H4 byte is inserted using the reduced H4 coding sequence format, where the 6 most significant bits are ones, and the 2 least significant bits take on the follow- ing values: 00-01-10-11-00, etc. The value of 00 indi- cates that the next STS-1 SPE contains the V1 overhead byte. The STS-1 can be provisioned to send AIS-P (TXPAISINS = 1 in bit 5 of register 0x01). Writing AIS-P consists of writing all 1s into the H1—H3 bytes and the entire SPE. The transmitted STS-1 can be configured to scramble the output data (STS1SCR = 1 in bit 2 of register 0x01) or transmit the data without scrambling (STS1SCR = 0 in bit 2, register 0x01). It is useful to turn off SONET scrambling if the data is going to be immediately multi- plexed into a higher rate SONET signal. When STS1SCR = 1 in register 0x01, the device scrambles the outgoing STS-1 frame according to the SONET frame synchronous scrambling sequence 1 + x6 + x7. The sequence is reset to 1111111 at the beginning of the byte following the C1 byte and scrambles all of the STS-1 data except the A1, A2, and C1 bytes. When this bit is 0, then the transmit data is not scrambled by the device. SPE Insertion Logic In addition to the one column of path overhead and 84 columns of VT pa yload, the STS-1 SPE also contains two columns of fixed stuff bytes. The path overhead is located in column #1, while column #30 and column #59 contain the fixed stuff b ytes. The remaining col- umns contain the interleaved VT data as shown in Table 8. The SPE insertion lo gic block acts in conjunction with the STS-1 frame generate block to place the VT infor- mation in the transmitted data stream. The cross-referencing between the VT1.5 # listed in Table 8 and the standard format (VT Group #, VT #) listed in GR-253-CORE section 3.2.4 is shown in Table 9. The cross-referencin g between the VT2 # listed in Table 10 and the standard format (VT Group #, VT #) listed in GR-253-CORE section 3.2.4 is shown in Table 11.

Table 8. VT1.5 SPE Insertion Format

• • • V T V T F I X E D V T V T
• • • V T V T F I X E D V T V T V T
• • • V T V T V T V T V T V T V T

Table 9. Ma Table 10. VT2 SPE Insertion Format

• • • V T V T F I X E D V T V T
• • • V T V T F I X E D V T V T V T
• • • V T V T V T V T V T V T V T

Table 11. Ma

TMPR28051 STS-1/AU-3 (STM-0) Mapper August 1999 16 Lucent T echnologies Inc. DS1/E1 to STS-1 Block Descriptions (continued) SPE Insertion Logic (continued) The device can transmit the data as either a serial bit stream (TXSERIAL = 1 in register 0x02, bit 6) or as a parallel byte of data (TXSERIAL = 0 in register 0x02, bit 6). There are two parallel modes of operation: bus mode and nonbus mode. Bus mode allows multiple TMPR28051 devices to operate on a 19.44 MHz bus; in nonbus mode, the device transmits data in a point-to-point fashion at 6.48 MHz. In either parallel mode, the device sends a parit y bit with the data. This parity bit is configurable to be either odd (TXPARITY = 1 in register 0x02, bit position 4) or even (TXPARITY = 0 in register 0x02, bit position 4) parity. The bus mode of operation requires the device to select which STS-1 time slot of the three that are avail- able to transmit data. The TBUSMODE bit (bit 2) in reg- ister 0x12 determines whether the device operates in bus mode (TBUSMODE = 1 ) or nonbus mode (TBUSMODE = 0 ). By default, the device powers up in bus mode. The TBUSPOS bits (bit 1 and bit 0) in regis- ter 0x12 determine in which of the three time slots the device transmits. B y default, the device does not trans- mit (TBUSPOS- [1:0] = 00 in register 0x12), but it can be configured to transmit during any of the three STS-1 time slots on the 19.44 MHz bus. In all three modes, the device frame sync input allows the 8 kHz STS-1 frames as well as the 2 kHz VT super- frames to be ali gned. STS-1 to DS1/E1 Block Descriptions Loo pback Select Logic The device can be configured to loop back the transmit STS-1 (STS1LB = 1 in bit 0 of register 0x01) or accept the receive STS-1 signal (STS1LB = 0 in bit 0 of regis- ter 0x01). When the receive STS-1 signal is selected, the user can configure which edge of the clock to use to retime the data (RXSTS1EDGE = 1 in bit 3 of regis- ter 0x02 uses the rising edge; RXSTS1EDGE = 0 in bit 3 of register 0x02 uses the falling edge). SPE Locate The device can receive data as either a serial bit stream (RXSERIAL = 1 in bit 7 of register 0x02) or as a parallel byte (RXSERIAL = 0 in bit 7 of register 0x02). In the parallel mode, the device receives a parity bit with the data. This bit is configurable to odd (RXPARITY = 1 in bit 5 of register 0x02) or even (RXPARITY = 0 in bit 5 of register 0x02) parity. Errors in this bit are reported to the microprocessor (RXPARER in bit 6 of register 0x03). The bus mode of operation is similar to normal opera- tion in the DS1/E1 to STS-1 direction. The device defaults to the bus mode (RBUSMODE = 1 in bit 5 of register 0x12) of operation and listens to none of the receive channels (RBUSPOS- [1:0] = 00 in bit 4 and bit 3 of register 0x12). The sync pulse is used only to define time slot #1 of the three that are possible. Bus mode operation re quires at least one sync pulse to define the time slot. The STS-1 locate block performs the functions neces- sary to locate the SPE. The device will frame on the incoming STS-1 signal, and indicate when it is in the out of frame (OOF ) condition (STS1OOF = 1 in bit 0 of register 0x03) or loss of frame (LOF ) condition (STS1LOF = 1 in bit 1 of register 0x03). Loss of frame is defined as being in the OOF condition for 3 ms or more. Both the OOF and LOF are current state condi- tions; the y hold their value for a minimum of 500 µs after the event. The indications reset if the condition is no lon ger true. The device monitors the received data bytes for contin- uous ones or zeros. If the number of continuous data b ytes exceeds the provisioned value (LOSDET- [7:0] in register 0x91), then loss of signal (STS1LOS = 1 in bit 0 of register 0x05) is declared. If the value in LOSDET- [7:0] in register 0x91 is 0x00, then LOS is not declared. STS-1/AU-3 Terminate The STS-1 terminate block can descramble the output data (STS1DSCR = 1 in bit 1 of register 0x01) or output the received data without descrambling (STS1DSCR = 0 in bit 1 of register 0x01). It is useful to turn off descrambling if the data is received locally from a higher-rate signal where descrambling has already taken place. For performance monitoring purposes, there are a number of BIP and REI error counters (registers 0xC0—0xFF ) in the receive section of the device. All of these internal counters are comprised of a running error counter and a hold register that presents stable results to the microprocessor. The counts in all of the runnin g counters are latched to the hold registers when LATCH_CNT (bit 3) in register 0x00 is written from 0 to 1. This also resets all of the running counters. The results are then held until read by the microprocessor.

August 1999 TMPR28051 STS-1/AU-3 (STM-0) Mapper 17Lucent T echnologies Inc. STS-1 to DS1/E1 Block Descriptions (continued) STS-1/AU-3 Terminate (continued) All of the internal counters have the ability to store more than one second of counts. As long as the LATCH_CNT (bit 3) in register 0x00 occurs every sec- ond or faster, no counts will be lost. In case this does not happen, all of the runnin g counters will hold their maximum value rather than roll over to zeros. The device performs pointer interpretation on the incoming signal to locate the start of the SPE. The pointer interpretation block will indicate when the device is in the path loss of pointer (LOP-P ) or path AIS (AIS-P) condition. Loss of pointer condition is declared as the result of either of the following conditions: 1. Continuous NDF—If the device receives 1001 in the NDF field for nine consecutive frames, then LOP-P is declared. 2. Invalid pointer values—If the device receives nine frames consecutivel y of a pointer that is not a nor- mal value, NDF, AIS-P, increment, or decrement, then LOP-P is declared. The SS bits do not contrib- ute to LOP-P when DS1_E1N is hi gh; otherwise, a non-10 value in the SS bits will contribute to LOP-P . AIS-P is declared on three consecutive frames with all 1s in the H1 and H2 bytes. AIS-P and LOP-P are mutually exclusive conditions. If neither STS1PAIS (bit 3 in register 0x03) or STS1LOP (bit 2 in register 0x03) is a logic 1, then the pointer interpreter declares a normal pointer. As part of the normal operation, the device will respond appropriatel y to valid NDF, increment, and decrement indications. Increment and decrement operations will be counted b y the device and presented to the microprocessor via the SPTR+[7:0] and SPTR–[7:0] bits in registers 0xFE and 0xFF, respectively. The B1, B2, and B3 BIP-8 values are recalculated and compared to the received values. Any differences are counted by the appropriate error counter (B[1:3]BIPCNT-[15:0] in registers 0xC0—0xC5 when BIP_CNTS = 1 in register 0xBF). In addition, B2 and B3 REI errors are also counted in registers 0xC2—0xC5 (B[2:3]REI-[15:0]; register 0xBF settings: REI_CNTS = 1 and BIP_CNTS = 0). The running and latched counts for both B1 and B2 counters are held at zero durin g OOF. The running and latched counts for B3 counters are held at zero during OOF as well as LOP-P. The device can be provisioned to count bits in error (BIPBLKCNT = 0 in bit 1 of register 0x00) or blocks in error (BIPBLKCNT = 1 in bit 0 of register 0x00). The J1 byte is terminated within the device. This con- sists of writing the receive J1 sequentially in a 64-byte register (modulo 64). At start-up, the receive J1 byte register is all 0s. When- ever the received J1 byte value does not match the current J1 byte in the register, the path trace mismatch TRACEER bit (bit 7 in register 0x03) is set to logic 1. This allows the user to read the 64-byte register once, and then ignore it unless differences are received. TRACEER bit (bit 7 in register 0x03) is masked during AIS-P and LOP-P. The F2 byte (F2-[7:0] in register 0x0B), the C2 byte (C2-[7:0] in register 0x0C), the 3 least significant bits of the K2 byte (K2-[6:8] in register 0x0D), the 4 least sig- nificant bits of the S1 byte (S1-[3:0] in register 0x14), and the 4 least significant bits of the G1 byte (G1-[5:8] in register 0x0D) are monitored by the microprocessor. The number of consistent, consecutive frames to update the values of all of these monitored b ytes can be set by the user to anywhere between 2 and 15 frames (F2#DET- [3:0] in register 0x0E, C2#DET-[3:0] in register 0x0E, K2#DET-[3:0] in register 0x0F, G1#DET- [3:0] in register 0x0F). None of these regis- ters will update during OOF condition. SPE Dro p Logic The SPE drop logic uses the H4 multiframe indicator to identify the V1 byte and drop the data to the correct VT termination blocks. Loss of multiframe synchronization will be reported to the microprocessor (H4LOMF = 1 in bit 4 of register 0x03). VT Terminate The VT terminate block performs VT pointer interpreta- tion on the received si gnal to locate the VT overhead. LOP-V (VTLOP [1:28] bit 6 in registers 0x6B—0x86) and AIS-V (VTAIS[1:28] bit 3 in registers 0x6B—0x86) are reported to the microprocessor. LOP-V is declared as a result of either of the followin g conditions: 1. Continuous NDF—If the device receives 1001 in the NDF field for nine consecutive superframes, then LOP-V is declared. 2. Invalid pointer values—If the device receives nine frames consecutivel y of a pointer that is not a nor- mal value, NDF, AIS-V, increment, or decrement, then LOP-V is declared. The SS bits do contribute to LOP-V.

TMPR28051 STS-1/AU-3 (STM-0) Mapper August 1999 18 Lucent T echnologies Inc. STS-1 to DS1/E1 Block Descriptions (continued) VT Terminate (continued) AIS-V is declared on three consecutive superframes with all 1s in the V1 and V2 bytes. AIS-V and LOP-V are mutually exclusive conditions. If neither VTAIS[1:28] (bit 3 in registers 0x6B—0x86) or VTLOP [1:28] (bit 6 in registers 0x6B—0x86) is a logic 1, then the pointer interpreter declares a normal pointer. As part of the normal operation, the device will respond appropriatel y to valid NDF, increment, and decrement indications. Increment and decrement oper- ations will be counted b y the device and presented to the microprocessor via bits VT[1:28]PTR+ [3:0] in regis- ters 0xC6—0xFF (BIP_CNTS = 1), and via VT [1:28]PTR– [3:0] in registers 0xC6—0xFF (REI_CNTS = 1 and BIP_CNTS = 0), respectively. Mismatches between the expected VT size bits, bit 11 for VT1.5 and bit 10 for VT2, and the actual received SS size bits are reported to the microprocessor VTSIZEER [1:28] bit (bit 7 in registers 0x6B—0x86). Once the V5 byte is located, the device checks for received BIP-2 errors (B2BIPCNT- [15:0] in registers 0xC0—0xC1 when BIP_CNTS bit in register 0xBF is set to 1) and received REI (B[2:3]REI-[15:0] in registers 0xC2—0xC5 when REI_CNTS and BIP_CNTS in reg- ister 0xBF are set to a 1 and 0, respectively). In addi- tion to reporting the occurrence of BIP-2 errors and REI, the device also maintains a count of each of these on a per VT basis (VTREI [7:0]_[1:28] in registers 0xC7—0xFD: REI_CNTS = 1, BIP_CNTS = 0, and BIP2CNT [7:0]_[1:28] in registers 0xC7—0xFD: BIP_CNTS = 1). These running and latched counts for both BIP-2 and REI counters are held at zero during OOF, LOP-P, LOP-V, and AIS-V. Additionally, the device checks for received RFI-V and RDI-V (bit 5 and bit 4, respectively, in registers 0x6B—0x86 ) and received VT label (VTLAB [2:0]_[1:28], bit 2 through bit 0 in registers 0x6B—0x86 ). Whenever the device receives three consecutive consistent values for the VT label fields that are different from the current values, it latches the new value and reports the chan ge to the microproces- sor. When a 1 is received in VTRDI0_[1:28], bit 4 in registers 0x6B—0x86 (represents bit 8 of the VT V5 overhead byte), for 10 consecutive superframes, it declares an RDI-V condition. Jitter Attenuate Each of the 28 VTs has a built-in digital jitter attenuator to remove the effects of mapping jitter and pointer adjustment jitter. The bits in registers 0x8A—0x8F are used to control various aspects of the digital jitter atten- uator. Two programmable terms are used to set the 2nd-order loop damping factor and natural frequency of the PLL. These terms are the gain threshold, set by DJAGTHR [23:0] in registers 0x8D—0x8F, and scale value, set by DJASCALE [15:0] in registers 0x8B—0x8C. The PLL bandwidth can be set using the above registers to accommodate various system con- straints. The digital jitter attenuator block can be enabled by setting the bit DJACTL = 1 (bit 4) in register 0x01. These digital jitter attenuators require a blue signal clock that runs at 16 times the nominal output rate. The digital jitter attenuators are designed to meet cur- rent jitter specifications as well as maximum time inter- val error (MTIE ) requirements. The clock transmitted from this block nominally has a 50% duty cycle. The jit- ter attenuator block can be bypassed by setting DJACTL = 0 (bit 4) in register 0x01. If this block is bypassed, the output produces gapped clock and data. Drop Select Logic Once the VT has been terminated, the source VT for each DS1/E1 output is selected. This selection re quires 5 bits per slot to determine which VT to use by programming VTDROP [4:0]_[1:28] bits (bits 4 through 0 in registers 0x33—0x4E). The numbering scheme for the five provisioned bits ranges from 00001 to 11100, where the binary value of the 5 bits corresponds to the VT source. For instance, the value 00001 corresponds to selectin g VT Group 1, VT #1. The unused values of 00000 and 11101—11110 will cause AIS to be inserted for that DS1 output. By default, all DS1/E1 outputs reset to a value of 00000 on powerup, which causes all of the DS1/E1s to transmit AIS (all 1s) using the blue signal clock. The value of 11111 will insert the test pattern as described next.

August 1999 TMPR28051 STS-1/AU-3 (STM-0) Mapper 19Lucent T echnologies Inc. Test Pattern Block Descriptions The device contains a test pattern generator and a test pattern detector for use in maintenance and trouble- shootin Test Pattern Insert The test pattern generator is capable of transmitting four different test patterns (XMT_PAT- [1:0] in bit posi- tions 0 and 1 of register 0x08). In addition to a 215 – 1, a 220 – 1, and a 223 – 1 sequence, the device can also transmit a QRSS sequence. The QRSS pattern is a 220 – 1 pseudorandom bit sequence defined by the equation 1 + x17 + x20 = 0, with a 14 zero limit. As can be seen in Figure 1 on page 5, this test pattern can be inserted in the place of any of the transmitted or received DS1/E1 signals. The test pattern can also be provisioned to be framed (XMT_FRAME = 1 in bit 2 of register 0x08) or unframed (XMT_FRAME = 0 in bit 2 of register 0x08). The framed sequence can be either DS1 SF format (TP_DS1E1N = 1 in bit 7 of register 0x09) or E1 format (TP_DS1E1N = 0 in bit 7 of register 0x09). The test pattern can also be forced to transmit a bit error (ERROR_INS bit in register 0x08, bit position 3, is forced to make low to high transition). The test patterns are O.151 compliant, so they can be used to drive external test equipment as well as to perform internal maintenance and troubleshooting. Test Pattern Drop The test pattern detector can detect the same four test se quences generated by the test pattern generator (RCV_PAT- [1:0] in bit positions 4 and 5 of register 0x08). When the detector is out of synchronization, the device continuously monitors the input data signal for matches with the expected data signal. When the device detects 32 matches in a row, it declares itself in s ync (TPOOS = 0 in bit 7 of register 0x0A), and the error detector is enabled. If the device detects eight consecutive bit mismatches, the test pattern detector declares itself out of s ync (TPOOS = 1 ), and starts searching again. The test pattern detector can be configured to look for a framed (RCV_FRAME = 1 in bit 6 of register 0x08) or unframed (RCV_FRAME = 0 in bit 6 of register 0x08) signal. While in sync, the device counts the number of times the input data differs from the expected data in a 7-bit counter, TPERR- [6:0] (bit 0 through bit 6 in register 0x0A), that holds its count when it reaches the maxi- mum value of 128. This counter is reset when the LATCH_TP bit (bit 7) in register 0x08 makes a 0 to 1 transition.

20 Lucent T echnologies Inc. of registers within the device. gisters must be written by the microprocessor on system start-up to guarantee proper device functionality. Table 12 highlights the four microprocessor modes controlled by the MPMUX and MPMODE inputs. Table 12. Microprocessor Configuration Modes

same set of pins in all modes. Table 13. Mode [1—4] Microprocessor Pin Definitions

22 Lucent T echnologies Inc. Table 13. Mode [1—4] Microprocessor Pin Definitions (continued)

0xBF (see the Register Architecture Description section, page 57—pa ge 59). Table 14. Device Register Map

24 Lucent T echnologies Inc. Table 14. Device Register Map (continued)

26 Lucent T echnologies Inc.

28 Lucent T echnologies Inc.

30 Lucent T echnologies Inc.

32 Lucent T echnologies Inc.

34 Lucent T echnologies Inc.

36 Lucent T echnologies Inc.

Table 15. Registers 0x00—0x16: Device-Level Control, Alarm, and Mask Bits counters to test mode and is intended for factory use only. This bit should always be set to 0. errors to be transmitted in their respective BIP-8 values.

5 B2ERRINS

4 B3ERRINS

that is not updated by this bit is the test pattern counter.

2 BLUECLKSEL The device can accept a blue si gnal clock at either the

38 Lucent T echnologies Inc. Table 15. Re gisters 0x00—0x16: Device-Level Control, Alarm, and Mask Bits (continued)

6 AUTO_LRDI When AUTO_LRDI = 1, the device will automaticall

5 TXPAISINS When TXPAISINS = 1, the device will write all 1s into the

4 DJACTL The DJACTL is used to enable the use of the built-in digital

the smoothed clock and data are transmitted. the transmit data is not scrambled. this bit is 0, then the received data is not descrambled. device uses the received data.

retime data into and out of the device.

6 TXSERIAL

5 RXPARITY Both the RXPARITY and TXPARITY bits determine the

with 1, odd parity is used; otherwise, even parity is used.

4 TXPARITY

3 RXSTS1EDGE When the ed ge register bits are set to 1, the data is retimed

ing edge of the TSTS1CLKOUT. to avoid potential race condition inside the device.

1 RXDS1EDGE

0 TXDS1EDGE

40 Lucent T echnologies Inc.

7 TRACEER The device monitors the received J1 b yte for path trace

match the previously received pattern, then TRACEER = 1. This is an event bit and is held until read.

6 RXPARER RXPARER = 1 reports a parit y violation on the receive

4 H4LOMF The device monitors the incomin

3 STS1PAIS STS1PAIS = 1 reports path AIS as detected b y the receive

indications reset if the condition is no longer true.

1 STS1LOF STS1LOF = 1 reports an out of frame condition that per-

0 STS1OOF STS1OOF = 1 reports an out of frame condition on the

condition is no longer true. register masks all of the bits in register 0x03.

6 RXPARERMSK

3 STS1PAISMSK

2 STS1LOPMSK

1 STS1LOFMSK

0 STS1OOFMSK

error, the corresponding composite bit indicates an error.

7 ESOFCOM ESOFCOM = 1 reports that the device has experienced

an event bit and is held until read. VT size bits are 11 for VT1.5 and 10 for VT2. 5 VTLOPCOM VTLOPCOM = 1 reports LOP-V.

4 VTRFIRDICOM VTRFIRDICOM = 1 reports the fact that the VT RFI/RDI

3 VTAISCOM VTAISCOM = 1 reports the fact that the V1 and V2 pointer

ytes are all 1s for three consecutive superframes. an event bit and is held until read.

1 AISLOCCOM AISLOCCOM = 1 reports an AIS or LOC condition on DS1/

42 Lucent T echnologies Inc.

6 VTSIZEMSK

4 VTRFIRDIMSK

0 STS1LOSMSK

7—1 — Reserved. These bits are set to 0 at reset.

0 DS1_E1N This bit reports the DS1_E1N value from the device input

tern generator and detector.

7 LATCH_TP A 0 to 1 transition on LATCH_TP causes the runnin g error

count to be latched and presented to the microprocessor.

6 RCV_FRAME RCV_FRAME = 1 causes a framed test pattern to be

5 RCV_PAT-1 RCV_PAT [1:0] determines the receive test pattern

4 RCV_PAT-0

3 ERROR_INS ERROR_INS causes a sin gle error to be inserted in the

data (not frame) bits after a 0 to 1 transition.

2 XMT_FRAME XMT_FRAME = 1 causes a framed test pattern to be gen-

1 XMT_PAT-1 XMTPAT- [1:0] determines the transmit test pattern

0 XMT_PAT-0

7 TP_DS1E1N TP_DS1E1N = 1 sets the frame se quence to DS1;

TP_DS1E1N = 0 sets the frame sequence to E1.

6 TP_INVERT TP_INVERT = 1 forces the test pattern se quence to be

5 TPDROPSIDE When TPDROPSIDE = 1, the test pattern is dropped from

4 TPDROP-4 The TPDROP [4:0] bits are used to select the VT that needs

7 TPOOS If the test pattern detector has been able to s ynchronize on

the dropped signal, then TPOOS = 0.

6 TPERR-6 When TPOOS = 0, then the TPERR- [6:0] bits are used to

gister is read by the microprocessor. receive byte in the path overhead. value for this register indicates path unequipped.

44 Lucent T echnologies Inc.

2 K2-6 The K2-

0x0C before updating their values.

7 C2#DET-3 The C2#DET- [3:0] bits are used to set the number of con-

C2-[7:0] bits in register 0x0C.

6 C2#DET-2

5 C2#DET-1

4 C2#DET-0

3 F2#DET-3 The F2#DET- [3:0] bits are used to set the number of con-

before updating their values.

7 G1#DET-3 The G1#DET- [3:0] bits are used to set the number of con-

G1-[5:8] bits in register 0x0D.

3 K2#DET-3 The K2#DET-

values to be transmitted in the F2 byte.

transmitted in the G1 and K2 bytes. G1 byte is written by the microprocessor.

2 K2INS-6 The K2INS-

mitted in the three least significant bits of the K2 byte. operation for both the transmit and receive sides.

5 RBUSMODE The RBUSMODE bit sets the STS-1 receive side of the

the device is set to nonbus mode.

4 RBUSPOS-1 The RBUSPOS-

[1:0] sets the time slot for the receive side.

2 TBUSMODE The TBUSMODE bit sets the STS-1 transmit side of the

the device is set to nonbus mode.

1 TBUSPOS-1 The TBUSPOS-

0 TBUSPOS-0

46 Lucent T echnologies Inc.

3 S1INS-3 The S1INS- [3:0] bits in register 0x13 are used to set the

7 S1#DET-3 The S1#DET- [3:0] bits are used to set the number of con-

3 S1-3 The S1-

The reset default value is the device version.

3 DEVVER-3

2 DEVVER-2

1 DEVVER-1

0 DEVVER-0

Table 16. Registers 0x17—0x32: DS1/E1 Insertion Selection

0.7 DS1/E1AIS [1:21] The DS1/E1AIS[1:21] bits report the received DS1/E1

the condition is no longer true.

6 DS1/E1LOC [1:21] The DS1/E1LOC [1:21] bits in bit 6 report the received

condition is no longer true.

5 DS1/E1LB [1:21] The DS1/E1LB[1:21] bits in bit 5 are used to force DS1/

by the outgoing DS1/E1 signal for that location.

4 DS1/E1INS4_ [1:21] The DS1/E1INS[4:0]_[1:21] bits in registers 0x17—

3 DS1/E1INS3_ [1:21]

2 DS1/E1INS2_ [1:21]

1 DS1/E1INS1_ [1:21]

0 DS1/E1INS0_ [1:21]

48 Lucent T echnologies Inc. Table 16. Registers 0x17—0x32: DS1/E1 Insertion Selection (continued)

0.7 DS1AIS [22:28] The DS1/E1AIS[1:21] and DS1AIS[22:28] bits report the

when the condition is no longer true.

6 DS1LOC [22:28] The DS1/E1LOC [1:21] and DS1LOC[22:28] bits in bit 6

5 DS1LB [22:28] The DS1/E1LB[1:21] and DS1LB[22:28] bits in bit 5 are

ten by the outgoing DS1 signal for that location.

4 DS1INS4_ [22:28] The DS1/E1INS[4:0]_[1:21] and DS1INS[4:0]_[22:28] bits

3 DS1INS3_ [22:28]

2 DS1INS2_ [22:28]

1 DS1INS1_ [22:28]

0 DS1INS0_ [22:28]

Table 17. DS1/E1 Insertion Selection Format Table 18. Registers 0x33—0x4E: VT Drop Selection

5 Programmed DS1/E1INS[4:0]_x Bits

0.6 RXESOF [1:28] The RXESOF [1:28] bits (see VT Drop Selection Registers,

DS1/E1 output has experienced an elastic store overflow.

5 TXESOF [1:28] The TXESOF [1:28] bits (see Control, Alarm, and Mask Bit

4 VTDROP4_ [1:28] These bits in registers 0x33—0x4E are used to select the

3 VTDROP3_ [1:28]

2 VTDROP2_ [1:28]

1 VTDROP1_ [1:28]

0 VTDROP0_ [1:28]

50 Lucent T echnologies Inc. Table 19. VT Drop Selection Format Table 20. VT to Address Mapping

5 Programmed DS1/E1INS[4:0]_x or VT Drop Data Bits

Table 21. Registers 0x4F—0x6A: Tx VT Overhead Insertion Control

7 BIP2ERINS [1:28] Each BIP2ERINS[1:28] bit = 1 forces the selected VT to

stream receiver to declare continuous BIP-2 errors.

6 VTRFIRDIEN

microprocessor (VTRFIRDIEN [1:28] = 0).

5 VTRFIINS [1:28] The VTRFIINS[1:28] bits directly program the transmitted

4 VTRDIINS [1:28] The VTRDIINS[1:28] bits directly program the transmitted

1s into the selected VT slot. well as specific payload mappings and AIS-V.

52 Lucent T echnologies Inc. Table 22. Registers 0x6B—0x86: Rx VT Drop Monitoring indications reset if the condition is no longer true.

4 VTRDI0_ [1:28]

µs. The indications reset if the condition is no longer true. 2 VTLAB2_ [1:28] The VTLAB [2:0]_[1:28] bits report the received VT labels.

0 VTLAB0_ [1:28]

Table 23. Registers 0x88—0x89: Signal Override Control can be individually programmed as follows.

0 TOVERRIDE If TOVERRIDE = 1, then the t

Group is determined by the 7 TVTG bits. can be individually programmed as follows.

0 ROVERRIDE If ROVERRIDE = 1, then the t

Group is determined by the 7 RVTG bits.

54 Lucent T echnologies Inc. Table 24. Registers 0x8A—0x8F: Digital Jitter Attenuator Controls

Table 25. Register 0x91: STS-1 LOS Detect/Test Pattern Edge Control

6.48 MHz clock periods required to declare received STS-1

the QRSS pattern generator and detector data is clocked. clock to retime the data, or uses the falling edge otherwise.

56 Lucent T echnologies Inc. Table 26. Register 0xBF: Block Control to the microprocessor from the registers 0xC0—0xFF. presented in the description of bits 2, 1, 0. 7—4 — Reserved. These bits are set to 0.

3 TJ1BYTE If TJ1BYTE = 1, the transmitted J1 b yte values are pre-

2 RJ1BYTE If RJ1BYTE = 1, the received J1 b ytes are presented

1 REI_CNTS If REI_CNTS = 1, REI error information is presented

0 BIP_CNTS If BIP_CNTS = 1, BIP error information is presented,

Table 27. Registers 0xC0—0xFD: Detected BIP Errors number of BIP errors detected by the device. Table 28. Registers 0xFE, 0xFF: Received SONET/SDH Pointer Value tors in the individual VT1.5 slots. increment counts are also presented in these registers.

3 BIP2CNT11_ [1:28]

2 BIP2CNT10_ [1:28]

1 BIP2CNT9_ [1:28]

0 BIP2CNT8_ [1:28]

7 BIP2CNT7_ [1:28]

6 BIP2CNT6_ [1:28]

5 BIP2CNT5_ [1:28]

4 BIP2CNT4_ [1:28]

3 BIP2CNT3_ [1:28]

2 BIP2CNT2_ [1:28]

1 BIP2CNT1_ [1:28]

0 BIP2CNT0_ [1:28]

58 Lucent T echnologies Inc. Table 29. Registers 0xC0—0xFD: Detected REI Errors are used to count the number of REI errors detected by the device. Table 30. Registers 0xFE—0xFF: Reserved When register 0xBF is set for BIP_CNTS = 0 and REI_CNTS = 1, the bytes in registers 0xFE—0xFF are reserved. Terminate section, page 16 and page 17). Note: In registers 0xC6—0xFC, bit 3 is reserved.

Table 31. Registers 0xC0—0xFF: Receive J1 Path Trace Bytes isters 0xC0—0xFF are used to read the received 64 path trace bytes. Table 32. Registers 0xC0—0xFF: Transmit J1 Path Trace Bytes ters 0xC0—0xFF are used to provision the transmit 64 path trace bytes. tion, then TRACEER bit (bit 7) in register 0x03 is set to 1. written by the microprocessor.

60 Lucent T echnologies Inc. cycle time is 200 ns for all device configurations. The read and write timing diagrams for all four microprocessor interface modes are shown in Figures 3—10. Table 33. Microprocessor Interface I/O Timing Specifications

ings for extended periods can adversely affect device reliability. Table 34. Absolute Maximum Ratings using these circuit parameters. Table 35. ESD Threshold Voltage

TMPR28051 STS-1/AU-3 (STM-0) Mapper August 1999 66 Lucent T echnologies Inc. O perating Conditions

Electrical Characteristics

Table 37. Logic Interface Characteristics Table 36. Recommended Operating Conditions 20 µA. All buffers use CMOS levels.

Table 38. Input Clock Specifications

68 Lucent T echnologies Inc. tal system interface timing is shown in Figure 11.

• These clock edges are programmable through the microprocessor interface.

↑ represents a low-to-high transition. ↓ represents a high-to-low transition. Figure 11. Interface Data Timing Table 39. Input Timing Specifications

The output clock specifications are shown in Table 40. shown in Figure 11, page 68.

• Propagation delay skew, tPLH —t PHL, is ±200 ps.

↑ represents a low-to-high transition. ↓ represents a high-to-low transition. Table 40. Output Clock Specifications

1.544 MHz ± 5% C L = 50 pF — 30 — 30 ns

2.048 MHz ± 5% C L = 50 pF — 30 — 30 ns

19.44 MHz ± 5% C L = 15 pF — 3 — 3 ns

6.48 MHz ± 5% C L = 15 pF — 3 — 3 ns

Table 41. Output Timing Specifications

TMPR28051 STS-1/AU-3 (STM-0) Mapper August 1999 74 Lucent T echnologies Inc. Outline Diagram 208-Pin SQFP Dimensions are in millimeters. 5-2196(F)r.14 156 105 30.60 ± 0.20 157208 53 104 28.00 ± 0.20 28.00 ± 0.20 30.60 ± 0.20 PIN #1 IDENTIFIER ZONE

4.10 MAX

0.08 3.40 ± 0.20 SEATING PLANE 0.25 MIN0.50 TYP DETAIL BDETAIL A 0.50/0.75 GAGE PLANE SEATING PLANE

1.30 REF

0.25 DETAIL A DETAIL B 0.17/0.27 0.10 M 0.090/0.200

August 1999 TMPR28051 STS-1/AU-3 (STM-0) Mapper 75Lucent Technologies Inc.

Ordering Information

DS99-068SONT Re places DS98-100TIC to Incorporate the Following Updates 1. Page 1, added bulleted items concerning 3.3 V operation, and alarm and control standards. 2. Page5 , D e s c r i p t i o n (continued) section, replaced the Lucent T7690/T7693 Quad Line Transceiver interfacing device with the Lucent T7698FL3/T7693 Quad Line Transceiver. 3. Page5 , F igure 1, Block Diagram, clarified block flow. 4. Page 6, changed pin 184 and all corresponding references to TCK. 5. Page 7, clarified Pin 102. 6. Page1 0 , o rganized Nomenclature Assumptions section from the text at the beginning of the Description sec- tion. 7. Page 10—pa ge 19, clarified block descriptions. 8. Page 14, 2nd paragraph, corrected the explanation of the reduced H4 coding sequence format from “alternate between” to “take on the following values.” 9. Page 23—pa ge 36, updated register map. 10. Page3 7 — p age 59, updated register description text and placed text in tables. 11. Page4 2 , T a b l e, R egisters 0x00—0x16: Device-Level Control, Alarm, and Mask Bits, corrected the test pat- tern sequence for register XMT_PAT-0, bits 01 and 11 combinations. 12. Page 49, Table 18, Registers 0x33—0x4E: VT Drop Selection, corrected VTxDROP, bits 4 through 0, to VT_DROP [4:0]_[1:28]. 13. Page 54, Table 24, Registers 0x8A—0x8F: Digital Jitter Attenuator Controls, added the register default val- ues. 14. Page 65, Table 34, Absolute Maximum Ratings, updated table, including input and output voltages. 15. Page 65, Table 35, ESD Threshold Voltage, added parameters and values. 16. Page 66, Table 36, Recommended Operating Conditions, updated to list 3.3 V power dissipation for DS1 and E1. 17. Page 67, Table 38, Input Clock Specifications, added to the document. 18. Page 69, Table 40, Output Clock Specifications, added to the document. 19. Page 70, Transmit Sync Timing section, expanded and corrected. 20. Page7 1 , F igure 15, Bus Parallel Mode Receive Sync Timing, corrected pin name. 21. Page 75, updated device code. 22. TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 2 of the Device, TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 3 of the Device, TMPR28051 STS-1/AU-3 (STM-0) Mapper Device Advisory for Version 4 of the Device, TMPR28051 STS-1/AU-3 (STM-0) Data Addendum, included all printed advisories and an addendum through version 4, each published in April 1999, (AY99-026SONT, AY99-027SONT, AY99-028SONT, DA99-009SONT ). An advisory was not issued for version 1 of the device. Device Code Packa geT e m perature Comcode (Ordering Number ) TMPR28051-3-SL5 208-Pin SQFP –40 °C to +85 °C 108421678

For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, P A 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA P ACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent T echnologies (China) Co., Ltd., A-F2, 23/F , Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P . R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAP AN: Microelectronics Group, Lucent T echnologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, T okyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DA T ALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 T echnical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 600 7070 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), IT AL Y: (39) 02 6608131 (Milan), SP AIN: (34) 1 807 1441 (Madrid) Data Sheet TMPR28051 STS-1/AU-3 (STM-0) Mapper August 1999 Lucent T echnologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright © 1999 Lucent T echnologies Inc. All Rights Reserved August 1999 DS99-068SONT (Replaces DS98-100TIC)