W3000

W3000 AGERE | Alldatasheet

Document overview

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Technical content

Features

+ 2.2 GHz operational + Dual-band optimized + Low supply current (5.1 mA) + Surface-mount 14-pin TSSOP package + Scaled PD gain for dual-band operation + Programmable phase-detector polarity + Synchronous or forced counter update loading + Powerdown mode via external pin or serial bus + Low-load capacitance on reference input buffer

Applications

+ GSM900/1800/1900 + North American IS-136/137 + Personal Digital Cellular (Japan RCR-27) + Personal Handy Phone (Japan RCR-28) + CDMA (IS-95) PHASE DETECTOR REF_IN LD TCXO R 11-BIT COUNTER V DDC PRESCALER ÷ 64/65 MAIN_IN M 11-BIT COUNTER A 7-BIT COUNTER RREF HIGH-PRECISION CURRENT REFERENCE V DD C CONTROL LOGIC 24-BIT SERIAL SHIFT REGISTER LAT DAT CLK IPD SETTING PD POLARITY IR EF IR EF VCO BAND A VCO BAND B BAND IPD SETTING PD POLARITY V CP OFF CHIP Figure 1 . Block Diagram with Pinout

W3000 PLL Dual-Band Frequency Synthesizer December 1999 Lucent Technologies Inc.2 Table of Contents

December 1999 W3000 PLL Dual-Band Frequency Synthesizer Lucent Technologies Inc. 3

Description

The W3000 is a high-performance UHF RF PLL synthesizer, designed for use in digital wireless communication applications. Particular emphasis in the design has been placed on dual-band applications, with near-seamless switching between operational bands without the need for external loop-filter circuitry other than that required for single band applications. In combination with a suitable reference crystal, UHF VCO, and associated loop-filter components, the W3000 offers a very low-noise oscillator solution. The reference signal is divided by a programmable 11-bit counter to provide a wide range of comparison frequencies, allowing compliance with the various standards. The reference input is rising-edge triggered, and we recommend that an inverting buffer be used when the W3000 is interfaced to a commercial TCXO. The MAIN_IN signal normally associated with the UHF VCO is fed into a dual modulus prescaler (64/65) and is then divided by the 11-bit main counter to be compared to the output of the reference counter in a digital phase detector. The W3000 is implemented with programmable charge-pump currents to allow fast switching between bands for dual-band applications, without changing the loop filter. The charge pump can be programmed internally, or externally with a resistor (recommended). Charge pump outputs can be disabled, thereby allowing open-loop VCO modulation schemes. With synchronous reloading, the counter reloads a new programmed value when the counter reaches zero. With forced counter reloading, the reloading occurs when the programmed word is latched in. These techniques can improve lock time when performing a dual-band hop or in start-up conditions. The W3000 uses a standard 3-wire programming bus (data, enable, clock) that operates up to 10 MHz. This serial interface is via a 24-bit word that incorporates both register addressing and device addressing allowing two chips to share the bus. TR REGISTER CONFIG REGISTER MAIN REGISTER REF REGISTER MAIN REGISTER SC1 PARALLEL LATCH SERLE1 SERCK SERDASERIAL SHIFT ADDRESS DECODER ADDRESS DECODER PARALLEL LATCH A[0:2] CLK DAT SERIAL SHIFT A[0:2] LAT DAT CLK LAT W3020 W3000 Figure 2 . Serial Bus Programming

W3000 PLL Dual-Band Frequency Synthesizer December 1999 Lucent Technologies Inc.4 Pin Information V DDC CPOUT V SS 1 MAIN_IN LAT DAT LOCKDET REF_IN PWRDN CLK RES V SS 2 V D D 1 V D D 2 Figure 3 . Pin Diagram Table 1 . Pin Descriptions Pin Symbol Function Name/Description 1 V DDC Supply Charge Pump Positive Supply Voltage . Must be ≥V DD . (V DD = V DD 1 = V DD 2). 2 CPOUT Output Charge Pump Output . 3 V SS 1 Ground Ground 1 . Charge pump and logic ground. 4 V SS 2 Ground Ground 2 . Prescaler and reference ground. 5 MAIN_IN Input VCO Signal Input . Must be ac-coupled. 6 V DD 1 Supply Voltage Supply 1 . Prescaler supply voltage. 7 V DD 2 Supply Voltage Supply 2 . Logic and reference supply (must be equal to V DD 1). 8 LOCKDET Output Lock Detect Output. 9 RES Input External Resistor Input . Add resistor to V DD C if required (>10 k Ω ). 10 REF_IN Input Reference Frequency Input . Connection from reference oscillator. Must be ac- coupled. 11 PWRDN Input Powerdown . For low current operation. (Low is powerdown mode.) 12 CLK Input Serial Input . Programming clock line. 13 DAT Input Serial Input . Programming data line. 14 LAT Input Serial Input . Programming latch line.

December 1999 W3000 PLL Dual-Band Frequency Synthesizer Lucent Technologies Inc. 5 Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Symbol Min Max Unit Ambient Operating Temperature T A –30 85 °C Storage Temperature T stg –65 150 °C Lead Temperature (soldering, 10 s) T L — 300 °C Positive Supply Voltage V DD 0 4.5 Vdc Positive Charge Pump Supply Voltage V DDC 0 4.5 Vdc Power Dissipation P D — 250 mW ac Input Voltage — 0 V DD Vp-p Digital Voltages — Vss – 0.3 V DD + 0.3 Vdc Electrostatic Discharge Caution Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent Technologies Microelectronics Group employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance = 1500 Ω , capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. Parameter Model Min Max Unit ESD Threshold Voltage HBM 1000 — V ESD Threshold Voltage (corner pins) CDM 1000 — V ESD Threshold Voltage (noncorner pins) CDM 1500 — V

W3000 PLL Dual-Band Frequency Synthesizer December 1999 Lucent Technologies Inc.6

Electrical Characteristics

Table 2 . General Specifications Conditions (unless otherwise specified): V DD = 2.7 V; T A = 25 °C ± 3 °C; V REF = 0.25 Vp-p, V DDC = 2.85 V. Parameters Symbol Min Typ Max Unit Ambient Operating Temperature T A –30 25 85 °C Nominal Operating Voltage V DD 2.7 2.85 3.6 V Nominal Charge Pump Operating Voltage V DDC V DD 2.85 3.6 V Power Supply Current † IDD — 5.1 8.0 mA Powerdown Current ‡ IDD — 0.1 20 µA Digital Inputs: Logic High Voltage V IH 0.7 * V DD V DD V DD + 0.15 V Logic Low Voltage V IL – 0.3 GND 0.3 * V DD V Logic High Current (V IH = V DD + 0.15 V) |I IH | — — 10 µA Logic Low Current (V IL = –0.3 V) |I IL | — — 10 µA Digital Outputs: Logic High Voltage (|I OH | = 2 mA) V OH V DD – 0.4 — — V Logic Low Voltage (|I OL | = 2 mA) V OL — — 0.4 V † (I DD 1 + I DD 2 + I DD C) under locked condition, V DDC = 2.85 V; f VCO .= 1200 MHz; f REF = 13 MHz. ‡ (I DD 1 + I DD 2 + I DD C) V IL = 0 Vdc on all logic input pins. Table 3 . Electrical Specifications Conditions (unless otherwise specified): V DD = 2.7 V; T A = 25 °C ± 3 °C; V REF = 0.25 Vp-p, V DDC = 2.85 V. Parameter Symbol Min Typ Max Unit Main Input Frequency Range f VCO 0.5 — 2.2 GHz Main Input Level (1100 MHz—1750 MHz) V MAIN –20 — 6 dBm/50 Ω * Main Input Level † V MAIN –10 — 6 dBm/50 Ω * Reference Input Frequency Range f REF 8 — 30 MHz Reference Input Shunt Resistance — 20 30 — k Ω Reference Input Shunt Capacitance — — 1.2 3 pF Reference Input Slew Rate — 41 60 — mV/ns Reference Input Level V REF 0.25 — 2.00 Vp-p Phase Detector Comparison Frequency f COMP 0.025 — 2 MHz External Resistor Value (pin 9 to V DDC ) — 10 18 — k Ω Phase Detector Range — –2 π — 2 π rad. Phase Detector Noise Floor, ±150 Hz offset (25 kHz comparison frequency) ‡ — — –167 — dBc/Hz *Equivalent voltage of a 50 Ω terminated source. † Frequencies outside the 1100 MHz—1750 MHz range and up to and including 2200 MHz. ‡ f VCO = 1190 MHz; V REF = 1.4 Vp-p.

December 1999 W3000 PLL Dual-Band Frequency Synthesizer Lucent Technologies Inc. 7 Charge Pump Current D ICP -UP (T = 25 °C ) ICP /mA V CP 0.4 2.45 ICP -DN (T = 25 °C ) COMPLIANCE RANGE 0.4 V COMPLIANCE RANGE V DD C – 0.4 V V DD C /2 A: CP UP CURRENT AT V CP = V DDC – 0.4. B: CP UP CURRENT AT V CP = V DDC /2. C: CP UP CURRENT AT V CP = 0.4. F E A C B D: CP DOWN CURRENT AT V CP = 0.4 V. E: CP DOWN CURRENT AT V CP = V DDC /2. F: CP DOWN CURRENT AT V CP = V DDC – 0.4. Figure 4 . Charge Pump Current vs. Voltage Table 4 . Charge Pump Specifications Conditions (unless otherwise specified): V DD = 2.7 V; T A = 25 °C ± 3 °C; V DDC = 2.85 V; V CP = V DDC/ 2; R REF = 18 k Ω . Parameter Conditions Symbol Min Typ Max Unit ICP = 0.7 mA IUP 0.6 0.7 0.8 mA ICP = 0.7 mA IDN –0.8 –0.7 –0.6 mA ICP = 0.9 mA IUP 0.8 0.9 1.0 mA ICP = 0.9 mA IDN –1.0 –0.9 –0.8 mA ICP = 1.9 mA IUP 1.6 1.9 2.2 mA ICP = 1.9 mA IDN –2.2 –1.9 –1.6 mA ICP = 2.5 mA IUP 2.1 2.5 2.9 mA Charge Pump Output Current ICP = 2.5 mA IDN –2.9 –2.5 –2.1 mA CP High-Impedance State Current 0.4 < V CP < V DDC – 0.4 V, ITRI — 0.1 20 nA CP Sink vs. Source Mismatch 1 T A = 25 °C — — 3 15 % CP Current vs. Voltage 2 0.4 < V CP < V DDC – 0.4 V, T A = 25 °C — — 2 8.5 % CP Current vs Temperature 3 –30 °C < T A < +85 °C — — 8 10 % Notes (refer to Figure 4 for definitions): 1. ICP-DN vs ICP-UP = charge pump output current up vs down mismatch = [|E| – |B|]/[ 1/2 * {|E| + |B|}] * 100%. 2. ICP vs VCP = charge pump output current magnitude variation vs voltage = [ 1/2 * {|F| – |D|}]/[1/2 * {|F| +|D|}] * 100% and 3. ICP vs TA = charge pump output current magnitude variation vs. temperature = [|E @ temp| – |E @ 25 °C|]/|E @ 25 °C| * 100% and [|B @

W3000 PLL Dual-Band Frequency Synthesizer December 1999 Lucent Technologies Inc.8 PLL Programming Information The oscillator frequency is selected according to the following expression: [ ] R f*A)M* P(f REFVCO += where: fVCO = VCO frequency P/(P + 1) = Dual modulus prescaler M = Programmable counter ratio (2 to 2047), M > A A = Swallow counter ratio (0 to M – 1 or 127) fREF = External reference oscillator frequency R = Reference counter rati o (2 to 2047) Example You wish to have a VCO operating at 1172 MHz, ability to step the frequency in 200 kHz steps, and a reference clock at 13 MHz. Step 1: Calculate the reference counter ratio R 65kHz 200 MHz 13R == Step 2: Calculate M & A [ ] R f* A)M* P(f REF VCO [ ] 586013 65*1172)AM*64( ==+ 369164 5860 = M is an integer, and so is A; therefore, M = 91, and A = 36.

December 1999 W3000 PLL Dual-Band Frequency Synthesizer Lucent Technologies Inc. 9 Serial Data Input The PLL is programmed via a 3-wire serial bus, utilizing a data pin (DAT), a clock pin (CLK), and a latch pin (LAT). Serial Bus Timing Information tCS tCH tLWH tLS V MSB LSBMSB – 1 DAT CLK tLL tCWHtCWL LAT OR LAT t Figure 5 . Serial Bus Timing Diagram Table 5 . Serial Bus Timing Information Symbol Parameter Min Typ Max Unit tCS Data to Clock Setup Time 33 — — ns tCH Data to Clock Hold Time 10 — — ns tCWH Clock Pulse Width High 33 — — ns tCWL Clock Pulse Width Low 33 — — ns tLS Clock Falling Edge to Latch High Setup Time 0 — — ns tLWH Latch Pulse Width 50 — — ns tLL Latch to Clock Setup Time 33 — — ns f CLK Clock Input Frequency — — 10 MHz

W3000 PLL Dual-Band Frequency Synthesizer December 1999 Lucent Technologies Inc.10 Functional Descriptions The W3000 contains a reference register (REF) and a main register (MAIN). The REF register is used for programming the division ratio of the reference clock and for initial setup of the operation modes. The MAIN register is intended for programming that can occur frequently, e.g., dynamic channel switching and putting the W3000 into power-saving mode. SHIFT REGISTER ADDRESS DECODER LAT DAT CLK MAIN REF Figure 6 . Register Programming Diagram Both REF and MAIN registers are programmed separately, each with a 24-bit data sequence. The last bit is that which immediately precedes a low-to-high latch input transition occurring while the CLOCK input is low. Bit 24 is loaded first, and bit 1 is loaded last. The last bit in the serial sequence is C0. This bit is used to direct the 24-bit sequence to the MAIN or REF registers. Table 6 . C0:C1: MAIN and REF Register Addressing (Destination of Serial Data) (Bits 1 and 24) C1 C0 Addressed Register 0 0 MAIN 0 1 REF 1 0 Secondary Address 1 1 Secondary Address The first bit, C1, allows the W3000 to share the serial bus. When C1 is a logic high, the W3000 ignores the data sent on the serial bus.

December 1999 W3000 PLL Dual-Band Frequency Synthesizer Lucent Technologies Inc. 11 REF Register This section describes each bit of the reference register. The REF register is used for programming the division ratio of the reference clock and for initial setup of the operation modes. Table 7 . REF Register Bit Description (C0 = 1, C1 = 0) Bit Name Description 1 C0 = 1 Register address bit. C0 = 1 for REF (last bit in serial sequence). 2:12 R[1:11] Reference frequency divide ratio. 13 D1 Forced counter reload programming (synchronous/asynchronous). 14 D2 Charge pump disable function. 15:16 D3, D4 Programable charge pump current for frequency band 2. 17 D5 Phase detector polarity. 18:19 D6, D7 Programable charge pump current for frequency band 1. 20 RE Reset for first programming after powerup (1 = reset). 21 ERES Enables external resistor (on RES pin) to set charge pump current. 22 EN1 Enable W3000. (0 is powerdown.) 23 LD Lock detect output enable. 24 C1 = 0 Secondary address bit (first bit in serial sequence). Table 8 . REF Register 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 = 1 R R R R R R R R R R R D D D D D D D RE ERES EN LD C1 = 0 Table 9 . R1:R11: Reference Divider Ratio (Bits 2 to 12) R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 Divide Ratio R 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 1 1 3 1 1 1 1 1 1 1 1 1 1 1 2047 *The reference counter cannot operate with division numbers less than 2. Last bit in serial sequence First bit in serial sequence

W3000 PLL Dual-Band Frequency Synthesizer December 1999 Lucent Technologies Inc.12 REF Register (continued) Table 10 . D1: Forced Counter Reload (Bit 13) D1 Response

0 Synchronous counter reloading update

1 Forced counter reload (M, R, A)

With synchronous reloading, the counter reloads a new programmed value when the counter reaches zero. With forced counter reloading, the reloading occurs when the programmed word is latched in. This can improve lock time when performing a dual-band hop. Table 11 . D2: Charge Pump Off Mode (Bit 14) D2 Response

0 Charge pump enabled

1 Charge pump off (high impedance)

This allows the disabling of the charge pump for systems that directly modulate an open-loop VCO. Table 12 . Band and Charge Pump Current (Band 1, Bits 18 and 19; Band 2, Bits 15 and 16) Band D3 Bit 15 Bit 16 Bit 18 Bit 19 Charge Pump Current ISET 1 x x 0 0 0.7 mA 1 x x 1 0 0.9 mA 1 x x 0 1 1.9 mA 1 x x 1 1 2.5 mA 2 0 0 x x 0.7 mA 2 1 0 x x 0.9 mA 2 0 1 x x 1.9 mA 2 1 1 x x 2.5 mA The charge pump current is selected by bit 23 of the MAIN register. Setting bit 23 to a 0 will select band 1, which is established with bits 18 and 19 of the REF register. Likewise, setting bit 23 to a 1 will select band 2, which is established with bits 15 and 16 of the REF register. This allows the charge pump current to be dynamically changed along with the VCO frequency. The PLL loop natural frequency is proportional to charge pump current and inversely proportional to the N count. Therefore, when the ratio of charge pump current and VCO frequency is the same, the loop natural frequency does not change. This allows the same loop filter to be used for two different VCO frequencies. For example, in a GSM900/1800 system with VCOs running at 1190 MHz/1570 MHz, the current could be set to 1.9 mA for GSM900 and 2.5 mA for GSM 1800 to compensate for the change in division ratios. The current setting may also be determined by an external resistor. (See Table 15 .) In that case, the ratio between the currents programmed will stay the same, but the absolute level will be resistor-dependent.

December 1999 W3000 PLL Dual-Band Frequency Synthesizer Lucent Technologies Inc. 13 REF Register (continued) Table 13 . D5: Phase Detector Polarity (Bit 17) D5 Phase Detector Polarity

0 Negative slope

1 Positive slope

The phase detector can be programmed for either a negative or positive slope to accommodate the VCO and low-pass filter characteristics. (See Figure 7 .) LOOP FILTER REFERENCE W3000 VCO VCO OUTPUT FREQUENCY VCO INPUT CONTROL VOLTAGE Figure 7 . Programming the Phase Detector Slope Table 14 . RE: Reset (Bit 20) RE Response

0 Operation mode

1 Reset MAIN and secondary registers

After the power supply is turned on, the REF register must be programmed with a reset. This must be followed by a programming of the MAIN register before or at the enabling of the PLL circuit. The RE bit will clear itself, and is required to ensure correct initialization of the IC. This results in the following conditions: + The RE bit is cleared back to 0. + The device is in powerdown mode, since the EN[1:2] bits are also cleared. + Previous reference and main counter values are maintained.

W3000 PLL Dual-Band Frequency Synthesizer December 1999 Lucent Technologies Inc.14 REF Register (continued) Table 15 . ERES: External Resistor Setting for Charge Pump Current (Bit 21) ERES External Resistor Status

0 Use internal charge pump current setting (not tested in production)

1 Use external resistor to set charge pump current (recommended)

If bit 21 is set to 0, the W3000 uses its internal current source to set the charge pump currents, with the values shown in Table 12 . If bit 21 is set to 1, the charge pump current is set by an external resistor between pin 9 (RES) and V DDC . In this case, the charge pump current is given by the following formula: REF DDC SETCP R *A 100 05.1V*II µ where ICP = Nominal charge pump current. ISET = Current setting as in Table 12 . RREF = Value of external current reference resistor. See Table 3 for appropriate value. A tight-tolerance R REF resistor is recommended. Table 16 . EN1: Synthesizer Enable (Bit 22) PWRDN (Input Pin 11) EN1 Mode High 0 Powerdown High 1 Enable Low 0 Powerdown Low 1 Powerdown The MAIN register also contains an enable bit, EN2. The W3000 is enabled and powered down with either the REF or the MAIN register, whichever was programmed more recently. The contents of the MAIN and REF registers are maintained in powerdown mode, providing supply voltages are maintained. Table 17 . LD: Lock Detect Enable (Bit 23) LD (Bit 23) Mode PLL Condition Output Level on Pin 8 LockDet

0 Disabled Locked High

0 Disabled Unlocked High

1 Enabled Locked High

1 Enabled Unlocked Low

December 1999 W3000 PLL Dual-Band Frequency Synthesizer Lucent Technologies Inc. 15 MAIN Register The MAIN register is intended for programming that can occur frequently for dynamic channel switching and putting the W3000 into power-saving mode. Table 18 . MAIN Register Bit Description (C0 = 0, C1 = 0) Bit Name Description 1 C0 = 0 Register address bit. C0 = 0 for MAIN (last bit in serial sequence). 2:8 A[1:7] Swallow counter for prescaler modulus control. 9:19 M[1:11] Main counter.

20 Reserved —

21 Reserved —

22 EN2 Enable all PLL circuits (0 = powerdown mode). 23 B Band select for charge pump current control (band 1 = 0, band 2 = 1). 24 C1 = 0 Secondary address bit. Table 19 . MAIN Register 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 = 0 A A A A A A A M M M M M M M M M M M X X EN B C1 = 0 Note: X bits are don’t care bits. Table 20 . A1:A7: Swallow Counter Count (Bits 2 to 8) Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Counter Ratio 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 2 0 1 1 1 1 1 1 63 1 1 1 1 1 1 1 127 Last bit in serial sequence First bit in serial sequence

W3000 PLL Dual-Band Frequency Synthesizer December 1999 Lucent Technologies Inc.16 MAIN Register (continued) Table 21 . M1:M11: Programmable Main Counter Divide Ratio (Bits 9 to 19) M11 Bit 19 M10 Bit 18 Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Divide Ratio M 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 1 1 3 0 0 0 1 1 1 1 1 1 1 1 255 1 1 1 1 1 1 1 1 1 1 1 2047 The main counter divides the frequency of the prescaler output signal and sources the divided signal to the phase comparator. Table 22 . EN2: Synthesizer Enable (Bit 22) PWRDN EN2 Mode H 0 Powerdown H 1 Enable L 0 Powerdown L 1 Powerdown The REF register also contains an enable bit, EN1 (see Table 16 ). The W3000 is enabled or powered down with either the REF or MAIN register, whichever was programmed more recently. The contents of the MAIN and REF registers are maintained in powerdown mode, providing supply voltages are maintained. Table 23 . B: Band Select (Bit 23) B Band

0 Band 1

1 Band 2

In dual-band operation, this bit allows the use of one loop filter by setting the charge pump current to correspond to the frequency of the band selected. See Table 12 for the available charge pump current settings.

December 1999 W3000 PLL Dual-Band Frequency Synthesizer Lucent Technologies Inc. 17 PLL Lock-Detect Function The W3000 provides a basic lock-detect function for fault finding or for system specification requirements. Inside the W3000, the length of the up or down pulses applied to the loop filter is compared with a reference clock period. If the current pulses are shorter than a reference clock period for 15 consecutive comparison periods, the LD line is asserted. If a current pulse is detected that is longer than a reference clock period, the LD line is unset. The LD line gives a signal to indicate a PLL fault condition. It does not provide a true loop-locked output. For example, in a GSM system with a reference clock of 13 MHz and a comparison frequency of 200 kHz, the current pulses only have to be less than 1/65 of a cycle for 15 consecutive times for the LD line to be asserted. This equates to ~0.4º of phase. In the worst case, if the phase stays inside this limit, moving from one extreme to the other, the frequency will only be within 0.2%, i.e., 4 MHz on a 2 GHz VCO. The LD output from the W3000 is a standard logic signal and requires no external comparison or R-C filters. Typical Performance Characteristics UHF SOURCE 0.047 µ F 100 pF +V DD C 100 pF +V DD µC REFERENCE SOURCE 0.01 µF

10 MHz REF

442 Ω CURRENT METER V DD C /2 50 Ω 6.8 pF 50 Ω LAT DAT CLK PWRDN REF_IN LOCK DET RES V DD C CPOUT V S S 1 V S S 2 MAIN_IN V D D 2 V D D 1 RREF = 18 k Ω V DD C Figure 8 . MAIN_IN and REF_IN Sensitivity Test Circuit Diagram MAIN_IN and REF_IN are set to cause a small beat frequency at the phase detector input. This generates a sawtooth signal at the charge pump output of known slope. The amplitude of the UHF source is decreased. The sensitivity limit is reached when the slope of this waveform deviates from the calculated value. This is then repeated for the reference source.

W3000 PLL Dual-Band Frequency Synthesizer December 1999 Lucent Technologies Inc.20 Application Information (continued) General rules for the values of these components have been derived many times 1 , and are quoted here merely for reference. If: p tansec1T ω φ−φ= )3T1T(* 12T 2 c +ω 2REF 20/attn )F*2( 1103T π where φ = Phase margin required, normally 45° for a critically damped response. pω = Loop bandwidth. cω = Loop bandwidth modified for extra pole of R3 and C3, as described by: ( ) ( ) [ ]  +++ +φ=ω 1 )3T1T(*tan 3T*1T)3T1T(1* T3*T1 T3) (T1 T3) (T1 * tan f REF = Reference frequency. atten = Attenuation provided by the third pole at the reference frequency. The loop filter values can then be derived as: c c c c PD )3T*1)(1T*1( )2T*1(* Kvco*K*2T 1T1C ω+ω+ ω  −= 11T 2T * 1C2C 2T1R = The final pole, consisting of R2 and C3, should be chosen such that the following guidelines are followed: 1C3C ≤ and 1R * 22R ≥ 1 . Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design , Prentice-Hall, 1983.

December 1999 W3000 PLL Dual-Band Frequency Synthesizer Lucent Technologies Inc. 21 Application Information (continued) For example, take a GSM application where a loop bandwidth of 22 kHz is required. Other parameters specified by the system are listed below: Parameter Value VCO Gain (K VCO) 88 MHz/V Charge Pump Current (I CP) 2.5 mA Divider Ratio (value of midband frequency used) (N) 7850 Required Phase Margin 45° Reference Frequency Attenuation from Additional Pole 20 dB Using the formulas above, the three time constants can be calculated as follows: T1 = 2.63697E – 10 –6 s T2 = 3.14484E – 10 –5 s T3 = 2.38732E – 10 –6 s From these values, we can derive the initial component values as follows: R1 = 2992 Ω C1 = 0.96 nF C2 = 10.5 nF If we choose R2 = 15 k Ω , then C3 = 159 pF From these initial values, the loop filter components used in the application circuit can be derived through practical optimization.

December 1999 W3000 PLL Dual-Band Frequency Synthesizer Lucent Technologies Inc. 23 Typical Performance Data (continued) SENSITIVITY MAX I/P LEVEL 0 500 1000 1500 2000 2500 3000 FREQUENCY (MHz) LEVEL (dBm) –40 –30 –20 –10 Figure 17 . Prescaler Sensitivity and Maximum Input Level 1.0 2.0 5.0 inf –5.0 –2.0 –1.0 –0.5 0.2 0.0 –0.2 0.5

2.2 GHz

500 MHz

Figure 18 . Input Impedance Smith Chart: 0.5 GHz to 2.2 GHz Frequency 100 1 k 10 k 100 k Start: 62.5 Hz Stop: 100 kHz TRACE A: F1 PSD1/K1 A Marker –83.245 dB* 1 750.0 Hz Y* = radrms 2 /Hz RMS: 18.551 mradrms Ch1 Carrier: 1.1900005 GHz –50 dB* –150 dB* LogMag 10 dB/div Figure 19 . Phase Noise 1190 MHz, Fcomp = 200 kHz V DD = V DDC = 2.85 V

December 1999 W3000 PLL Dual-Band Frequency Synthesizer Lucent Technologies Inc. 25 Typical Performance Data (continued) Figure 22 . Dual-Band Locking

W3000 PLL Dual-Band Frequency Synthesizer December 1999 Lucent Technologies Inc.26 Outline Diagram 14-Pin TSSOP Dimensions are in millimeters. 4. 3/ 4. 5 SEE DET AIL A 0. 09 0/ 0. 20 0.9 0 ± 0 .05 -E- 1. 0 0 1. 0 0 1. 0 0 8 14 7 1 0. 2 5 4 EM M 6. 25 / 6. 5 BA SE M E TA L WITH PLATI NG DE TA IL C 0. 90 /0 .1 35 0. 09 0/ 0. 20 0. 2 2 ± 0. 0 3 0. 19 / 0. 3 0 SE AT IN G PL A N E DE TA IL C 0. 0 7 6 C 0. 65 BS C 1. 1 0 M A X 0. 1 5 M A X 5. 0 ± 0. 10 0. 25 BC S DE TA IL A 0. 60 ± 0 . 108 DE TA IL C DET AI L G 5-5462 C

December 1999 W3000 PLL Dual-Band Frequency Synthesizer Lucent Technologies Inc. 27 Manufacturing Information This device will be assembled in multiple locations, which include assembly codes P, M, and T.

Ordering Information

Device Code Description Package Comcode LUCW3000CCN W3000 PLL Frequency Synthesizer Sticks 14-pin TSSOP 108417601 LUCW3000CCN-TR W3000 PLL Frequency Synthesizer Tape and Reel 14-pin TSSOP 108417619 Note: Contact your Lucent Technologies Microelectronics Group Account Manager for minimum order requirements .

For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447 , FAX 610-712-4106 (In CANADA: 1-800-553-2448 , FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent T echnologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833 , FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Sh an Xi Road, Shanghai 200233 P.R. China Tel. (86) 21 6440 0468, ext. 316 , FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600 , FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368 , FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: ( 34) 1 807 1441 (Madrid) Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright © 1999 Lucent Technologies Inc. All Rights Reserved Printed in U.S.A. December 1999 DS99-058WRF (Replaces DS97-268WRF)