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UT0.6CRCommercial RadHardTM Gate Array Family Data Sheet May 2014 www.aeroflex.com/RadHardASIC
FEATURES
Multiple gate array sizes up to 500,000 usable equivalent gates Toggle rates up to 150 MHz Advanced 0.60.5Leffradiation-tolerant silicon gate CMOS processed in a commercial fab Operating voltage of 5V and/or 3.3V QML Class Q & V compliant Designed specifically for high reliability applications Commercial RadHardTM for radiation-tolerant to 300 krads(Si) to meet space requirements and SEU-immune to less than 2.0E-10 errors/bit-day JTAG (IEEE 1149.1) boundary-scan supported Low noise package technology for high speed circuits Design support using Mentor Graphics® and SynopsysTM in VHDL or Verilog design languages on Sun® and Linux workstations Supports cold sparing for power down applications Supports voltage translation - 5V bus to 3.3V bus - 3.3V bus to 5V bus PRODUCT DESCRIPTION The high-performance UT0.6CRH gate array family features densities up to 500,000 equivalent gates and is avail- able in MIL-PRF-38535 QML Q and V product assurance levels and is radiation-tolerant. The Commercial RadHardTM silicon is fabricated at ON Semi- conductor using a minimally invasive processing module, developed by Aeroflex, that enhances the total dose radiation hardness of the field and gate oxides while maintaining circuit density and reliability. In addition, for both greater transient radiation-hardness and latchup immunity, the Aeroflex 0.6 process is built on epitaxial substrate wafers. Developed using Aeroflex’s patented architectures, the UT0.6CRH gate array family uses a highly efficient continu- ous column transistor architecture for the internal cell construction. Combined with state-of-the-art placement and routing tools, the utilization of available transistors is maxi- mized using three levels of metal interconnect. The UT0.6CRH family of gate arrays is supported by an ex- tensive cell library that includes SSI, MSI, and 54XX equivalent functions, as well as configurable RAM and cores. Aeroflex’s core library includes the following functions: Intel 80C31® equivalent Intel 80C196® equivalent MIL-STD-1553 functions (BRCTM, RTI, RTMP) MIL-STD-1750 microprocessor RISC microcontroller Configurable RAM (SRAM, DPSRAM) USART (82C51) EDAC Aeroflex Gaisler We offer Aeroflex Gaisler LEON3 and other IP which can be reviewed at www.gaisler.com/CMS
Table 1. Gate Densities
- Based on NAND2 equivalents. Actual usable gate count is design-dependent. Estimates reflect a mix of functions including RAM.
- Includes five pins that may or may not be reserved for JTAG boundary-scan, depending on user requirements.
- Reserved for dedicated VDD/VSS and VDDQ/VSSQ.
4.Aeroflex offers four die sizes: KD (280 mils), KC (407 mils), KB (535 mils), and KM (677 mils).
Table 2. Packages
- The number of device I/O pads available ma y be restricted by the selected package.
- PGA packages have one additio nal non-connected index pin (i.e., 84 + 1 index pin = 85 total package pins for the 85 PGA).
Contact Aeroflex for specific package drawings.
84 X X
132 X X
172 X X X X X X
196 X X X X X X
208 X X
256 X X X X X X X X X X X X
304 X X X X
352 X X X X X
299 X X X X
472 X X X X X
The UT0.6CRH family of gate arrays is supported by an exten- sive cell library that includes SSI, MSI, and 54XX-equivalent functions, as well as RAM and other library functions. User-se- lectable options for cell configurations include scan for all register elements, as well as output drive strength. Aeroflex’s core library includes the following functions: Intel® 80C31 equivalent Intel® 80C196 equivalent MIL-STD-1553 functions (RTI) MIL-STD-1750 microprocessor Standard microprocessor peripheral functions Configurable RAM (SRAM, DPSRAM) RISC Microcontroller USART (82C51) EDAC Aeroflx Gaisler IP Refer to Aeroflex’s UT0.6CRH Design Manual for complete cell listing and details. I/O Buffers The UT0.6CRH gate array family offers up to 544 signal I/O locations (note: device signal I/O availability is affected by pack- age selection and pinout.) The I/O cells can be configured by the user to serve as input, output, bidirectional, three-state, or addi- tional power and ground pads. Output drive options range from 2 to 12mA. To drive larger off-chip loads, output drivers may be combined in parallel to provide additional drive up to 24mA. Other I/O buffer features and options include: Slew rate control Pull-up and pull-down resistors TTL, CMOS, and Schmitt levels Cold sparing V oltage translation - 5V bus to 3.3V bus - 3.3V bus to 5V bus JTAG Boundary-Scan The UT0.6CRH arrays provide for a test access port and bound- ary-scan that conforms to the IEEE Standard 1149.1 (JTAG). Some of the benefits of this capability are: Easy test of complex assembled printed circuit boards Gain access to and control of internal scan paths Initiation of Built-In Self Test Clock Driver Distribution Aeroflex design tools provide methods for balanced clock distri- bution that maximize drive capability and minimize relative clock skew between clocked devices. Speed and Performance Aeroflex specializes in high-performance circuits designed to op- erate in harsh military and radiation environments. Table 3 presents a sampling of typical cell delays. Note that the propagation delay for a CMOS device is a function of its fanout loading, input slew, supply voltage, operating tem- perature, and processing radiation tolerance. In a radiation environment, additional performance variances must be consid- ered. The UT0.6CRHarray family simulation models account for all of these effects to accurately determine circuit performance for its particular set of use conditions. Power Dissipation Each internal gate or I/O driver has an average power consump- tion based on its switching frequency and capacitive loading. Radiation-tolerant processes exhibit power dissipation that is typ- ical of CMOS processes. For a rigorous power estimating methodology, refer to the Aeroflex UT0.6CRH Design Manual or consult with an Aeroflex Applications Engineer. Typical Power Dissipation 1.1W/Gate-MHz@5.0V 0.4W/Gate-MHz@3.3V
Using a combination of state-of-the-art third-party and proprietary design tools, Aeroflex delivers the CAE support and capability to handle complex, high-performance ASIC designs from design concept through design verification and test. Aeroflex’s flexible circuit creation methodology supports high level design by providing UT0.6CRH libraries for Mentor Graphics and Synopsys synthesis tools. Design verification is performed in any VHDL or Verilog simulator or the Mentor Graphics environment, using Aeroflex’s robust libraries. Aeroflex also supports Automatic Test Program Generation to improve design testing. Aeroflex HDL DESIGN SYSTEM Aeroflex offers a Hardware Description Language (HDL) design system supporting VHDL and Verilog. Both the VHDL and Verilog libraries provide sign-off quality models and robust tools. The VHDL libraries are VITAL 3.0 compliant, and the Verilog libraries are OVI 1.0 compliant.With the library capabilities Aeroflex provides, you can use High Level Design methods to synthesize your design for simulation. Aeroflex also provides tools to verify that your HDL design will result in working ASIC devices. Aeroflex’s HDL design system lets you easily access Aeroflex’s RadHard capabilities. ADV ANTAGES OF THE AEROFLEX HDL DESIGN SYSTEM
- The Aeroflex HDL Design System gives you the freedom to use tools from Synopsys, Mentor Graphics, Cadence, and other vendors to help you synthesize and verify a design.
- Aeroflex’s Logic Rules Checker and Tester Rules Checker allow you to verify partial or complete designs for compliance with Aeroflex design rules.
- Aeroflex HDL Design System accepts back-annotation of timing information through SDF.
- Your design stays entirely within the language in which you started (VHDL or Verilog) preventing conversion headaches. XDT sm (eXternal Design Translation) Through Aeroflex’s XDT services, customers can convert an existing non-Aeroflex design to Aeroflex’s processes. The XDT tool is particularly useful for converting an FPGA to an Aeroflex radiation-tolerant gate array. The XDT translation tools convert industry standard netlist formats and vendor libraries to Aeroflex formats and libraries. Industry standard netlist formats supported by Aeroflex include:
- VHDL
- Verilog HDL TM
- FPGA source files (Actel, Altera, Xilinx)
- E D I F
- Third-party netlists supported by Synopsys Mentor ModelSim HDL Tool Supplier Completed ASIC Design Cadence NSIM Verilog XL VCS Synopsys VSS/VCS High Level Design Activities Aeroflex HDL Design System Aeroflex HDL Design Flow Aeroflex Gaisler IP
AEROFLEX MENTOR GRAPHICS DESIGN SYSTEM The Aeroflex Mentor Graphics Design System software is fully integrated into the Mentor Graphics design environment, making it familiar and easy to use. Aeroflex tools support Mentor functions such as cross-highlighting, graphical menus, and design navigation. After creating a design in the Mentor Graphics environment, you can easily verify the design for electrical rules compliance with the Aeroflex Logic Rules Checker. Testability can be verified with the Aeroflex Tester Rules Checker. Both of these tools are fully integrated into the Mentor Graphics Environment. When you have completed all design activities, Aeroflex’s Design Transfer tool captures all the required files and prepares them for easy transfer to Aeroflex. Aeroflex uses this data to convert your design into a packaged and tested device. ADV ANTAGES OF THE AEROFLEX MENTOR DESIGN SYSTEM
- Aeroflex customers have succe ssfully used the Aeroflex Mentor Graphics Design System for over a decade.
- Aeroflex’s Logic and Tester Rules Checker tools allow you to verify partial or complete designs for compliance with Aeroflex manufacturing practices and procedures.
- The Design System accepts pre-and post-layout timing information to ensure your design results in devices that meet your specifications.
- The Design System supports Leonardo, and database transfer between Synopsys and Mentor.
- The Design System supports powerful Mentor Graphics ATPG capabilities. TOOLS SUPPORTED BY AEROFLEX Aeroflex supports libraries for:
- Mentor Graphics
- ModelSim
- T e s s e n t
- Synopsys
- Design Compiler
- PrimeTime
- Formality
- T e t r a M a x
- VITAL-compliant VHDL Tools
- OVI-compliant Verilog Tools TRAINING AND SUPPORT Aeroflex personnel conduct training classes tailored to meet individual needs. These classes can address a wide mix of engineering backgrounds and specific customer concerns. Applications assistance is also available through all phases of ASIC Design. Design Manufacturing Aeroflex Mentor Design System Translate an External Design Convert an FPGA Schematic Entry Synthesis Design Idea Aeroflex Mentor Graphics Design Flow Aeroflex Gaisler IP
Table 3. Typical Cell Delays
- All specifications in ns (typical). Output load capacitance is 50pF. Fanout loading for input buffers and gates is the equivalent of two gate input loads.
Using three layers of metal interconnect, Aeroflex achieves optimized layouts that maximize speed of critical nets, overall chip performance, and design density up to 500,000 equivalent gates. Test Capability Aeroflex supports all phases of test development from test stim- ulus generation through high-speed production test. This support includes ATPG , fault simulation, and fault grading. Scan design options are available on all UT0.6CRH storage ele- ments. Automatic test program development capabilities handle large vector sets for use with Aeroflex’s Teradyne Tiger tester supporting high-speed testing (up to 1.2GHz with pin multiplexing). Unparalleled Quality and Reliability Aeroflex is dedicated to meeting the stringent performance re- quirements of aerospace and defense systems suppliers. Aeroflex maintains the highest level of quality and reliability through our Quality Management Program under MIL-PRF- 38535 and ISO-9001. In 1988, we were the first gate array man- ufacturer to achieve QPL certification and qualification of our technology families. Our product assurance program has kept pace with the demands of certification and qualification. Our quality management plan includes the following activities and initiatives. Quality improvement plan Failure analysis program SPC plan Corrective action plan Change control program Standard Evaluation Circuit (SEC) and Technology Charac- terization Vehicle (TCV) assessment program Certification and qualification program Because of numerous product variations permitted with custom- er specific designs, much of the reliability testing is performed using a Standard Evaluation Circuit (SEC) and Technology Characterization Vehicle (TCV). The TCV utilizes test struc- tures to evaluate hot carrier aging, electromigration, and time dependent test samples for reliability testing. Data from the wa- fer-level testing can provide rapid feedback to the fabrication process, as well as establish the reliability performance of the product before it is packaged and shipped. Radiation Tolerance Aeroflex incorporates radiation-tolerance techniques in process design, design rules, array design, power distribution, and li- brary element design. All key radiation-tolerance process parameters are controlled and monitored using statistical meth- ods and in-line testing. Notes: 1. Total dose Co-60 testing is in accordance with MIL-STD-883, Method 1019. Data sheet electrical characteristics guaranteed to 1.0E5 rads(SiO2). All post-radiation values measured at 25C. 2. Total dose Co-60 testing is in accordance with MIL-STD-883, Method 1019 at dose rates <1 rad(SiO2)/s. 3. Short pulse 20ns FWHM (full width, half maximum). 4. Is design dependent; SEU limit based on standard evaluation circuit at 4.5V worst case condition. 5. SEU-hard flip-flop cell. Non- hard flip-flop typical is 4E -8. PARAMETER RADIATION TOLERANCE NOTES Total dose 1.0E5 rad(SiO2) 3.0E5 rad(SiO2) Dose rate upset 1.0E8 rad(Si)/sec 3 Dose rate survivability 1.0E11 rad(Si)/sec 4 SEU <2.0E-10 errors per cell-day 4, 5 Projected neutron fluence 1.0E14 n/sq cm Latchup Latchup-immune over speci- fied use conditions
ABSOLUTE MAXIMUM RATINGS 1 (Referenced to VSS) Note: 1. Stresses outside the listed absolute maxi mum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS VDD DC supply voltage -0.3 to 6.0V VI/O V oltage on any pin -0.3V to VDD + 0.3 TSTG Storage temperature -65 to +150C TJ Maximum junction temperature +175C ILU Latchup immunity 150mA II DC input current 10mA TLS Lead temperature (soldering 5 sec) +300C SYMBOL PARAMETER LIMITS VDD Positive supply voltage 3.0 to 5.5V TC Case temperature range -55 to +125C VIN DC input voltage 0V to VDD
5V DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT VIL
3 Low-level input voltage
VDD = 4.5V and 5.5V 0.8 .3VDD V VIH
3 High-level input voltage
VDD = 4.5V and 5.5V 2.2 .7VDD V VT+3 Schmitt Trigger, positive going threshold VDD = 4.5V and 5.5V .2.4 7VDD V VT-3 Schmitt Trigger, negative going threshold VDD = 4.5V and 5.5V 0.9 .3VDD V VH 4 Schmitt Trigger, typical range of hysteresis 0.4 0.6 V IIN Input leakage current TTL, CMOS, and Schmitt inputs Inputs with pull-down resistors Inputs with pull-down resistors Inputs with pull-up resistors Inputs with pull-up resistors Cold Spare Inputs - Normal Mode Cold Spare Inputs - Cold Spare Mode VDD = 5.5V VIN = VDD and VSS VIN = VDD VIN = VSS VIN = VSS VIN = VDD VIN = 0 to 5.5V VDD = VSS = 0V VIN = V and 5.5V +20 -225 +225 -20 VOL Low-level output voltage TTL 2.0mA buffer TTL 4.0mA buffer TTL 8.0mA buffer TTL 12.0mA buffer * CMOS outputs CMOS outputs (optional) CMOS outputs (cold spare) VDD = 4.5V IOL = 2.0mA IOL = 4.0mA IOL= 8.0mA IOL = 12.0mA IOL = 1.0A IOL = 100A IOL = 100A 0.4 0.4 0.4 0.4 0.05 0.25 0.25 V VOH High-level output voltage TTL 2.0mA buffer TTL 4.0mA buffer TTL 8.0mA buffer TTL 12.0mA buffer * CMOS outputs CMOS outputs (optional) CMOS outputs (cold spare) VDD = 4.5V IOH = -2.0mA IOH = -4.0mA IOH = -8.0mA IOH = -12.0mA IOH = -1.0A IOH = -100A IOH = -100A 2.4 2.4 2.4 2.4 V DD-0.05 VDD-0.35 VDD-0.35 V
Notes: * Contact Aeroflex prior to usage. shall be specified in the AID. 2. Devices are supplied to this drawing will meet all levels M, D, P, L, R and F of irradiation. However, this device is only tested at the "R" and "F" level. Pre and Post irradiation values are identical unless otherwise specified in Table 1. When performing post irradiation electrical measurements for any RHA level, TA = +25oC. SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT IOZ Three-state output leakage current TTL 2.0mA buffer TTL 4.0mA buffer, CMOS TTL 8.0mA buffer TTL 12.0mA buffer * Cold Spare Inputs - normal mode Cold Spare Inputs - cold spare mode VDD = 5.5V VO = 0V and 5.5V VDD = VSS = 0 VDD = 0 to 5.5V -10 -20 -30 IOS 4,5 Short-circuit output current TTL 2.0mA buffer TTL 4.0mA buffer, CMOS TTL 8.0mA buffer TTL 12.0mA buffer * VO = 0V and 5.5V -50 -100 -200 -300 100 200 300 mA IDDQ Quiescent Supply Current6 Group A subgroups 1,3 VDD = 5.5V 200K gates 400K gates 500K gates 100 180 Group A subgroup 2 VDD = 5.5V 200K gates 400K gates 500K gates mA Group A, subgroup 1 RHA Designator: M, D, P, L, R,F VDD = 5.5V 200K gates 400K gates 500K gates mA CIN
7 Input capacitance 23 pF
7 Output capacitance
TTL 2.0mA buffer TTL 4.0mA buffer, CMOS TTL 8.0mA buffer TTL 12.0mA buffer * pF CIO
7 Bidirect I/O capacitance
TTL 4.0mA buffer, CMOS TTL 8.0mA buffer TTL 12.0mA buffer * pF
- Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 4. Supplied as a design limit bu t not guaranteed or tested. 5. Not more than one output may be shorted at a time for maximum duration of one second. 6. All inputs with internal pull-ups should be left floating. All other inputs should be tied high or low. 7. Capacitance measured for initial qualificatio n and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz @0V and a signal amplitude of <50mV RMS.
3V DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT VIL VDD = 3.0V and 3.6V 0.8 .3VDD V VIH VDD = 3.0V and 3.6V 2.4 .7VDD V VT+3 Schmitt Trigger, positive going threshold VDD = 3.0V and 3.6V .7VDD V VT-3 Schmitt Trigger, negative going threshold VDD = 3.0V and 3.6V .3VDD V VH 4 Schmitt Trigger, typical range of hysteresis .6 V IIN Input leakage current TTL, CMOS, and Schmitt inputs Inputs with pull-down resistors Inputs with pull-down resistors Inputs with pull-up resistors Inputs with pull-up resistors Cold Spare Inputs - normal mode Cold Spare Inputs - cold spare mode VDD = 3.6V VIN = VDD and VSS VIN = VDD VIN = VSS VIN = VSS VIN = VDD VIN = 0 to 3.6V VDD = VSS = 0V VIN = V and 3.6V +10 -225 +225 -10 VOL Low-level output voltage TTL 2.0mA buffer TTL 4.0mA buffer TTL 8.0mA buffer CMOS outputs CMOS outputs (optional) CMOS outputs (cold spare) VDD = 3.0V IOL = 2.0mA IOL= 4.0mA IOL= 8.0mA IOL = 1.0A IOL = 100A IOL = 100A 0.4 0.4 0.4 0.05 0.25 0.25 V VOH High-level output voltage TTL 2.0mA buffer TTL 4.0mA buffer, CMOS TTL 8.0mA buffer CMOS outputs CMOS outputs (optional) CMOS outputs (cold spare) VDD = 3.0V IOH = 2.0mA IOH = 2.0mA IOH = 8.0mA IOH = 1.0A IOH = 100A IOH = 100A 2.4 2.4 2.4 V DD-0.05 VDD-0.35 VDD-0.35 V
Notes: * Contact Aeroflex prior to usage. shall be specified in the AID. 2. Devices are supplied to this drawing will meet all levels M, D, P, L, R and F of irradiation. However, this device is only tested at the "R" and "F" level. Pre and Post irradiation values are identical unless otherwise specified in Table 1. When performing post irradiation electrical measurements for any RHA level, TA = +25oC. 3. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 4. Supplied as a design limit bu t not guaranteed or tested. 5. Not more than one output may be shorted at a time for maximum duration of one second. 6. All inputs with internal pull-ups should be left floating. All other inputs should be tied high or low. 7. Capacitance measured for initial qualificatio n and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz @0V and a signal amplitude of <50mV RMS. SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT IOZ Three-state output leakage current CMOS Cold Spare Inputs - normal mode Cold Spare Inputs - cold spare mode VDD = 3.6V VO = VDD and VSS VDD = VSS = 0V VO = 0V and 3.6V -20 IOS 4,5 Short-circuit output current 5 CMOS, LVTTL VO = VDD and VSS -200 200 mA IDDQ Quiescent Supply Current6 Group A subgroups 1,3 VDD = 5.5V 200K gates 400K gates 500K gates 100 180 Group A subgroup 2 VDD = 5.5V 200K gates 400K gates 500K gates mA Group A, subgroup 1 RHA designator: M, D, P, L, R VDD = 5.5V 200K gates 400K gates 500K gates mA CIN 26 pF CIO 26 pF
Intel is a registered trademark of Intel Corporation Mentor, Mentor Graphics, AutoLogic II, QuickSim II, QuickFault II, QuickHDL, QuickGrade II, FastScan, FlexTest and DFT Advisor are registered trademarks of Mentor Graphics Corporation Sun is a registered trademark of Sun Microsystems, Inc. Verilog and Leapfrog are registered trademarks of Cadence Design Systems, Inc. Synopsys, Design Compiler, Test Compiler Plus, VHDL Compiler, Verilog HDL Compiler, TestSim and VSS are trademarks of Synopsys, Inc. Vantage is a trademark of Viewlogic
www.aeroflex.com info-ams@aeroflex.com Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused Aeroflex Colorado Springs, Inc., reserves the right to make changes to any products and services described herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties. This product is controlled for export under the International Traffic in Arms Regulations (ITAR). A license from the U.S. Gov- ernment is required prior to the export of this product from the United States. Aeroflex Colorado Spring s - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced HiRel