ACTSF128K16

ACTSF128K16 AEROFLEX | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 11

Technical content

FEATURES

www.aeroflex.com eroflex Circuit Technology - Advanced Multichip Modules © SCD1677 REV A 4/28/98 ■ 2 – 128K x 8 SRAMs & 2 – 128K x 8 Flash Die in One MCM ■ Access Times of 25ns (SRAM) and 60ns (Flash) or 35ns (SRAM) and 70 or 90ns (Flash) ■ 128K x 16 SRAM ■ 128K x 16 5V Flash ■ Organized as 128K x 16 of SRAM and 128K x 16 of Flash Memory with Separate Data Buses ■ Both Blocks of Memory are User Configurable as 256K x 8 ■ Low Power CMOS ■ Input and Output TTL Compatible Design ■ MIL-PRF-38534 Compliant MCMs Available ■ Decoupling Capacitors and Multiple Grounds for Low Noise ■ Industrial and Military Temperature Ranges ■ Industry Standard Pinouts ■ Packaging – Hermetic Ceramic

• 66 Pin, 1.08" x 1.08" x .160" PGA Type, No Shoulder, Aeroflex code# "P3"
• 66 Pin, 1.08" x 1.08" x .185" PGA Type, With Shoulder, Aeroflex code# "P7"
• 68 Lead, .94" x .94" x .140" Single-Cavity Small Outline Gull Wing, Aeroflex code# "F18" (Drops into the 68 Lead JEDEC .99"SQ CQFJ footprint) ■ DESC SMD Pending – 5962-96900 FLASH MEMORY FEATURES ■ Sector Architecture (Each Die)
• 8 Equal Sectors of 16K bytes each
• Any combination of sectors can be erased with one command sequence. ■ +5V Programing, 5V ±10% Supply ■ Embedded Erase and Program Algorithms ■ Hardware and Software Write Protection ■ Internal Program Control Time. ■ 10,000 Erase/Program Cycles Pin Description FI/O0-15 Flash Data I/O SI/O0-15 SRAM Data I/O A 0–16 Address Inputs FWE 1-2 Flash Write Enables SWE 1-2 SRAM Write Enables FCE 1-2 Flash Chip Enables SCE 1-2 SRAM Chip Enables OE Output Enable NC Not Connected VC C Power Supply GND Ground 128Kx8 FCE 2 OE A 0 – A 16 SI/O0-7 SI/O8-15 FI/O0-7 FI/O8-15 8 8 8 8 FCE 1 FWE 2FWE 1SWE 2SWE 1 SCE 1 SCE 2 Block Diagram – PGA Type Package (P3,P7) and CQFP (F18) SRAM 128Kx8 SRAM 128Kx8 Flash 128Kx8 Flash 128Kx16 SRAM/FLASH Multichip Module ACT–SF128K16 High Speed Note: Programming information available upon request

2Aeroflex Circuit Technology SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700 Absolute Maximum Ratings Symbol Rating Range Units TC Case Operating Temperature -55 to +125 °C TSTG Storage Temperature -65 to +150 °C VG Maximum Signal Voltage to Ground -0.5 to +7 V TL Maximum Lead Temperature (10 seconds) 300 °C Parameter Flash Data Retention 10 Years Flash Endurance (Write/Erase Cycles)10,000 Normal Operating Conditions Symbol Parameter Minimum Maximum Units VCC Power Supply Voltage +4.5 +5.5 V VIH Input High Voltage +2.2 VCC + 0.3 V VIL Input Low Voltage -0.5 +0.8 V Capacitance (VIN = 0V, f = 1MHz, TC = 25°C) Symbol Parameter Maximum Units C AD A0 – A16 Capacitance 50 pF C O E OE Capacitance 50 pF F/S CW E1,2 F/S Write Enable Capacitance 20 pF F/S CC E1,2 F/S Chip Enable Capacitance 20 pF F/S CI/O I/O0 – I/O15 Capacitance 20 pF These parameters are guaranteed by design but not tested DC Characteristics (VC C = 5.0V, VSS= 0V, TC = -55°C to +125°C, unless otherwise indicated) Parameter Sym Conditions Min Max Units Input Leakage Current ILI VCC = Max, VIN =0toV CC 10 µA Output Leakage Current ILO FCE = SCE = VIH, OE = VIH, VOUT =0toV CC 10 µA SRAM Operating Supply Current x 16 ModeICC x16 SCE = VIL, OE = VIH, f = 5MHz, VCC = Max, FCE = VIH 250 mA Standby Current ISB FCE = SCE = VIH, OE = VIH, f = 5MHz, VCC = Max 40 mA SRAM Output Low Voltage VOL IOL = 8 mA, VCC = 4.5V 0.4 V SRAM Output High Voltage VOH IOH = -4.0 mA, , VCC = 4.5V 2.4 V Flash Vcc Active Current for Read (1)ICC1 FCE = VIL, OE = VIH, SCE = VIH 100 mA Flash Vcc Active Current for Program or Erase (2) ICC2 FCE = VIL, OE = VIH, SCE = VIH 130 mA Flash Output Low Voltage VOL IOL = 12 mA, VCC = 4.5V, SCE = VIH 0.45 V Flash Output High Voltage VOH IOH = -2.5 mA, , VCC = 4.5V, SCE = VIH 0.85 x VC C V Flash Low Vcc Lock Out Voltage VLKO 3.2 V Notes: 1) The IC C current listed includes both the DC operating current and the frequency dependent component (at 5MHz). The frequency component typically is less than 2mA/MHz, with OE at VIH 2) IC C active while Embedded Algorithim (program or erase) is in progress 3) DC test conditions: VIL = 0.3V, VIH = VC C - 0.3V

3Aeroflex Circuit Technology SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700 SRAM AC Characteristics (VC C = 5.0V, VSS= 0V, TC = -55°C to +125°C) Read Cycle Parameter Symbol –025 Min Max –035 Min Max Units Read Cycle Time tRC 25 35 ns Address Access Time tAA 25 35 ns Chip Select Access Time tACE 25 35 ns Output Hold from Address Change tOH 0 0 ns Output Enable to Output Valid tOE 15 20 ns Chip Select to Output in Low Z * tCLZ 3 3 ns Output Enable to Output in Low Z * tOLZ 0 0 ns Chip Deselect to Output in High Z * tCHZ 12 20 ns Output Disable to Output in High Z * tOHZ 12 20 ns * Parameters guaranteed by design but not tested Write Cycle Parameter Symbol –025 Min Max –035 Min Max Units Write Cycle Time tWC 25 35 ns Chip Select to End of Write tCW 20 25 ns Address Valid to End of Write tAW 20 25 ns Data Valid to End of Write tDW 15 20 ns Write Pulse Width tWP 20 25 ns Address Setup Time tAS 0 0 ns Output Active from End of Write * tOW 0 0 ns Write to Output in High Z * tWHZ 10 20 ns Data Hold from Write Time tDH 0 0 ns Address Hold Time tAH 0 0 ns * Parameters guaranteed by design but not tested SRAM Truth Table Mode SCE OE SWE Data I/O Power Standby H X X High Z Standby Read L L H Data Out Active Output Disable L H H High Z Active Write L X L Data In Active

4Aeroflex Circuit Technology SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700 Timing Diagrams — SRAM D I/O tRC tOH tAA Data ValidPrevious Data Valid tO E High Z tO H Z Read Cycle Timing Diagrams Data Valid tC LZ SCE OE tAC E tC H Z UNDEFINED DON’T CARE Read Cycle 2 (SWE = VIH ) Write Cycle (SCE Controlled, OE = VIH ) tC W tAS tW P tD W tD W SCE SWE Data Valid Write Cycle (SWE Controlled, OE = VIH ) D I/O AC Test Circuit IO L Parameter Typical Units Input Pulse Level 0 – 3.0 V Input Rise and Fall 5 ns Input and Output Timing Reference Level 1.5 V Notes: 1) VZ is programmable from -2V to +7V. 2) IO L and IO H programmable from 0 to 16 mA. 3) Tester Impedance ZO =75 Ω. 4) VZ is typically the midpoint of VO H and VO L. 5) IO L and IO H are adjusted to simulate a typical resistance load circuit. 6) ATE Tester includes jig capacitance. IO H To Device Under Test VZ ~ 1.5 V (Bipolar Supply) Current Source Current Source C L = 50 pF tW C tAW tAH tRC tAA tO LZ SEE NO TE SE E NO TE SEE NO TE SE E NO TE Note: Guaranteed by design, but not tested. D I/O tD HtW H Z SEE NO TE Read Cycle 1 (SCE = OE = VIL, SWE = VIH ) Write Cycle Timing Diagrams tW P tD W Data Valid tW C tAW tAH D I/O tD H SCE SWE tC WtAS A0-18 A0-18 A0-18 A0-18 AC Test Conditions

5Aeroflex Circuit Technology SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700 Flash AC Characteristics – Read Only Operations(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C) Parameter Symbol JEDEC Stand’d –60 Min Max –70 Min Max –90 Min Max Units Read Cycle Time tA VA V tR C 60 70 90 ns Address Access Time tA VQ V tA C C 60 70 90 ns Chip Enable Access Time tELQ V tC E 60 70 90 ns Output Enable to Output Valid tG LQ V tO E 30 35 40 ns Chip Enable to Output High Z (1) tEH Q Z tD F 20 20 25 ns Output Enable High to Output High Z(1) tG H Q Z tD F 20 20 25 ns Output Hold from Address, CE or OE Change, Whichever is First tA XQ X tO H 0 0 0 ns Note 1. Guaranteed by design, but not tested Flash AC Characteristics – Write/Erase/Program Operations, FWE Controlled(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C) Parameter Symbol JEDEC Stand’d –60 Min Max –70 Min Max –90 Min Max Units Write Cycle Time tA VA C tW C 60 70 90 ns Chip Enable Setup Time tELW L tC E 0 0 0 ns Write Enable Pulse Width tW LW H tW P 30 35 45 ns Address Setup Time tA VW L tA S 0 0 0 ns Data Setup Time tD VW H tD S 30 30 45 ns Data Hold Time tW H D X tD H 0 0 0 ns Address Hold Time tW LA X tA H 45 45 45 ns Chip Enable Hold Time tW H EH tC H 0 0 0 ns Write Enable Pulse Width High tW H W L tW PH 20 20 20 ns Duration of Byte Programming Operation tW H W H 1 14 TYP 14 TYP 14 TYP µs Sector Erase Time tW H W H 2 60 60 60 Sec Chip Erase Time tW H W H 3 120 120 120 Sec Read Recovery Time before Write tG H W L 0 0 0 µs Vcc Setup Time tVC E 50 50 50 µs Output Enable Setup Time tO ES 12.5 12.5 12.5 Sec Output Enable Hold Time1 tO E H 10 10 10 ns Note: 1. For Toggle and Data Polling. Flash AC Characteristics – Write/Erase/Program Operations, FCE Controlled(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C) Parameter Symbol JEDEC Stand’d –60 Min Max –70 Min Max –90 Min Max Units Write Cycle Time tA VA C tW C 60 70 90 ns Write Enable Setup Time tW LEL tW S 0 0 0 ns Chip Enable Pulse Width tELEH tC P 35 35 50 ns Address Setup Time tA VE L tA S 0 0 0 ns Data Setup Time tD VEH tD S 30 30 50 ns Data Hold Time tEH D X tD H 0 0 0 ns Address Hold Time tELA X tA H 45 45 50 ns Write Enable Hold from Write Enable High tEH W H tW H 0 0 0 ns Chip Enable Pulse Width High tEH EL tC PH 20 20 20 ns Duration of Byte Programming tW H W H 1 14 TYP 14 TYP 14 TYP µs Sector Erase Time tW H W H 2 60 60 60 Sec Chip Erase Time tW H W H 3 120 120 120 Sec Read Recovery Time tG H EL 0 0 0 ns Chip Programming Time 12.5 12.5 12.5 Sec

6Aeroflex Circuit Technology SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700 AC Waveforms for Flash Memory Read Operations tO HtC E tO E tA C C tR C tD F Output Valid High ZHigh ZOutputs OE FWE FCE Addresses Addresses Stable FWE OE FCE Data Addresses 5.0V 5555H PA Data Polling PA D7 D O U TPDAOH tW H W H 1 tO E tR C tC E tD F tO H tA HtA S tD H tW PH tW P tD S tC E tW C Write/Erase/Program Operation for Flash Memory, FWE Controlled Notes: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the 0utput of the complement of the data written to the deviced. 4. Dout is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. tG H W L

7Aeroflex Circuit Technology SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700 AC Waveforms Chip/Sector Erase Operations for Flash Memory Data Addresses VC C 5555H Data PollingtA H FCE tA S FWE 5555H 5555H SA2AAAH 2AAAH tG H W L tW P tW PH tD S tD HtC E tVC E 55H AAH80H 55H 10H/30HAAH OE Notes: 1. SA is the sector address for sector erase. AC Waveforms for Data Polling During Embedded Algorithm Operations for Flash Memory tO E tC H tW H W H 1 or 2 tO E tO H tD F tC E tO EH * DQ7=Valid Data (The device has completed the Embedded operation). DQ0–DQ6=Invalid DQ 7 DQ 7= Valid Data DQ0–DQ6 Valid Data High Z FCE DQ7 OE FWE DQ0-DQ6

8Aeroflex Circuit Technology SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700 FCE OE FWE Data Addresses 5.0V 5555H PA Data Polling PA D7 D O U TPDAOH tW H W H 1 tA HtA S tD H tC PH tC P tD S tW S tW C tG H W L Notes: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the 0utput of the complement of the data written to the device. 4. DO U T is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. Write/Erase/Program Operation for Flash Memory, FCE Controlled

9Aeroflex Circuit Technology SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700 Pin Numbers & Functions

66 Pins — PGA-Type

Pin # Function Pin # Function Pin # Function Pin # Function

1 SI/O8 18 A12 35 FI/O9 52 FWE 1

2 SI/O9 19 Vcc 36 FI/O10 53 FCE 1

3 SI/O10 20 SCE 1 37 A6 54 GND

4 A13 21 NC 38 A7 55 FI/O3

5 A14 22 SI/O3 39 NC 56 FI/O15

6 A15 23 SI/O15 40 A8 57 FI/O14

7 A16 24 SI/O14 41 A9 58 FI/O13

8 NC 25 SI/O13 42 FI/O0 59 FI/O12

9 SI/O0 26 SI/O12 43 FI/O1 60 A0

10 SI/O1 27 OE 44 FI/O2 61 A1

11 SI/O2 28 NC 45 VC C 62 A2

12 SWE 2 29 SWE 1 46 FCE 2 63 FI/O7

13 SCE 2 30 SI/O7 47 FWE 2 64 FI/O6

14 GND 31 SI/O6 48 FI/O11 65 FI/O5

15 SI/O11 32 SI/O5 49 A3 66 FI/O4

16 A10 33 SI/O4 50 A4

17 A11 34 FI/O8 51 A5

1.085 SQ 1.000 .600 1.000 .100 .020 .016 .100 .180 TYP 1.030 1.040 .160 Pin 56 Pin 66 Pin 11 Pin 1 Bottom View (P7 & P3) MAX MAX "P3" — 1.08" SQ PGA Type (without shoulder) Package "P7" — 1.08" SQ PGA Type (with shoulder) Package 1.030 1.040 .020.016 .100 .025 .185 MAX Side View (P7) Side View (P3) .050 .180 TYP .035 All dimensions in inches

10Aeroflex Circuit Technology SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700 Pin Numbers & Functions

68 Pins — Dual-Cavity CQFP

Pin # Function Pin # Function Pin # Function Pin # Function

1 GND 18 GND 35 OE 52 GND

2 FCE 1 19 SI/O8 36 SCE 2 53 FI/O7

3 A5 20 SI/O9 37 NC 54 FI/O6

4 A4 21 SI/O10 38 SWE 2 55 FI/O5

5 A3 22 SI/O11 39 FWE 1 56 FI/O4

6 A2 23 SI/O12 40 FWE 2 57 FI/O3

7 A1 24 SI/O13 41 NC 58 FI/O2

8 A0 25 SI/O14 42 NC 59 FI/O1

9 NC 26 SI/O15 43 NC 60 FI/O0

10 SI/O0 27 Vcc 44 FI/O15 61 VC C

11 SI/O1 28 A11 45 FI/O14 62 A10

12 SI/O2 29 A12 46 FI/O13 63 A9

13 SI/O3 30 A13 47 FI/O12 64 A8

14 SI/O4 31 A14 48 FI/O11 65 A7

15 SI/O5 32 A15 49 FI/O10 66 A6

16 SI/O6 33 A16 50 FI/O9 67 SWE1

17 SI/O7 34 SCE 1 51 FI/O8 68 FCE 2

.015 ±.002 All dimensions in inches "F18" — CQFP Package .015 .990 SQ ±.010 .940 SQ ±.010 .800 REF See Detail “A” ±.002 Pin 60 Pin 44 Pin 43Pin 27 Pin 26 Pin 10 Pin 9 .900 SQ MAX Pin 61 .140 REF .640 SQ REF .008 ±.002 Detail “A” .010±.008 .040 Metal spacer

11Aeroflex Circuit Technology SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700

Ordering Information

Model Number DESC SMD Number Speed Package ACT–SF128K16N –26P3Q 5462-96900* 25(S) / 60(F) ns 1.08"SQ PGA-Type ACT–SF128K16N –37P3Q 5462-96900* 35(S) / 70(F) ns 1.08"SQ PGA-Type ACT–SF128K16N –39P3Q 5462-96900* 35(S) / 90(F) ns 1.08"SQ PGA-Type ACT–SF128K16N –26P7Q 5462-96900* 25(S) / 60(F) ns 1.08"SQ PGA-Type ACT–SF128K16N –37P7Q 5462-96900* 35(S) / 70(F) ns 1.08"SQ PGA-Type ACT–SF128K16N –39P7Q 5462-96900* 35(S) / 90(F) ns 1.08"SQ PGA-Type ACT–SF128K16N –26F18Q 5462-96900* 25(S) / 60(F) ns .94"sq CQFP ACT–SF128K16N –37F18Q 5462-96900* 35(S) / 70(F) ns .94"sq CQFP ACT–SF128K16N –39F18Q 5462-96900* 35(S) / 90(F) ns .94"sq CQFP Note: (S) = Speed for SRAM, (F) = Speed for FLASH * Pending Aeroflex Circuit Technology

35 South Service Road

Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: 1-(800) 843-1553 CIRCUIT TECHNOLOGY Specification subject to change without notice Part Number Breakdown ACT– S F 128K 16 N– 26 P7 Q Aeroflex Circuit Technology Memory Type S (SRAM) & F (FLASH) Combo Memory Depth Memory Width, Bits Memory Speed cODE Package Type & Size C = Commercial Temp, 0°C to +70°C I = Industrial Temp, -40°C to +85°C T = Military Temp, -55°C to +125°C M = Military Temp, -55°C to +125°C, Screening Q = MIL-PRF-38534 Compliant / SMD Screening * Screened to the individual test methods of MIL-STD-883 Surface Mount Packages Thru-Hole Packages F18 = .94"SQ 68 Lead Dual-Cavity CQFP P3 = 1.085"SQ PGA 66 Pins with out shoulder P7 = 1.085"SQ PGA 66 Pins with shoulder 26 = 25ns SRAM & 60ns FLASH 37 = 35ns SRAM & 70ns FLASH 39 = 35ns SRAM & 90ns FLASH Options, N = none