DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 21
Technical content
UT04VS33P V oltage Supervisor Data Sheet July 28, 2014 www.aeroflex.com/V oltSupv
FEATURES
3.0V to 3.6V Operating voltage range 6 Fixed Threshold V oltage Monitors (3.3V , 2.5V , 1.8V , 1.5V , 1.2V , 1.0V) Fixed & Adjustable Threshold V oltage Select modes Threshold V oltage Select with TH0, TH1 pins Adjustable RESET Timeout with external capacitor Independent V oltage Monitoring and Sequencing Manual Reset Input Pin Active Low and Active High RESET pins Output V oltages Open Drain Two VOUTS active high and two VOUTS programmable with INV Pin RESET, RESETB Outputs Open Drain Over-voltage Detection Mode Operating Temperature Range -55oC to +125oC Low Power Typical 1000A Tolerance Select Input Pin (5% & 10%) RESET, RESETB, VOUT1, VOUT2, VOUT3 and VOUT4 guaranteed to be in the correct state for VDD down to 1.2V Packaging options: - 28-lead ceramic dual flatpack Operational environment: - Total dose: 300 krad(Si) - SEL Immune: <110 MeV-cm2/mg @125oC - SET Immune: <109MeV-cm2/mg Standard Microelectronics Drawing (SMD) 5962-13206 - QML Q and V INTRODUCTION The UT04VS33P is a radiation-hardened V oltage Supervisor which simultaneously monitors up to four supply levels utilized in a system, providing status output for each signal, VOUTx, as well as, a system reset signal if any of the monitored signals moves out of range. To set the monitor trip points, the TH0 and TH1 pins allow the selection of three sets of preset threshold levels per channel, determined by an internal bandgap voltage reference, to reduce supply and temperature variance, and a fourth selection which allows the user to determine the level for each channel. There are two modes of operation, determined by the OVSH pin. In the first mode, when the OVSH pin is connected to VSS, four independent supplies are monitored for an under-voltage condition. In the second mode when the OVSH pin is connected to VDD, then under-voltage and over-voltage of the inputs are monitored. In this mode, two supplies can be monitored using channels 1 and 3 or channels 2 and 4, respectively. For flexibility, both system RESET and RESETB outputs are available for interfacing to the system. Each channel has an enable, ENx, allowing use of one, two, three or all four monitor channels. The margin (or tolerance) to the given threshold voltage, for under-voltage monitoring, is determined by the setting of the TOL pin. The logic sense of the channel 3 and 4 outputs can be inverted by setting the INV pin, appropriately. Also, MRB, master reset, provides a means for a manual input to activate the RESET signals. In addition, the user can adjust two timing parameters by the addition of external capacitors to the device. These are the response times of the channel VOUTx signal when the associated input returns to a valid level, implemented by a capacitor connected to CDLYx and the time to clear RESET (and RESETB) when a channel enable or input level becomes valid; implemented by CRESET. APPLICATION The UT04VS33P supervisory circuit reduces the complexity and number of circuits required to monitor power supply and battery functions in microprocessor, DSP, microcontroller, ASIC and FPGA systems. The UT04VS33P supervisory circuit significantly improves system reliability and accuracy over comparable systems that use separate ICs or discrete components.
Number Pins Type Description 1 EN1 Digital Input Active high enable for VI N1. Setting this pin low forces VOUT1 low regardless of the value of VIN1. Setting this pin high enables the monitor circuitry for VIN1. 2 VIN1 Analog Input Analog input VIN1. When enabled the voltage input is monitored for an under-voltage condition; see Functional Descriptions - Thresholds, Over-voltage Setting/Tolerance. The condition is output on VOUT1. 3 EN3 Digital Input Active high enable for VI N3. Setting this pin low forces VOUT3 low when OVSH=0 (VOUT3 is forced low when OVSH=1) regardless of the value of VIN3. Setting this pin high enables the monitor circuitry for VIN3. 4 VIN3 Analog Input Analog input VIN3. When enabled and dependent on the mode of operation (OVSH), the voltage input is monitored for an under-voltage or over-voltage condition; see Functional Descriptions - Thresholds, Over-voltage Setting/Tolerance. The condition is output on VOUT3 when OVSH=0 and on VOUT1 when OVSH=1. 5N C N C 6 OVSH Digital Input Over-voltage pin. When OVSH = 1, the over-voltage mode is enabled. This allows for the monitoring of both over-voltage and under-voltage of two supplies. Inputs VIN1 and VIN2 function normally, while VIN3 is used to monitor an over-voltage condition in conjunction with the VIN1 source and VIN4 likewise for the VIN2 source. See Functional Descriptions - Thresholds, Over-voltage Setting/Tolerance. When OVSH=0 all four inputs, VIN1, VIN2, VIN3 and VIN4 monitor under- voltage. 7 TH1 Digital Input Digital Threshold select1. Used with TH0 to select one of four analog input voltage thresholds. (See Table 2) 8 TH0 Digital Input Digital Threshold select0. Used with TH1 to select one of four analog input voltage thresholds. (See Table 2)
9 TOL Digital Input Threshold tolerance select sets the accuracy of the threshold to 5%
below the nominal value by connecting TOL to logic 0. Connecting TOL to logic 1 sets the threshold voltage to 10% below the nominal value. 10 EN2 Digital Input Active high enable for VI N2. Setting this pin low forces VOUT2 low regardless of the value of VIN2. Setting this pin high enables the monitor circuitry for VIN2. 11 VIN2 Analog Input Analog input VIN2. When enabled, the voltage input is monitored for an under-voltage condition; see Functional Descriptions - Thresholds, Over-voltage Setting/Tolerance.The condition is output on VOUT2.
Number Pins Type Description 12 EN4 Digital Input Active high enable for VIN4. Setting this pin low forces VOUT4 low when OVSH=0 (VOUT4 is forced low when OVSH=1) regardless of the value of VIN4. Setting this pin high enables the monitor circuitry for VIN4. 13 VIN4 Analog Input Analog input VIN4. When enabled and dependent on the mode of operation (OVSH), the voltage input is monitored for an under-voltage or over-voltage condition; see Functional Descriptions - Thresholds, Over-voltage Setting/Tolerance. The condition is output on VOUT4 when OVSH=0 and on VOUT2 when OVSH=1. 14 VSS Supply GND Ground. This pin must be tied to system ground to establish a reference for voltage detection. 15 CDLY4 Analog Output External capacitor delay connection. Allows adjustment of the VOUT4 timing after VIN4 becomes valid, when OVSH = 0. See Functional Descriptions - CDLY timing section.
16 VOUT4 Open Drain
Output of VIN4 monitor when OVSH = 0; inactive when OVSH=1. With INV=0, logic 1 indicates that the VIN4 input is at a valid level. With INV=1, logic 0 indicates that VIN4 is at a valid level. Device contains active pull-down device; requires external pull-up. 17 CDLY2 Analog Output External capacitor delay connection. Allows adjustment of the VOUT2 timing after VIN2 becomes valid. See Functional Descriptions - CDLY timing section.
18 VOUT2 Open Drain
When OVSH=0, it indicates the signal state of the VIN2 monitor. When OVSH=1, it indicates the combined signal states for VIN2 and VIN4 (under-voltage and over-voltage detection). See Functional Descriptions - Thresholds, Device contains active pull-down device; requires external pull-up.
19 RESET Open Drain
Active high output indicating a system reset condition is activated by appropriate condition on VOUTx, ENx, or MRB pin. See discussion for state changes and timing information. Device contains active pull- down device; requires external pull-up. 20 CRESET Analog Output External capacitor delay connection. Allows adjustment of RESET timeout, which is the time RESET is held after all reset input conditions are cleared. See Functional Description - CRESET timing section.
21 RESETB Open Drain
Active low output indicating a system reset condition is activated by appropriate condition on VOUTx, ENx, or MRB pin. See discussion for state changes and timing information. Device contains active pull- down device; requires external pull-up. 22 INV Digital Input When logic 1, inverts the sense of the VOUT3 and VOUT4 outputs.
23 MRB Digital Input
Master Reset active low input. This forces the RESET/RESETB pins to their active state. See discussion for timing information.
Number Pins Type Description 24 CDLY3 Analog Output External capacitor delay connection. Allows adjustment of the VOUT3 timing after VIN3 becomes valid when OVSH=0. See Functional Descriptions - CDLY timing section.
25 VOUT3 Open Drain
Output of VIN3 monitor when OVSH=0; inactive when OVSH=1. With INV=0, logic 1 indicates that the VIN3 input is at a valid level. With INV=1, logic 0 indicates that VIN3 is at a valid level. Device contains active pull-down device; requires external pull-up. 26 CDLY1 Analog Output External capacitor delay connection. Allows adjustment of the VOUT1 timing after VIN1 becomes valid. See Functional Descriptions - CDLY timing section.
27 VOUT1 Open Drain
When OVSH=0, it indicates the signal state of the VIN1 monitor. When OVSH=1, it indicates the combined signal states for VIN1 and VIN3 (under-voltage and over-voltage detection). See Functional Descriptions - Thresholds, Device contains active pull-down device; requires external pull-up. 28 VDD Supply Supply voltage, 3.0 to 3.6V .
Notes: 1. Using MIL-STD-883, TM1019, Condition A. 2. Worst case temperature and voltage of Tc = +125oC, VDD = 3.6V . ABSOLUTE MAXIMUM RATINGS 1 Notes: 1. Stresses outside the listed absolute maxi mum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS PARAMETER LIMIT UNITS Total Ionizing Dose (TID)1 300 krad(Si) Single Event Latchup Immune (SEL)2 <110 MeV-cm2/mg Single Event Transient Immune (SET) <109 MeV-cm2/mg SYMBOL PARAMETER LIMITS UNITS VDD Positive supply voltage 4.8 V VIO V oltage on any I/O pin -0.3 to VDD + 0.3V V IIO DC I/O current +10 mA PD Power dissipation 1.0 W JC Thermal resistance, junction to case 16 oC/W TLEAD Lead temperature (soldering 10 seconds) 300 oC TJ Maximum junction temperature +175 C TSTOR Storage temperature -65 to +150 C VESD ESDHBM 1000 V SYMBOL PARAMETER LIMITS UNITS VDD Positive supply voltage 3.0 to 3.6 V VSS Negative supply voltage 0.0 V TC Case temperature range -55 to +125 C VIN Analog inputs Digital inputs 0.6 to 3.6 VSS to VDD V V
DC ELECTRICAL CHARACTERISTICS 1,2 (VDD=3.0V to 3.6V; -55C < TC < +125C) SYMBOL PARAMETER CONDITION MIN MAX UNIT Power Supply IDD VDD supply current All V OUTX high 1250 A Digital Inputs and Outputs VIL Digital input low -0.3 0.3*V DD V VIH Digital input high 0.7*V DD VDD+0.3 V VILMRB MRB Digital input low -0.3 0.8 V VIHMRB MRB Digital input high 2.0 V DD+0.3 V VHYSTMRB MRB Input voltage hysteresis 60 mV IMRB MRB pull-up current MRB=0V VDD=3.6V for Max IMRB 225 A VOL Open drain digital output low V DD =3.6V I sink=1mA 0.3 V ICH_RESET 3 Charge current CRESET V DD =3.0V 0.35 1.25 A IOZL Digital output leakage current low -1 1 A IOZH Digital output leakage current high -1 1 A IIL Digital input leakage current low -1 1 A IIH Digital input leakage current high -1 1 A ICH_CDLY 3 Charge current CDLY V DD=3.0V 0.55 1.90 A VTH_CDLY 3 Threshold CDLYx CDLY rising 1.17 1.23 V VTH_CRESET 3 Threshold CRESET CRESET rising 1.17 1.23 V VRFTH
3 Reference threshold voltage 585 615 mV
VTH_VIN Analog threshold under-voltage case 3.3V threshold, TOL= 0 3.3V threshold, TOL= 1 2.5V threshold, TOL= 0 2.5V threshold, TOL= 1 1.8V threshold, TOL= 0 1.8V threshold, TOL= 1 1.5V threshold, TOL= 0 1.5V threshold, TOL= 1 1.2V threshold, TOL= 0 1.2V threshold, TOL= 1 1.0V threshold, TOL= 0 1.0V threshold, TOL= 1 2.97 2.805 2.25 2.125 1.620 1.530 1.350 1.275 1.080 1.020 0.90 0.85 3.135 2.970 2.375 2.250 1.710 1.620 1.425 1.350 1.140 1.080 0.950 0.915 V V V V V V V V V V V V C VINX
3 VINx input capacitance 15 pF
Notes: 1. For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is specified at 25oC per MIL-STD-883 Method 1019, Condition A, up to the maximum TID level procured (see ordering information). 2. RESET, RESETB, VOUT1, VOUT2, VOUT3 and VOUT4 guaranteed to be in the correct state for VDD down to 1.2V . 3. Guaranteed by design but not tested.
AC CHARACTERISTICS READ CYCLE (Post-Radiation)* (VDD = 3.0V to 3.6V; -55C < TC < +125C) Notes: *Post-radiation performance guaranteed at 25oC per MIL-STD-883 Method 1019 at 300 krad(Si). 1. Guaranteed by design but not tested Figure 3: Test Circuit Load used for AC timing SYMBOL PARAMETER CONDITION MIN MAX UNIT tDELAY+
1 VIN+ to VOUT propagation delay V IN rising, CDLY open 11 60 s
tDELAY+ VIN+ to VOUT propagation delay V IN rising, Cdly capacitance value on CDLYx=112pF (Figure 3, Test Circuit Load) 81 263 s tDELAY- VIN- to VOUT propagation delay V IN falling 40 s tRP
1 Reset timeout period CRESET open 37 170 s
tRP Reset timeout period Creset capacitance value on CRESET =65pF (Figure 3, Test Circuit Load) 100 283 s tON
1 EN+ to VOUT propagation delay EN rising to V OUT going high
11 60 s tON EN+ to VOUT propagation delay EN rising to V OUT going high, Cdly capacitance value on CDLYx=112PF (Figure 3, Test Circuit Load) 81 263 s tOFF EN- to VOUT propagation delay EN falling to V OUT deasserted 4 s tMRST MRB- to RESET/RESETB propagation delay MRB falling to RESET/RESETB asserted 5 s tMPW Minimum MRB Input pulse width 2.5 s tMRP MRB+ to RESET/RESETB propagation delay MRB rising to RESET/RESETB deasserted 3 s tRST_DELAY VINx- to RESET/RESETB asserted V IN falling 40 s tGLITCH ENx or MRB glitch rejection 270 ns tGLITCH_VINx
1 VINx glitch rejection 800 ns
Zo = 50-ohms VDD CL Test PointDUT
voltage is connected directly to the pin or via a resistive divider. Channel Detection Threshold section. Table 2. The actual threshold voltage, accounting for tolerance, given in the DC Characteristics table.
sistive divider, the maximum voltage of the monitored signal can be greater than the maximum level when using the preset threshold, as given by: Vmonitor < [(RT + RB)/RB] * VRFTH where RT is the top resistor of the divider and RB is the lower resistor, tied to VSS. One should account for resistor toleranc- es. Also, with the resistive divider tied to VSS, the minimum voltage that can be monitored is VRFTH. It is possible to tie the resistive divider to the VDD supply and, hence, monitor signals lower than VRFTH. If this arrangement is used, the variation in the VDD supply will affect the result. Enables Each channel has an enable, ENx. When a channel is disabled its corresponding output is held in the logic 0 state. Also, the outputs are not affected by any changes of signals that may oc- cur on disabled channels. However, when a channel is enabled, the outputs are put into the mode for the length of time as deter- mined by RESET timeout. As noted, when the OVSH is logic 1, the enables of channels 1 and 3 are connected together to af- fect channel 1 output and those for channels 2 and 4 affect chan- nel 2 output. See Figure 4 for timing. The condition whereby all four enables are in the logic 0 state is reserved and should not be used. Master Reset The device has a master reset (inverted logic) input, MRB, which provides a means for the system reset to be combined with the voltage supervisor reset functionality. The timing of this input with respect to the RESET/RESETB outputs is shown in Figure 5. Timing specifications are given in the AC Charac- teristics table. An RC time constant can be associated with this pin to extend the RESET state. Timing (CDLY, CRESET) Many of the timing parameters of the device are fixed and listed in the AC Characteristics table. Along with those are the default value for the CDLY function, response time of VOUTx after the corresponding input signal becomes valid, and the C func- tion, defining the timeout until an output is released after an event (an ENx or all enabled VOUTx becoming valid). CDLY timing The delay time (t DELAY+) for each channel is independently ad- justable by adding a capacitor to the desired CDLYx pin. The equation that defines the delay is: tDELAY+ = (Cdly + 18pF) * (VTH_CDLY)/ ICH_CDLY where Cdly is the user chosen, external capacitance connected to CDLY pin, 18pF is the internal capacitance (any significant board capacitance should be added), I CH_CDLY is the charging current with value given in the DC Characteristics table and VTH_CDLY is the threshold voltage utilized by this function, also given in the DC Characteristics table. CRESET timing The timeout for the outputs (tRP) when activated by changes of an ENx or VINx signal, is adjustable by the addition of an ex- ternal capacitor to the CRESET pin. The equation that defines the RESET timeout period is: t RP=(Creset+ 40pF)*(VTH_CRESET) /ICH_RESET where Creset is the user chosen, external capacitance, 40pF is the device default and parasitic capacitance (any significant board capacitance should be added), ICH_RESET is the charging current with value given in the DC Characteristics table and VTH_CRESET is the threshold voltage utilized by this function, also given in the DC Characteristics table. Output drive (open drain - power, speed) The outputs from the device, RESET, RESETB and VOUTx are of the open drain type, having only an active pulldown, with characteristics given in the DC and AC Characteristics tables. Hence, the user must supply an appropriate valued resistor for the pullup. Note: This allows for 1) the connecting of several outputs from the given device or other devices and 2) provides for voltage drive-level adjustment by connecting the resistor to an appropriate supply (note the voltage level is constrained by the operating voltage of this device, V DD). INV function For further system interface flexibility, the INV pin provides for the logical inversion of the channel 3 and 4 VOUT signals. In all modes, the logic level of the output is inverted from its normal state.
Figure 6. VINx Timing Diagram
- Effect of INV on VOUT (TOL = x and OVSH = 0), ENx and VINx refer to the corresponding output.
- Effect of INV on V out (TOL= x and OVSH=1). ENx/ENy refers to EN1 and EN3 or EN2 and EN4, respectively. VINx/VINy refers to VIN1 and VIN3 or VIN2
and VIN4, respectively. Note: V out3/V out4 are not used in this mode.
- Having all four enables low is an invalid state for the device operation. This state will not cause any harm to the device or system, but operation may not be as expected.
- For OVSH=1, VTH _OVRV is the threshold which is set with external resistors to either the VIN3 or VIN4 input to monitor an over-voltage condition in conjunction
with the under-voltage monitor by VIN1 or VIN2, respectively, as shown in Figure 8 and Figure 9. Note: Refer to the section, "Thresholds/Over-V oltage Setting/Tolerance" for information regarding the adjustable threshold. Table 2. Quad Input Voltage Threshold Selections
Note: Listed in Table 3 are the estimated input resistances, as referenced to VSS, seen at each of the VINx pins. The resi stance can be used to estimate the expected load current at that VINx input. Table 3: Analog Input Resistance Referenced to VSS (VDD = 3.0V to 3.6V; -55oC < TC < +125oC) ANALOG INPUT RESISTANCE THRESHOLD SELECT MIN MAX UNIT TH1 TH0 RIN1 0 0 94 160 k RIN2 0 0 282 485 k RIN3 0 0 205 355 k RIN4 0 0 172 295 k RIN1 0 1 94 160 k RIN2 0 1 205 355 k RIN3 0 1 172 295 k RIN4 0 1 137 235 k RIN1 1 0 94 160 k RIN2 1 0 172 295 k RIN3 1 0 137 235 k RIN4 1 0 114 197 k
Figure 11. 28-pin Flatpack
ORDERING INFORMATION
UT04VS33P VOLTAGE SUPERVISOR Lead Finish: (Notes: 1) (C) = Gold Screening Level: (Notes: 2 and 3) (P) = Prototype Flow (C) = HiRel Flow (Temperature range -55 oC to +125oC) Case Outline: (X) = 28-lead Ceramic Flat Package TID Tolerance: (-) = None Device Type (33P)= 3.3V Quad V oltage Supervisor Generic UT04VS33P part number: (04VS) Notes: 1. Lead finish is "C" (Gold) only. 2. Prototype flow per Aeroflex Manufacturing Flows Document. Devices are tested at 25C only. Lead finish is Gold "C" only. Radiation neither tested nor guaranteed. 3. HiRel Flow per Aeroflex Manufacturing Flows Do cument. Radiation neither tested nor guaranteed.
UT04VS33P VOLTAGE SUPERVISOR: SMD Lead Finish: (Note 1) (C) = Gold Case Outline: (X) = 28-lead ceramic flatpack Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type: (01) = UT04VS33P (Temperature Range: -55 C to +125C) Drawing Number: (13206) = 3.3V V oltage Supervisor Total Dose: (R) = 100 krad(Si) (F) = 300 krad(Si) Federal Stock Class Designator: No options Notes: 1. Lead finish is "C" (Gold) only.
www.aeroflex.com info-ams@aeroflex.com Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused Aeroflex Colorado Springs, Inc., reserves the right to make changes to any products and services described herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the informa- tion in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or ser- vice described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties. This product is controlled fo r export under the International Traffic in Arms Regulations (ITAR). A license from the U.S. Government is required prior to the export of this product from the United States. Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel