UT0.25UHBD AEROFLEX | Alldatasheet

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UT0.25μHBD Hardened-by-Design Standard Cell ASIC Data Sheet June 2010 www.aeroflex.com/RadHardASIC

FEATURES

‰ Up to 3,000,000 usable equivalent gates using standard cell architecture ‰ Toggle rates up to 1.2 GHz ‰ Advanced 0.25μ silicon gate CMOS processed in a com- mercial fab ‰ Operating voltage of 100% 3.3V or 3.3V I/O and 2.5V core ‰ Input buffers are 5-volt tolerant ‰ Multiple product assurance levels available, QML V and Q, military, industrial ‰ Radiation hardened from 100 krads(Si) to 1 Mrad total dose available using Aeroflex’s RadHard techniques ‰ SEU-immune to less than 1.0E-10 errors/bits-day avail- able using special library cells ‰ Robust Aeroflex Design Library of cells and macros ‰ Support for Verilog and VHDL design languages on Sun and Linux workstations ‰ Cell models validated in Mentor Graphics® and Synop- sysTM design environments ‰ Full complement of industry standard IP cores ‰ Various RAM configurations available ‰ Supports cold sparing for power down applications ‰ Power dissipation of 0.04μW/MHz/gate at VDDCORE 2.5V and 20% duty cycle and 0.06μW/MHz/gate at VDDCORE 3.3V and 20% duty cycle ‰ External chip capacitor attachment option available to space quality levels (for improved SSO response) PRODUCT DESCRIPTION The high-performance UT0.25um Hardened-by-Design ASIC standard cell family features densities up to 3,000,000 equivalent gates and is available in multiple quality assur- ance levels such as MIL-PRF-38535, QML V and Q, military, industrial grades, and non-RadHard versions. For those designs requiring stringent radiation hardness, Aeroflex's 0.25um process employs a special technique that enhances the total dose radiation hardness from 100Krads(Si) to 1 Mrad while maintaining circuit density and reliability. In addition, for greater transient radiation hardness and latch-up immunity, the deep submicron pro- cess is built on epitaxial wafers. Developed from Aeroflex's patented architectures, the 0.25um ASIC family uses a highly efficient standard cell architecture for internal cell instantiation. Combined with state-of-the-art, timing driven placement and routing tools, the area utilization and signal routing of transistors is max- imized using five levels of metal interconnect. The UT0.25uHBD ASIC family is supported by an exten- sive cell library that includes SSI, MSI, and 54XX equivalent functions, as well as PLL, RAM, and cores. Aer- oflex's core library includes the following functions:

  • Intel 80C31® equivalent
  • Intel 80C196® equivalent
  • MIL-STD-1553 functions (BRCTM, RTI, RTMP)
  • MIL-STD-1750 microprocessor
  • RISC microcontroller
  • Select RAM configurations (with optional MBIST and EDAC)
  • Phase Locked Loop (PLL)
  • Aeroflex Gaisler - LEON3 and other IP can be reviewed at www.gaisler.com/CMS

Table 1. Gate Densities

  1. Based on NAND2 equivalents plus 20% routing overhead. Actual usable gate count is design-dependent.

design circuitry from switching noise. Table 2. Packages

  1. Contact Aeroflex for specific package drawings.
  2. External chip capacitor attachment option available to space quality levels (for improved SSO response).
  3. Aeroflex supports all JEDEC outline package designs. Listed packages are tooled.
  4. LGA package formats can be provided with Solder Columns.

The UT0.25uHBD standard cell family is supported by an exten- sive cell library that includes SSI, MSI, and 54XX-equivalent functions, as well as RAM and other library functions. User-se- lectable options for cell configurations include scan and radiation hardness (SEU) levels for all register elements, as well as output drive strength. Phase-Locked Loop (PLL) macro cells are derived from the Aeroflex Standard Products UT7R995 RadClockTM. They are available in three frequency ranges - 24MHz to 50MHz, 48MHz to 100MHz, and 96MHz to 200MHz. All PLLs support a power-down mode and phase lock indicator. Refer to Aeroflex’s UT0.25μHBD Design Manual for complete cell listing and details. I/O Buffers The UT0.25uHBD gate array family offers up to 530 signal I/O locations (note: device signal I/O availability is affected by pack- age selection and pinout). The I/O cells can be configured by the user to serve as input, output, bidirectional, three-state, or addi- tional power and ground pads. Output drive options range from 4 to 24mA. To drive larger off-chip loads, output drivers may be combined in parallel to provide additional drive up to 48mA. Other I/O buffer features and options include:

  • Pull-up and pull-down resistors
  • Schmitt trigger
  • LVDS
  • PCI
  • SSTL
  • CML
  • Cold Sparing LVDS transmitter (Tx) and receiver (Rx) buffers are based on the Aeroflex Standard Products UT54LVDS031LV LVDS driver and UT54LVDS032LV receiver products. They provide the same >400Mbps (200MHz) switching rates, 340mV nominal differen- tial signaling levels, cold-sparing, transmitter enable, and receiver fail-safe circuitry. Each supports a power-down mode, putting the I/O buffers into their lowest power state. A unique Aeroflex reference circuit improves performance matching be- tween multiple Tx buffers and multiple Rx buffers. The PCI I/O buffer is usable as an input, output or bidirect and is compliant to the PCI 2.2 specification. Aeroflex's ASIC SSTL bidirect, tristate, and input buffers are based on the JESD8-15A standard for Stub Series Terminated Logic for 1.8V (SSTL_18) Class-1 and -2. They provide switch- ing rates >200Mbps (100MHz) and all support a power-down mode. JTAG Boundary-Scan The UT0.25μHBD arrays provide for a test access port and boundary-scan that conforms to the IEEE Standard 1149.1 (JTAG). Some of the benefits of this capability are:
  • Easy test of complex assembled printed circuit boards
  • Gain access to and control of internal scan paths
  • Initiation of Built-In Self Test Clock Driver Distribution Aeroflex design tools provide methods for balanced clock distri- bution that maximize drive capability and minimize relative clock skew between clocked devices. Speed and Performance Aeroflex specializes in high-performance circuits designed to op- erate in harsh military and radiation environments. Table 3 presents a sampling of typical cell delays. Note that the propagation delay for a CMOS device is a function of its fanout loading, input slew, supply voltage, operating tem- perature, and processing radiation tolerance. In a radiation environment, additional performance variances must be considered. The UT0.25uHBD array family simulation models account for all of these effects to accurately determine circuit performance for its particular set of use conditions. Power Dissipation Each internal gate or I/O driver has an average power consump- tion based on its switching frequency and capacitive loading. Radiation-tolerant processes exhibit power dissipation that is typ- ical of CMOS processes. For a rigorous power estimating methodology, refer to the Aeroflex UT0.25μHBD Design Manual or consult with a Aeroflex Applications Engineer. Typical Power Dissipation 0.04μW/Gate-MHz@2.5V 20% duty cycle 0.06μW/Gate-MHz@3.3V 20% duty cycle

Table 3. Typical Cell Delays

  1. All specifications in ns (typical). Output load capacitance is 50pF. Fanout loading for input buffers and gates is the equivalent of two gate input loads. For core

cells and output buffers input slew is ~.2ns. For input buffer, input slew is 0.4ns (slew is measured from 30% - 70% of VDD).

Using a combination of state-of-the-art third-party and proprietary design tools, Aeroflex delivers the CAE support and capability to handle complex, high-performance ASIC designs from design concept through design verification and test. Aeroflex's flexible circuit creation methodology supports high level design methodology by providing synthesis libraries in Liberty syntax. Compiled technology files are provided for Synopsys synthesis and design analysis tools. Design verification is performed in any VHDL or Verilog simulation environment, using Aeroflex's robust libraries. Aeroflex also supports Automatic Test Program Generation to improve design testing. Aeroflex HDL DESIGN SYSTEMS Aeroflex offers a Hardware Description Language (HDL) design system supporting VHDL and Verilog. Both the VHDL and Verilog libraries provide sign-off quality models and robust tools. The VHDL libraries are VITAL 3.0 compliant, and the Verilog libraries are OVI 1.0 compliant.With the library capabilities Aeroflex provides, you can use High Level Design methods to synthesize your design for simulation. Aeroflex also provides tools to verify that your HDL design will result in working ASIC devices. ADV ANTAGES OF THE AEROFLEX HDL DESIGN SYSTEMS

  • The Aeroflex HDL Design System gives you the freedom to use tools from Synopsys, Mentor Graphics, Cadence, Viewlogic, and other vendors to help you synthesize and verify a design.
  • Aeroflex’s Logic Rules Checke r and Tester Rules Checker allow you to verify partial or complete designs for compliance with Aeroflex design rules.
  • Aeroflex HDL Design System accepts back-annotation of timing information through SDF. XDT sm (eXternal Design Translation) Through Aeroflex’s XDT services, customers can convert an existing non-Aeroflex design to Aeroflex’s processes. The XDT tool is particularly useful for converting an FPGA to an Aeroflex radiation-tolerant gate array. The XDT translation tools convert industry standard netlist formats and vendor libraries to Aeroflex formats and libraries. Industry standard netlist formats supported by Aeroflex include:
  • VHDL
  • Verilog HDL TM
  • FPGA source files (Actel, Altera, Xilinx)
  • E D I F
  • Third-party netlists supported by Synopsys TOOLS SUPPORTED BY AEROFLEX Aeroflex supports libraries for:
  • Mentor Graphics - ModelSim - FastScan
  • Synopsys - Design Compiler (with Power Compiler) - PrimeTime - PrimePower - Formality - TetraMax
  • VITAL-compliant VHDL Simulation Tools
  • OVI-compliant Verilog Tools Mentor ModelSim HDL Tool Supplier Completed ASIC Design Cadence Leapfrog/ Verilog XL Viewlogic SpeedWave/ VCS Synopsys VSS/VCS High Level Design Activities Aeroflex HDL Design System Aeroflex Springs HDL Design Flow

Aeroflex personnel conduct training classes tailored to meet individual needs. These classes can address a wide mix of engineering backgrounds and specific customer concerns. Applications assistance is also available through all phases of ASIC Design. Physical Design Using five layers of metal interconnect, Aeroflex achieves optimized layouts that maximize speed of critical nets, overall chip performance, and design density up to 3,000,000 equivalent gates. Test Capability Aeroflex supports all phases of test development from test stim- ulus generation through high-speed production test. This support includes ATPG , fault simulation, and fault grading. Scan design options are available on all UT0.25uHBD storage elements. Automatic test program development capabilities handle large vector sets for use with Aeroflex's LTX/Trillium MicroMaster, supporting high-speed testing (up to 80MHz with pin multiplexing), or Teradyne Tiger (up to 1.2GHz). Unparalleled Quality and Reliability Aeroflex is dedicated to meeting the stringent performance re- quirements of aerospace and defense systems suppliers. Aeroflex maintains the highest level of quality and reliability through our Quality Management Program under MIL-PRF- 38535 and ISO- 9001. In 1988, we were the first gate array manufacturer to achieve QPL certification and qualification of our technology families. Our product assurance program has kept pace with the demands of certification and qualification. Our quality management plan includes the following activities and initiatives.

  • Quality improvement plan
  • Failure analysis program
  • SPC plan
  • Corrective action plan
  • Change control program
  • Standard Evaluation Circuit (SEC) and Technology Charac- terization Vehicle (TCV) assessment program
  • Certification and qualification program Because of numerous product variations permitted with cus- tomer specific designs, much of the reliability testing is performed using a Standard Evaluation Circuit (SEC) and Tech- nology Characterization Vehicle (TCV). Aeroflex utilizes the wafer foundry's data from TCV test structures to evaluate hot carrier aging, electromigration, and time dependent test sam- ples for reliability testing. Data from the wafer-level testing can provide rapid feedback to the fabrication process, as well as establish the reliability performance of the product before it is packaged and shipped. Radiation Tolerance Aeroflex incorporates radiation-tolerance techniques in pro- cess design, design rules, array design, power distribution, and library element design. All key radiation-tolerance process pa- rameters are controlled and monitored using statistical methods and in-line testing. Notes: 1. Total dose Co-60 testing is in accordance with MIL-STD-883, Method 1019. 2. Data sheet electrical characteristics guaranteed to 3.0E5 rads(Si O2) with on-chip RAM. All post-radiation values measured at 25°C. 3. Datasheet electrical characteristics guaranteed to 1.0E6 rad (SiO2) with on- chip RAM. All post-radiation values measured at 25°C. 4. Short pulse 20ns FWHM (full width, half maximum) 25°C, 2.25V core/3.0V I/O VDD. 5 Short pulse 35ns FWHM (full width, half maximum) 125°C, 2.75V core/ 3.6V I/O VDD. 6. SEU limit based on standard evaluation circuit at 2.25V or 3.6V core/3.0V I/O VDD 25oC condition. 7. SEU-hard flip-flop cell. Non-ha rd flip-flop typical is 8E-9. 8. Dose rate upset number may be different for a specific design due to the size of the ASIC die. 9. Based on George C. Messenger, "A Summary Review of Displacement Damage from High Energy Radiation in Silicon Semiconductors and Semi- conductor Devices," IEEE Trans Nucl. Sci, vol. 39, no. 3, June 1992. PARAMETER RADIATION HARDNESS ASSURANCE NOTES Total Ionizing Dose (TID) 1.0E5 rad(SiO2) 1.0E6 rad(SiO2) 1,2 1,3 Dose Rate Upset (DRU) >6.6E9 rad(Si)/sec 4 Dose Rate Survivability (DRS) No latchup observed to max- imum dose rate of equipment configuration >4.8E11 rad(Si)/sec 5,8 Single Event Up- set (SEU) <1.2E-12 errors per cell-day 6,7 Single Event Latchup (SEL) Latchup-immune over worst case 125oC, 2.75V or 3.6V core, 3.6V I/O VDD, LET >108MeV/cm2/mg Projected neutron fluence 1.0E14 n/sq cm 9

ABSOLUTE MAXIMUM RATINGS 1 (Referenced to VSS) Note: 1. Stresses outside the listed absolute maximu m ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The recommended "power-on" sequence is VDDCORE voltage supply applied first, followed by the VDD voltage supply. The recommended "power-off" sequence is the reverse. Remove VDD voltage supply, followed by removing VDDCORE voltage supply. RECOMMENDED OPERATING CONDITIONS Note: 1. Under normal conditions, V DD must be maintained at a voltage greater than VDDCORE by 0.25V for 2.5V core option. SYMBOL PARAMETER LIMITS VDD 2 I/O DC Supply V oltage -0.3V to 4.0V VDDCORE 2 Core DC Supply V oltage -0.3 to 2.8V or -0.3 to 4.0V VDD - VDDCORE Max V oltage Difference (2.5V core) 3.6V VDDCORE - VDD Max V oltage Difference (2.5V core) 2.8V TSTG Storage temperature -65°C to +150°C TJ Maximum junction temperature +150°C ILU Latchup immunity +150mA II DC input current +10mA TLS Lead temperature (solder 5 sec) +300°C SYMBOL PARAMETER LIMITS VDD I/O DC Supply V oltage 3.3 + 0.3V VDDCORE Core DC Supply V oltage 2.5 + 0.25V or 3.3 + 0.3V

DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER CONDITION MIN MAX UNIT VIL Low-level input voltage 1 CMOS, OSC inputs PCI inputs VDD = 3.3V + 0.3V VDDCORE = 2.5V + 0.25V 0.3*VDD 0.3*VDD V VIH High-level input voltage 1 CMOS inputs PCI inputs VDD = 3.3V + 0.3 VDDCORE = 2.5V + 0.25 0.7*VDD 0.5*VDD V VIL Low-level input voltage SSTL inputs VDDSTL = 1.8V + 10% VREF = 0.9V VREF - 0.125 V VIH High-level input voltage SSTL inputs VDDSTL = 1.8V + 10% VREF = 0.9v VREF + 0.125 V VT+ Schmitt Trigger, positive going threshold1 VDD = 3.3V + 0.3 VDDCORE = 2.5V + 0.25 0.7*VDD V VT- Schmitt Trigger, negative going threshold1 VDD = 3.3V + 0.3 VDDCORE = 2.5V + 0.25 0.3VDD V VH Schmitt Trigger, typical range of hysterisis2 0.4 V IIN Input leakage current CMOS and Schmitt inputs Inputs with pull-down resistors Inputs with pull-down resistors Inputs with pull-up resistors Inputs with pull-up resistors Cold Spare Inputs - Off Cold Spare Inputs - On VIN = VDD or VSS VIN = VDD VIN = VSS VIN = VSS VIN = VDD VIN = 0 to 3.6V VIN = VDD or VSS -120 120 -10 μA VOL Low-level output voltage 3 CMOS/LVTTL 4.0mA buffer CMOS/LVTTL 8.0mA buffer CMOS/LVTTL 12.0mA buffer CMOS/LVTTL 24.0mA buffer CMOS outputs (optional) CMOS outputs (optional) PCI outputs IOL = 4.0mA IOL = 8.0mA IOL = 12.0mA IOL = 24.0mA IOL = 1.0μA IOL = 100.0μA IOL = 1500.0μA 0.4 0.4 0.4 0.4 0.05 0.25 0.1 * V DD V

SYMBOL PARAMETER CONDITION MIN MAX UNIT VOH High-level output voltage3 CMOS/LVTTL 4.0mA buffer CMOS/LVTTL 8.0mA buffer CMOS/LVTTL 12.0mA buffer CMOS/LVTTL 24.0mA buffer CMOS outputs (optional) CMOS outputs (optional) PCI outputs IOH = -4.0mA IOH = -8.0mA IOH = -12.0mA IOH = -24.0mA IOH = -1.0μA IOH = -100.0μA IOH = -500.0μA 2.4 2.4 2.4 2.4 V DD-0.05 VDD-0.35 0.9* VDD V VOL Low-level output voltage SSTL outputs VDDSTL = 1.8V - 10% IOL = 12mA 0.7 V VOH High-level output voltage SSTL outputs VDDSTL = 1.8V - 10% IOL = -12mA VDDSTL - 0.5 V IOZ Three-state output leakage current CMOS Cold Spare Inputs - Off Cold Spare Inputs - On VO = VDD and VSS VIN = 0V and 3.6V VDD = VSS = 0 VDD = VDD = VSS -10 -10 +10 +10 μA IOS Output short-circuit current 2 ,4 V/OUT= I/O drive = 4mA I/O drive = 8mA I/O drive = 12mA I/O drive = PCI V/OUT= I/O drive = 4mA I/O drive = 8mA I/O drive = 12mA I/O drive = PCI 3.0V@125oC 68mA 95mA 174mA 410mA 3.6V@-55 oC -84mA -102mA -153mA -348mA 3.6V@-55oC 143mA 204mA 340mA 764mA 3.0V@125 oC -30mA -47mA -92mA -230mA mA CIN Input capacitance 5 LVDS inputs SSTL inputs f = 1MHz @ 0V 4 15 pF COUT Output capacitance 5 4.0mA buffer 8.0mA buffer 12.0mA buffer 24.0mA buffer LVDS outputs SSTL outputs f = 1MHz @ 0V pF

CIO Bidirect I/O capacitance 5 4.0mA buffer 8.0mA buffer 12.0mA buffer PCI bidirects f = 1MHz @ 0V pF VOD1 Differential output voltage LVDS RL = 100Ω 250 800 mV VOS Offset voltage LVDS RL = 100Ω 1.12 1.6 V ΔVOD1 Change in magnitude of VOD1 for comple- mentary output states LVDS RL = 100Ω 35 mV ΔVOS1 Change in magnitude of VOS1 for complemen- tary output states LVDS RL = 100Ω 25 mV IOS LVDS Output short circuit current LVDS VIN = VDD, VOUT+ = 0V or VIN=GND, VOUT - = 0.V 9.0 mA IDDQ Quiescent Supply Current6 Group A, subgroups 1,3 VDD = 3.6V 200K gates 400K gates 600K gates 800K gates 1000K gates 1500K gates 2000K gates 2500K gates 3000K gates 100 150 200 250 375 500 625 750 Group A, subgroup 2 VDD = 3.6V 200K gates 400K gates 600K gates 800K gates 1000K gates 1500K gates 2000K gates 2500K gates 3000K gates 7.5 12.5 Group A, subgroup 1 RHA Designator: M, D, P, L, R VDD = 3.6V 200K gates 400K gates 600K gates 800K gates 1000K gates 1500K gates 2000K gates 2500K gates 3000K gates

Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density < 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF*MHz. 4. Aeroflex IOS specification - maximum of 1 second for any output to be shorted to ground or the maximum output voltage supply - exceeding this specification will reduce the DC current lifetime because of potential joule heating. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V SS at frequency of 1MHz @0V and a signal amplitude of <50mV RMS in a 144 CPGA package. 6. All inputs with internal pull-ups should be left floating. All other inputs should be tied high or low.

HP/Apollo and HP-UX are registered trademarks of Hewlett-Packard, Inc. Intel is a registered trademark of Intel Corporation Mentor, Mentor Graphics, AutoLogic II, QuickSim II, QuickFault II, QuickHDL, QuickGrade II, FastScan, FlexTest and DFT Advisor are registered trademarks of Mentor Graphics Corporation Sun is a registered trademark of Sun Microsystems, Inc. Verilog and Leapfrog are registered trademarks of Cadence Design Systems, Inc. Synopsys, Design Compiler, Test Compiler Plus, VHDL Compiler, Verilog HDL Compiler, TestSim and VSS are trademarks of Synopsys, Inc.

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