UP9616SDYA

UP9616S UPI | Alldatasheet

Document overview

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Technical content

1uP9616S-DS-F00A0, May 2018 www.upi-semi.com rebmuNredrOe pyTegakcaPg nikraMpoT 8CDS6169PuL 8-5x6NFDVS 6169Pu AYDS6169PuL 01-6x5NFDVS 6169Pu 3.3A Charger Interface, Wide Input Sensorless CC/CV Synchronous-Rectified Buck Converter for QC2.0/QC3.0/PE+1.1/PE+2.0 And FCP

Ordering Information

The uP9616S is a high-efficiency synchronous-rectified buck converter with an internal power switch. With internal low RDS(ON) switches, the high-efficiency buck converter is capable of delivering up to 3.3A output current for charger interface and a wide input voltage range from 8V to 32V. It operates in either CV (Constant Output Voltage) mode or CC (Constant Output Current) mode and provides a current limitation function. The uP9616S has a constant output voltage 5.1V/9V/12V for Qualcomm ® Quick ChargeTM 3.0/ 2.0(QC2.0/QC3.0) that is detected from D+ and D- line and automatically detects whether a connected Powered Device (PD) is Quick Charge (QC2.0/QC3.0) capable before enabling output voltage adjustment. If a PD not compliant to Quick Charge (QC2.0/QC3.0) is detected, the uP9616S disables output voltage adjustment to ensure safe operation with legacy 5.1V only USB PDs. uP9616S is a USB secondary side fast-charging converter, supporting Qualcomm ® Quick ChargeTM 3.0 (QC 3.0) High Voltage Dedicated Charging Port (HVDCP) Class A specification. uP9616S allows for selection of the output voltage of an AC/DC USB adapter based on commands from the Portable Device (PD) being powered. Selecting a higher charging voltage will reduce the charging current for a given power level resulting in reduced IR drops and increased system efficiency. Another advantage of QC3.0 is a decreased battery charging time and a reduced PD system cost thanks to the ability to select an optimum charging voltage. This eliminates the need for costly DC/DC converters within the PD. The USB-bus voltage can be controlled in discreet steps from 3.6 V up to 12.1V. The output current is limited not to exceed maximum allowable power level. Other features for the buck converter include internal soft- start, adjustable external CC (Constant Output Current) limit setting, built-in fixed line-compensation, short circuit protection, VIN/VOUT over voltage protection, and over temperature protection. It is available in space saving VDFN6x5-8L and VDFN5x6-10L packages. Note: (1) Please check the sample/production availability with uPI representatives. (2) uPI products are compatible with the current IPC/JEDEC J-STD-020 requirement. They are halogen-free, RoHS compliant and 100% matte tin (Sn) plating that are suitable for use in SnPb or Pb-free soldering processes. ††††† PDA Like Device Car Chargers ††††† Portable Charging Devices

Applications

2 uP9616S-DS-F00A0, May 2018 www.upi-semi.com BOOT SENSE+ SENSE- VIN=8V~32V VOUT = 3.6V~12.1V VIN L1 22uH GND LX 0.1uF RSENSE 39m ohm 0.1uF/16V 1uF/50V 100uF/50V USB/FCP 3.3nF 3.3 ohm 22uFx4/16V/X7R/MLCC 220uF/16V/ESR=90m ohm/EC 220uF/16V/ESR=25m ohm/OSCON uP9616SDC8 Typical Application Circuit BOOT SENSE+ SENSE- VIN=8V~32V VIN 22uH GND LX 0.1uF RSENSE 39m ohm 0.1uF/16V 1uF/50V 100uF/50V USB/FCP/QC 2.0 and 3.0 3.3nF 3.3 ohm CC2 CC1 USB Type C Detect VOUT = 3.6V~12.1V 22uFx4/16V/X7R/MLCC 220uF/16V/ESR=90m ohm/EC 220uF/16V/ESR=25m ohm/OSCON uP9616SDYA ††††† Certification: uP9616S is certified by Qualcomm® and UL. Please refer to the information below for verification: „„„„„ Qualcomm Quick Charge is a product of Qualcomm Technologies, Inc. „„„„„ UL Certificate No. 47876554328-2 for uP9616S Series „„„„„ http://www.qualcomm.com/documents/quick- charge-device-list ††††† Input Voltage Absolute Maximum Rating: 40V ††††† Wide Input Voltage Range : 8V to 32V ††††† Input Over Voltage Protection: 32.8V (min.) ††††† Up to 3.3A Output Current ††††† CV/CC Mode Control (Constant Voltage and Constant Current) ††††† Supports USB DCP Shorting D+ Line to D- Line Per USB Battery Charging Sepecification BC 1.2 ††††† Supports USB DCP Applying 2.7V on D+ Line and 2.7V on D- Line

Features

††††† Supports USB DCP Applying 1.2V on D+ Line and D- Line ††††† Compliant with Apple® and Samsung Devices ††††† Internal QC2.0/QC3.0/PE+1.1/PE+2.0/FCP Protocol and USB Type C ††††† Wide Output Voltage Range: 3.6V to 12.1V ††††† Output Voltage Accuracy: +1.5% ††††† Fixed 125kHz Frequency Operation ††††† Up to 95% Conversion Efficiency ††††† Fixed Cable Compensation Voltage ††††† Adjustable External CC (Constant Output Current) Limit Setting: Default = 3.3A ††††† CC (Constant Output Current) Limit Accurarcy:+3% ††††† Short Circuit Protection ††††† VIN/VOUT Over Voltage Protection and Over Temperature Protections ††††† VDFN6x5-8L and VDFN5x6-10L Packages ††††† RoHS Compliant and Halogen Free

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4 uP9616S-DS-F00A0, May 2018 www.upi-semi.com Functional Block Diagram Control & Protection Logic UG Driver Current Sense GND VIN LX BOOT Internal Regulator VAVCC VA UVP VREF OTP OTP EN PORPOR SENSE+ SENSE- D+ D- Current Sense/CC (Constant Output Current) Limit Amplifier Line/Cable Compensation Set Current Limit OVP FB COMP_CC COMP_CV LG Driver VCC Diff Amplifier VREF_CC VREF_OVP VREF_UVP VREF_CV EN Logic BC1.2/QC2.0/ QC3.0/FCP USB TYPE CPE+1.1/PE+2.0 CC1 CC2

6 uP9616S-DS-F00A0, May 2018 www.upi-semi.com eciveDelbatroPA ssalCPCDVH +D- De gatloVtuptuO V6.0D NGV 1.5 V3.3V 6.0V 9 V6.0V 6.0V 21 V6.0V 3.3e doMsuounitnoC 3.33 .3e gatloVsuoiverP Functional Description High Voltage Dedicated Charging Port (HVDCP) Mode After power-up pins D+ and D- of uP9616S are shorted with impedance RDCP_DAT and internal reference voltage VREF is set to V BUS voltage 5.1V. The device is in a BC1.2 compatible mode. If a portable device compatible with the Qualcomm Quick Charge specification is connected, a negotiation between HVDCP and PD is executed. Once the negotiation is successful the uP9616S opens D+ and D- short connection and D- is pulled down with a R DM_DWN. The uP9616S enters HVDCP mode. It monitors D+ and D- inputs. Based on the specified control patterns, the internal voltage reference value V REF is adjusted in order to increase or decrease output voltage to the required value. The uP9616S is available in Class A version. Class A allows to change the output voltage up to VBUS = 12V. If the unplug event is detected the decoder circuitry turns-on an internal current sink, which discharges the output capacitors to a safe voltage level. If the uP9616S is set to a Continuous mode it responds to the PD requests in a Single request mode. It does not support Group request mode. HVDCP Continuous Mode The continuous mode of operation leverages the previously unused state in QC2.0. If the portable devices try and utilize this mode, it applies voltages on D+ and D- per Table 2. Assuming the HVDCP supports this mode of operation, it will glitch filter the request as it currently does, using TGLITCH_V_CHANGE(40ms). Before the portable device can begin to increment or decrement the voltage, it must wait TV_NEW_REQUEST_CONT before pulling D+ and D- high or low. Once this time has finished, the portable device now attempts to increment or decrement the voltage. To increment, the portable device sends a pulse of width TACTIVE by pulling D+ to VDP_UP and then must return D+ to VDP_SRC for TINACTIVE. Table2. HVDCP detection voltage coding and status Note: GND is not forced by the portable device. The portable device shall go High-Z and the HVDCP pulls D- low through Rdm_dwn. This is to prevent misdetection when current flowing through GND causes the GND in the portable device to be at a higher voltage relative to HVDCP GND. Care should be taken in the portable device as this can result in a negative relative voltage on D- as seen by the portable device.

7uP9616S-DS-F00A0, May 2018 www.upi-semi.com (Note 1) ESD Rating (Note 2) D+/D-/Sense- Pin Other Pins (Note 4) Absolute Maximum Rating Thermal Information Recommended Operation Conditions Package Thermal Resistance (Note 3) Power Dissipation, PD @ TA = 25oC Note 1. Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. θJA is measured in the natural convection at TA = 25oC on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 4. The device is not guaranteed to function outside its operating conditions.

8 uP9616S-DS-F00A0, May 2018 www.upi-semi.com (VIN = 12V, T A =25oC, unless otherwise specified)

Electrical Characteristics

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9uP9616S-DS-F00A0, May 2018 www.upi-semi.com retemaraPl obmySs noitidnoCtseTn iMp yTx aMs tinU ).tnoC(noitcetorP erutarpmeTnwodtuhSlamrehTT DS --0 51- - oC siseretsyHnwodtuhSlamrehTT SYHDS --0 2- - oC )-D/+D(troPgnigrahCdetacideDegatloVhgiH egatloVtceteDataDV FER_TAD 52.05 23.00 4.0V noitceleSetgatloVtuptuO ecnerefeR V FER_LES PCDVHnoitceleSrofecnerefeRV0.2 egatloV 08.120 2.2V taPCDVHroftimiLtnerruC egatloVtuptuOynA I NIM_PCDVH tatnerrucsihttuptuotsums'PCDVHllA muminim 005- -- -A m emiTretliFhctilGwoL-DT WOL_MD_PHCTILG sinwd_mdRdnanepoeraA-/+DretfA tcepxePCDVHdluohsgnolwoh,detressa .hgihdellupgnieberofebwolyatsot-D 1- -- -s m emiTretliFhctilGhgiH-DT HGIH_MD_PHCTILG sinwd_mdRdnanepoeraA-/+DretfA ecivedelbatroparetfagnolwoh,detressa tsrifsekamtierofeb,wolog-Dsees .hgih-Dsllupdnatseuqeregatlov 04- -- -s m emiTretliFhctilGhgiH+DT enoD_CB_PHCTILG ,etelpmocsinoitceteD2.1CBretfA PCDVH 1- -0 5.1s retliFhctilGegatloVtuptuO emiT T EGNAHC_V_PHCTILG erofebelggot-/+DretfaretlifhctilG egatlovtuptuoegnahcotstpmettaPCDVH 020 40 6s m egrahcsiDsubVgulpnUT GULPNU_V niV1.5otegrahcsidotsubVrofemiT gulpnunoPCDVH --- -0 05s m emiTtrohSPCDVH-D/+DT TROHS_-D_+D PCDVHnotrohsot-D/+DrofemiT- -0 10 2s m ecnaticapaC-D+DC RWP_PCD ot-Ddna+DnoecnaticapactnelaviuqE DNG --- -1F n egakaeLeniLataDR GKL_TAD 003- -0 051k Ω ecnatsiseRnwoDlluP-DR NWD_-D 215 18 1k Ω )edoMtrohS(edoMPCD2.1CB gniruDecnatsiseR-Dot+D edoMPCD R TAD_PCD --0 20 4 Ω egatloVtuptuO+DV +V2.1_PD V21=NIV2 1.10 2.18 2.1V egatloVtuptuO-DV +V2.1_MD V21=NIV2 1.10 2.18 2.1V ecnadepmItuptuO+DR V2.1_PD Au5-=+DI0 82 010 31k Ω ecnadepmItuptuO-DV +V2.1_MD Au5-=-DI0 82 010 31k Ω )V7.2/V7.2(edoMrediviD egatloVtuptuO+DV V7.2_+D V21=NIV7 5.20 7.24 8.2V egatloVtuptuO-DV V7.2_-D V21=NIV7 5.20 7.24 8.2V ecnadepmItuptuO+DR V7.2_+D Au5-=+DI- -6 3- -k Ω ecnadepmItuptuO-DR V7.2_-D Au5-=-DI- -6 3- -k Ω

10 uP9616S-DS-F00A0, May 2018 www.upi-semi.com VOUT (2V/Div) VIN (5V/Div) LX (10V/Div) IL (5A/Div) VOUT (2V/Div) VIN (5V/Div) LX (10V/Div) IL (5A/Div) D- (1V/Div) D+ (1V/Div) VOUT (5V/Div) IL (2A/Div) D- (1V/Div) D+ (1V/Div) VOUT (5V/Div) IL (2A/Div) VOUT (2V/Div) VIN (5V/Div) LX (10V/Div) IL (2A/Div) VOUT (2V/Div) VIN (5V/Div) LX (10V/Div) IL (2A/Div) Typical Operation Characteristics Output Short Circuit Protection Time : 400ms/Div VIN = 12V, VOUT = 5.1V, IOUT = 3A Output Short Circuit Protection Recover Power On Waveforms Time : 4ms/Div VIN = 12V, VOUT = 5.1V, IOUT = 3A Power Off Waveforms Time : 40ms/Div VIN = 12V, VOUT = 5.1V, IOUT = 3A HVDCP Detection Voltage Status Waveforms Time : 100ms/Div VIN = 12V, VOUT = 5.1V to 9V, IOUT = 3A HVDCP Detection Voltage Status Waveforms Time : 100ms/Div VIN = 12V, VOUT = 5.1V to 12V, IOUT = 3A Time : 400ms/Div VIN = 12V, VOUT = 5.1V, IOUT = 3A

11uP9616S-DS-F00A0, May 2018 www.upi-semi.com

Application Information

Output inductor selection is usually based on the considerations of inductance, rated current value, size requirements and DC resistance (DCR). The inductance is chosen based on the desired ripple current. Large value inductors result in lower ripple currents and small value inductors result in higher ripple currents. Higher V IN or V OUT also increases the ripple current as shown in the equation below. A reasonable starting point for setting ripple current is ∆I L = 900mA (30% of 3000mA). V1(VLf IN OUT OUT OUTOSC L −××=∆ Maximum current ratings of the inductor are generally specified in two methods: permissible DC current and saturation current. Permissible DC current is the allowable DC current that causes 40 oC temperature raise. The saturation current is the allowable current that causes 10% inductance loss. Make sure that the inductor will not saturate over the operation conditions including temperature range, input voltage range, and maximum output current. If possible, choose an inductor with rated current higher than 5A so that it will not saturate even under current limit condition. The size requirements refer to the area and height requirement for a particular design. For better efficiency, choose a low DC resistance inductor. DCR is usually inversely proportional to size. Different core materials and shapes will change the size, current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends on the price vs. size requirements and any radiated field/EMI requirements. Input Capacitor Selection The input capacitor needs to be carefully selected to maintain sufficiently low ripple at the supply input of the converter. A low ESR capacitor is highly recommended. Since large current flows in and out of this capacitor during switching, its ESR also affects efficiency. The input capacitance needs to be higher than 22uF. The best choice is he ceramic type and low ESR electrolytic types may also be used provided that the RMS ripple current rating is higher than 50% of the output current. In the case of the electrolytic types, they can be further away if a small parallel 1uF ceramic capacitor is placed right close to the IC. A 100uF elecrolytic capacitor and 1uF ceramic capacitor are recommended and placed close to VIN and GND pins, with the shortest traces possible. Output Capacitor Selection The ESR of the output capacitor determines the output ripple voltage and the initial voltage drop following a high slew rate load transient edge. The output ripple voltage can be calculated as: )Cf8 1ESR(IV TOUOSC Where f OSC = operating frequency, C OUT = output capacitance and ∆IC = ∆IL = ripple current in the inductor. The ceramic capacitor with low ESR value provides the low output ripple and low size profile. In the case of electrolytic capacitors, the ripple is dominated by R ESR multiplied by the ripple current. Connect a 220uF electrolytic capacitor at output SENSE+ terminal for good performance and low output ripple and place output capacitor5s as close as possible to the device. In the case of ceramic output capacitors, R ESR is very small and does not contribute to the output ripple. Connect a 0.1uF ceramic capacitor at output SENSE- terminal for good performance and place output capacitors as close as possible to the device. PCB Layout Consideration The PCB layout is an important step to maintain the high performance of the uP9616S. High switching frequencies and relatively large peak currents make the PCB layout a very important part of all high frequency switching power supply design. Both the high current and the fast switching nodes demand full attention to the PCB layout to save the robustness of the uP9616S through the PCB layout. Improper layout might show the symptoms of poor load or lineregulation, radiate excessive noise at ground or input, output voltage shifts, stability issues, unsatisfying EMI behavior or worsened efficiency. Follow the PCB layout guidelines for optiomal performances of uP9616S.

12 uP9616S-DS-F00A0, May 2018 www.upi-semi.com Layout Guidelines For uP9616SDC8: 1. Arrange the power components to reduce the AC loop size consisting of CIN, VIN (Pin 1, 2) and LX (Pin 8) 2. The input decoupling ceramic capacitor 1uF must be placed closest to the VIN (Pin 1, 2) and Exposed Pad GND plane through vias or a short and wide path. 3. Return SENSE+ (PIN 6) to signal GND pin, and connect the signal GND to power GND at a single point for best noise immunity. Connect exposed pad to power ground opper area with copper and vias. 4. Apply copper plane to Exposed Pad GND for best heat dissipation and noise immunity. The exposed pad is the main path for heat convection and should be well-soldered to the PCB for best thermal performance. 5. Use a short trace connecting the bootstrap capacitor C BOOT to BOOT (Pin 7) and LX (Pin 8) to form a bootstrap circuit. 6. Use a short trace connecting R-C to LX (Pin 8) and Exposed Pad GND Plane to form a Snubber Circuit. 7. The LX (Pin 8) pad is the noise node switching from VIN (Pin 1, 2) to GND. LX node copper area should be minimized to reduce EMI and should be isolated from the rest of circuit for good EMI and low noise operation. 8. The D+ (Pin 3) pad and D- (Pin 4) pad of the uP9616S are the USB detect data line input node, the D+ and D- Pin of the via or trace area should be isolated using 0.96mm space to prevent direct contact with VIN area components which may cause voltage of D+ and D- pins to exceed maximum rating of 6V. uP9616SDC8 VIN Plane SENSE+ Plane+ GND USB Connector SENSE- Plane GND Plane GND Plane Via to D+ Via to D- Via to GND Plan Exposed Pad (GND) 4 5

13uP9616S-DS-F00A0, May 2018 www.upi-semi.com Layout Guidelines For uP9616SDYA: 1. Arrange the power components to reduce the AC loop size consisting of CIN, VIN (Pin 5) and LX (Pin 6,7) 2. The input decoupling ceramic capacitor 1uF must be placed closest to the VIN (Pin 5) and Exposed Pad GND plane through vias or a short and wide path. 3. Return SENSE+ (PIN 9) to signal GND pin, and connect the signal GND to power GND at a single point for best noise immunity. Connect exposed pad to power ground copper area with copper and vias. 4. Apply copper plane to Exposed Pad GND for best heat dissipation and noise immunity. The exposed pad is the main path for heat convection and should be well-soldered to the PCB for best thermal performance. 5. Use a short trace connecting the bootstrap capacitor C BOOT to BOOT (Pin 8) and LX (Pin 6,7) to form a bootstrap circuit. 6. Use a short trace connecting R-C to LX (Pin 6,7) and Exposed Pad GND Plane to form a Snubber Circuit. 7. The LX (Pin 6,7) pad is the noise node switching from VIN (Pin 5) to GND. LX node copper area should be minimized to reduce EMI and should be isolated from the rest of circuit for good EMI and low noise operation. 8. The CC1 (Pin 4), CC2 (Pin 5), D+ (Pin 2) pad and D- (Pin 1) pad of the uP9616S are the USB detect data line input node, the CC1, CC2, D+ and D- Pin of the via or trace area should be isolated using 0.96mm space to prevent direct contact with VIN area components which may cause voltage of CC1, CC2, D+ and D- pins to exceed maximum rating of 6V. uP9616SDYA VIN Plane SENSE+ Plane+ GND USB Connector SENSE- Plane GND Plane GND Plane Via to D+ Via to D- Via to GND Plan Exposed Pad (GND) 2 9 1 10 Via to CC2 Via to CC1 CC1 CC2

14 uP9616S-DS-F00A0, May 2018 www.upi-semi.com

Package Information

1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm. VDFN6x5 - 8L θ 0.80 - 1.00 0.31 - 0.511.27 BSC

6.00 BSC

5.00 BSC

3.25 - 3.55 0.50 - 0.80 3.85 - 4.15 0.20 REF 0.00 - 0.05

15uP9616S-DS-F00A0, May 2018 www.upi-semi.com 0.31 - 0.51 2.60 - 2.80 4.40 - 4.60 0.00 - 0.050.20 REF 5 1 1.20BSC 106 Note 1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm. θ

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