UP8815PDDA

UP8815 UPI | Alldatasheet

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Technical content

Features

Note: (1) Please check the sample/production availability with uPI representatives. (2) uPI products are compatible with the current IPC/JEDEC J-STD-020 requirement. They are halogen-free, RoHS com- pliant and 100% matte tin (Sn) plating that are suitable for use in SnPb or Pb-free soldering processes. Pin Configuration PGOOD GND VCNTL EN REFIN VIN VOUT PGND GND DFN3x3-10L VSENSE 5 REFOUT6

2 uP8815-DS-F00A0, Apr. 2018 www.upi-semi.com .oNniPe maNn oitcnuFniP 1N IFER .tupnIecnerefeR 2N IV .egatloVtupnI ottnerrucseilppustahtecivedrewopehtottupniniardehtsisihT roftupni5188PuehtnoFu01tsaeltaforoticapaccimarecaesU.niptuptuoeht .esnopsertneisnartgnivorpmidnaytilibats 3T UOV .egatloVtuptuO muminimA.ecivedehtfotuptuorewopehtsinipsihT simumixamehtdnA.dednemmocersiroticapactuptuo3xFu01foecnaticapac .roticapacFu05 4D NGP .rotalugeRfodnuorGrewoP 5E SNESV .ODLehtrofesneSetomeRegatloVtuptuO 6T UOFER .tuptuOecnerefeR .dnuorgotnipsihtmorfroticapaccimarecFu1.0atcennoC 7N E .tupnINE eht,wolllupsinipNEehtfI.elbanelliwCIeht,hgihllupsinipNEehtfI .ecnatsiserlanretnihguorhtegatlovtuptuoehtegrahcsidnehtdnaelbasidlliwCI DNG .dnuorGlangiS .nipsihtottcepserhtiwderusaemeraslevelegatlovllA daPdesopxE 9D OOGP .noitacidnIdooGrewoP hgihehtsatessidnatuptuoniard-neponasinipsihT .wodniwdoogrewopsretneTUOVecnoecnadepmi 01L TNCV .tiucriClortnoCroftupnIylppuS lortnocehtotegatlovsaibsedivorpnipsihT tnerructuptuofoytilibapacgnivirdehT.rotsisnartssapehtrofrevirddnayrtiucric Vehtotdenoitroporpsi .LTNC nipsihtnoegatloveht,etalugerotecivedehtroF Vnahtsselondna,egatlovtuptuoehtnahtretaergV5.1tsaeltaebtsum NIM_LTNC Functional Pin Description Typical Application Circuit VIN PGOOD VCNTL VOUT VIN EN REFIN RPGOOD 100K R2 uP8815 PGND CIN 10uF CCNTL 1uF~4.7uF Enable REFOUT VSENSE VOUT COUT 10uFx3 VCNTL REFOUT GND 0.1uF 0.1uF 10Ω

3uP8815-DS-F00A0, Apr. 2018 www.upi-semi.com Functional Block Diagram VINVCNTL EN VSENSE PGOOD GND VOUT Current Limit EA Control Logic VCNTL/REFIN UVLO Protection Thermal ProtectionEN REFIN Delay REFOUT PGND Current Sense Current Sense Buffer PGOOD Window

4 uP8815-DS-F00A0, Apr. 2018 www.upi-semi.com Source/Sink Current Limit The uP8815 monitor sourcing and sinking output currents and it has a constant over current limit by reducing Power MOSFET gate voltage. Note that the current limit level will be folded back to be one half when the output voltage is lower than 0.3V. This reduction is a non-latch protection. Power Good The PGOOD is an open drain that asserts high with 2 ms (typ) delay time after the VOUT enters power good window which is V SENSE within +20% of REFOUT. When the VSENSE is out of the PGOOD window, PGOOD de-asserts within 10us (typ). REFOUT This buffer generates the DDR VTT reference and is ca- pable of supporting both a sourcing and sinking load of 10mA. REFOUT is independent of the EN pin state. VCNTL UVLO Protection The V CNTL UVLO protection through monitor VCNTL. If VCNTL is less than the UVLO threshold voltage, Both V OUT and REFOUT regulators are powered off. REFIN The RFFIN has UVLO protection. And It can be set by ex- ternal equivalent ratio voltage divider connected to the memory supply bus (VDDQ). EN Control The uP8815 features an enable pin for enable/disable con- trol of the chip. Pulling V EN lower than 0.3V disables, an internal discharge MOSFET of 18Ω RDS(ON) turns on to pull output voltage to ground. Pulling VEN higher than 1.7V en- ables the output voltage. Functional Description

5uP8815-DS-F00A0, Apr. 2018 www.upi-semi.com Note 1. Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. θJA is measured in the natural convection at TA = 25oC on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 4. The case temp location for measuring θJC is on the top of the package. Note 5. The device is not guaranteed to function outside its operating conditions. (Note 1) Control Input Voltage,VCNTL Power Input Voltage,VIN ESD Rating (Note 2) Package Thermal Resistance (Note 3) Power Dissipation, PD @ TA = 25OC (Note 4) Absolute Maximum Rating Thermal Information Recommended Operation Conditions

6 uP8815-DS-F00A0, Apr. 2018 www.upi-semi.com

Electrical Characteristics

retemaraP lobmySs noitidnoCtseTn iMp yTx aM stinU tupnIylppuSLTNCV dlohserhTROPLTNCVV HTRLTNC V HTRLTNC gnisir5 .27 .25 8.2V siseretsyHROPLTNCVV SYHLTNC V HTRLTNC gnillaf- -2 .0- -V tnerruCnwodtuhSLTNCVI LTNCV_DS V NE V= NIFER I,V0= TUO A0=- -5 60 8A u tnerruCybdnatSLTNCVI LTNCV_BS V NE V,V0= NIFER I,V4.0> TUO A0=- -0 020 04A u tnerruCtupnILTNCVI LTNCV V NE V= LTNC I,V5= TUO V,A0= NIFER V4.0>- -7 .01 A m tupnIylppuSNIV tnerruCylppuSNIVI NIV V NE V= LTNC I,V5= TUO V,A0= NIFER V4.0>- -1 0 5A u tnerruCnwodtuhSNIVI NIV_NDHS V NE V= NIFER daoLoN,V0=- -1 .00 5A u tnerruCybdnatSNIVI NIV_BS V NE V,V0= NIFER I,V4.0> TUO A0=- -- -0 5A u egatloVtuptuO egatloVtuptuO V TUO TUOFERottesffOegatloVTUOVV SO_TUO I TUO V,A2+= NI V,V5.1= TUOFER V57.0=5 2-- -5 2 VmI TUO V,A2+= NI V,V53.1= TUOFER V576.0=5 2-- -5 2 I TUO V,A2+= NI V,V2.1= TUOFER V6.0=5 2-- -5 2 noitalugeRdaoL ∆V DAOL I<A1- TUO A1<0 2-- -0 2V m ecnatsiseRegrahcsiDTUOVR EGRAHCSID V NIFER V,V0= TUO V,V3.0= NE V0=- -8 15 2 Ω timiLtnerruCecruoSTUOVI RS_TUOV_MIL V TUO wodniWDOOGPni5 .35 .45 .5A timiLtnerruCkniSTUOVI KS_TUOV_MIL V TUO wodniWDOOGPni5 .35 .45 .5A TUOFER/NIFER dlohserhThgiHcigoLNIFER V HNE ecivedehtelbaneotgnisirNIFER0 630 930 24V m dlohserhTwoLcigoLNIFER V LNE ecivedehtelbasidotgnillafNIFER- -0 2- -V m tnerruCtupnINIFER I NIFER V NE V= LTNC --- -1 A u egnaRegatloVNIFER V NIFER 5.0- -8 .1V otecnareloTegatloVTUOFER NIFER V TUOFER_LOT I<Am01- TUOFER V,Am01< NIFER V57.0=5 1-- -5 1 VmI<Am01- TUOFER V,Am01< NIFER V576.0=5 1-- -5 1 I<Am01- TUOFER V,Am01< NIFER V6.0=5 1-- -5 1 timiLtnerruCecruoSTUOFER I RS_TUOFER_MIL V TUOFER V0=0 10 4- -A m timiLtnerruCkniSTUOFER I KS_TUOFER_MIL V TUOFER V= NIFER V1+0 10 4- -A m (VCNTL = 5V, COUT = 10uFx3, T A = 25OC, unless otherwise specified)

7uP8815-DS-F00A0, Apr. 2018 www.upi-semi.com retemaraP lobmySs noitidnoCtseTn iMp yTx aM stinU noitcetorPlamrehT erutarepmeTnwodtuhSlamrehTT DS --0 61- - oC siseretsyHnwodtuhSlamrehTT SYH_HDS --0 3- - oC DOOGP dlohserhTDOOGP V DOOGP_HT V ESNES ottcepserhtiwdlohserhtrewol TUOFER 52-0 2-5 1- %V ESNES ottcepserhtiwdlohserhtreppu TUOFER 510 25 2 siseretsyHDOOGP- -5- - yaleDpu-tratSDOOGP T 1YALEDGP V,yaledgnisirpu-tratS ESNES nihtiw egnarDOOGP --2- -s m egatloVwoLtuptuO V DOOGP_WOL I DOOGP Am4=- -- -4 .0V yaleDgnillaFDOOGP T 2YALEDGP V,yaledgnillaF ESNES fotuosi egnarDOOGP --0 1- -s u tnerruCegakaeL I DOOGP_EGAKAEL V ESNES V= NIFER hgihDOOGP( V.)ecnedepmi DOOGP V0.3+NIV= --- -1 A u dlohserhTNE egatloVtupnINE V NE 7.1- -- -V V DS --- -3 .0V _ _

8 uP8815-DS-F00A0, Apr. 2018 www.upi-semi.com The uP8815 is an ultra low dropout linear regulator specifically designed to provide termination voltage for DDR memory system. Designed with low on-resistance NMOSFETs, this device is capable of sinking/sourcing up to 3A output current. The output voltage is tightly regulated to track reference voltage input with fast to line/load transient. Supply Voltage for Control Circuit VCNTL This uP8815 works with dual supplies, a control input for the control circuitry and a power input as low as 1.0V for providing current to output. The control input provides bias current for control circuit and gate voltage for turning on and off the NMOSFETs. It is highly recommended to keep the control input 1.5V higher than the output voltage for optimal performance. The control voltage should be locally bypassed by a minimum 1uF ceramic capacitor plus a 10Ω resistor. Power Input Capacitor (C IN) and Control Input Capacitor (CCNTL) The VIN pin supplies current to output when the upper MOSFET turns on. The uP8815 is designed to work with minimum 10uF ceramic input capacitor. When work with large output capacitor, the uP8815 may demand large input current during soft start. Make sure the power input is capable of delivering up to 3A. Table 1 Component Recommended Value tnenopmoCe ulaVdednemmoceR C LTNC roticapaCcimareCFu7.4~Fu1 CNI roticapaCcimareCretaergroFu01 Reference Input The output voltage is regulated to track the reference input at REFIN pin. The reference input can be obtained from power input by voltage divider or from an independent voltage reference. A ceramic capacitor physically near the IC is required to filter the reference voltage. Output Voltage and Output Capacitor, C OUT The uP8815 is designed to work with low ESR ceramic capacitors. Attach three, 10-uF ceramic capacitors in parallel to minimize the effect of equivalent series resistance (ESR) and equivalent series inductance (ESL). Thermal Consideration The uP8815 integrates internal thermal limiting function to protect the device from damage during fault conditions. However, continuously keeping the junction near the thermal shutdown temperature may remain possibility to affect device reliability. It is highly recommended to keep the junction temperature below the recommended operation condition 125 oCfor maximum reliability. Power dissipation in the device is calculated as: PD = (VIN - VOUT) x IOUT + VCNTL x ICNTL

Application Information

It is adequate to neglect power loss with respective to control circuit V CNTL x I CNTL when considering thermal management in uP8815. This power dissipation is conducted through the package into the ambient environment, and, in the process, the temperature of the die (T J) rises above ambient. Large power dissipation may cause considerable temperature raise in the regulator in large dropout applications. The geometry of the package and of the printed circuit board (PCB) greatly influence how quickly the heat is transferred to the PCB and away from the chip. The most commonly used thermal metrics for IC packages are thermal resistance from the chip junction to the ambient air surrounding the package (∆T JA): θJA = ( TJ -TA ) / PD θJA specified in the Thermal Information section is measured in the natural convection at TA = 25oC on a high effective thermal conductivity test board (4 Layers, 2S2P) of JEDEC 51-5 thermal measurement standard. Given power dissipation P D, ambient temperature and thermal resistance θJA, the junction temperature is calculated as: TJ = TA + ∆TJA = TA + PD x θJA To limit the junction temperature within its maximum rating, the allowable maximum power dissipation is calculated as: P D(MAX) = ( TJ(MAX) -TA ) / θJA where T J(MAX) is the maximum operation junction temperature 125oC, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance.

9uP8815-DS-F00A0, Apr. 2018 www.upi-semi.com

Package Information

1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm. 6 10 0.18 - 0.300.50 BSC 2.90 - 3.10 2.90 - 3.10 1.40 - 1.80 0.00 - 0.050.20 REF 0.70 - 0.80

10 uP8815-DS-F00A0, Apr. 2018 www.upi-semi.com Important Notice uPI and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. uPI products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment. However, no responsibility is assumed by uPI or its subsidiaries for its use or application of any product or circuit; nor for any infringements of patents or other rights of third parties which may result from its use or application, including but not limited to any consequential or incidental damages. No uPI components are designed, intended or authorized for use in military, aerospace, automotive applications nor in systems for surgical implantation or life-sustaining. No license is granted by implication or otherwise under any patent or patent rights of uPI or its subsidiaries. COPYRIGHT ( C) 2015, UPI SEMICONDUCTOR CORP. uPI Semiconductor Corp. Headquarter 9F.,No.5, Taiyuan 1st St. Zhubei City, Hsinchu Taiwan, R.O.C. uPI Semiconductor Corp. Sales Branch Office 12F-5, No. 408, Ruiguang Rd. Neihu District, Taipei Taiwan, R.O.C.