UP8208P UPI | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 21

Technical content

1uP8208P/Q-DS-F0100, Mar. 2018 www.upi-semi.com General Description Features The uP8208P/Q series is used for secondary protection of lithium-ion rechargeable batteries, and incorporates a high- accuracy voltage detection circuit and a delay circuit. Short circuits between cells accommodate series connection of two to four cells. In order to drive an external RTC. A voltage regulator of 3.3V(uP8208P) or 3.0V(uP8208Q) is incorporated in uP8208P/Q. uP8208P/Q is available in the WDFN2x2-8L package. Li-Ion/Polymer 2/3/4-Cell Second Protection IC + Voltage Regulator Note: (1) Please check the sample/production availability with uPI representatives. (2) uPI products are compatible with the current IPC/JEDEC J-STD-020 requirement. They are halogen-free, RoHS compliant and 100% matte tin (Sn) plating that are suitable for use in SnPb or Pb-free soldering processes. † †† †† High Accuracy Voltage Detection Circuit for Each Cell „ „„ „„ Overcharge Detection Voltage n (n = 1 to 4) 4.3V to 4.6V (in 50mV steps) Accuracy: 20mV (+25oC) Accuracy: 25mV (0oC to +60oC) „ „„ „„ Overcharge Hysteresis Voltage n (n = 1 to 4) † †† †† Delay Time for Overcharge Detection Can Be Set by An Internal Circuit (No External Capacitor Required) „ „„ „„ Optional Overcharge Detection Delay Time: 2s, 4s, 6s, and 8s „ „„ „„ Optional Output Delay of Shutdown: 2s, 4s, 6s, and 8s † †† †† High Withstand Voltage Devices: „ „„ „„ Absolute Maximum Rating: 32V „ „„ „„ Wide Operating Voltage Range: 4V to 24V † †† †† Wide Operating Temperature Range: -40oC to +85oC † †† †† Low Current Consumption „ „„ „„ At 3.1V for Each Cell: 5.0uA max.(+25oC) „ „„ „„ At 2V for Each Cell: 0.4uA max. (+25oC) † †† †† CO Pull Up Voltage: 4.7V † †† †† Support Test Mode to Shorten Mass Production Time † †† †† Voltage Regulator: „ „„ „„ VOUT Off Voltage: 2.3V/2.5V/2.8V „ „„ „„ Output Current: 2mA (max.) „ „„ „„ VR Short Circuit Protection † †† †† RoHS Compliant and Halogen Free

Applications

† †† †† Lithium-Ion Rechargeable Battery Packs (for Secondary Protection) † †† †† Notebook Computers † †† †† Portable Instrumentation † †† †† Portable Equipment r e b m u N r e d rOe g a k c aPk r a m e R Y X - 8 N D P 8 0 2 8 P u L 8 - 2 x 2 N F D W e p y T d l o h s e r h T e g a t l o V : X e p y T e m i T y a l e D : Y ro f e g a p t x e n e h t o t r e f e R ( ) . n o i t i n i f e d Y X d e l i a t e dY X - 8 N D Q 8 0 2 8 P u V 0 . 3 = T U O V : Q 8 0 2 8 P u ; V 3 . 3 = T U O V : P 8 0 2 8 P u Pin Configuration

Ordering Information

Line1 : Product Code Line2 : Date Code Number 6 5 3 4 uP8208QDN8-XY 8 7 1 2 HAXY XXXXXX Line1 : Product Code Line2 : Date Code Number

2 uP8208P/Q-DS-F0100, Mar. 2018 www.upi-semi.com ) X ( e p y T e g r a h c r e v O e g a t l o V n o i t c e t o r P V (U C) n w o d t u h S e g a t l o V d l o h s e r h T V (D S) e m i T y a l e D ) Y ( e p y T e g r a h c r e v O y a l e D n o i t c e t e D e m i T t (U C) y a l e D n w o d t u h S e m i T t (D S) A 0 3 . 4 V 3 .2A s 2 s 2 BV 5 .2B s 4 CV 8 .2C s 6 D 5 3 . 4 V 3 .2D s 8 EV 5 .2E s 4 s 2 FV 8 .2F s 4 G 0 4 . 4 V 3 .2G s 6 HV 5 .2H s 8 IV 8 .2I s 6 s 2 J 5 4 . 4 V 3 .2J s 4 KV 5 .2K s 6 LV 8 .2L s 8 M 0 5 . 4 V 3 .2M s 8 NV 5 .2N s 4 OV 8 .2O s 6 P 5 5 . 4 V 3 .2P s 8 QV 5 . 2 RV 8 . 2 S 0 6 . 4 V 3 . 2 TV 5 . 2 UV 8 . 2

3uP8208P/Q-DS-F0100, Mar. 2018 www.upi-semi.com Typical Application Circuit Cautions: 1. The above connection example does not guarantee operation. Perform thorough evaluation using the actual application. 2. Cell connection: To prevent incorrect output activation, the VSS pin must be connected first. Follow the connecting sequence below: Configuration of 4 serial cell : BAT4 -> BAT3 -> BAT2 -> BAT1 Configuration of 3 serial cell : BAT3 -> BAT2 -> BAT1 Configuration of 2 serial cell : BAT2 -> BAT1 VDD R VDD C VDD VC2 VC4 VC3 VC1 COC1 PB- PB+ SC Protector BAT1 BAT2 BAT3 BAT4 C4 VSS VOUT C VOUT

4 uP8208P/Q-DS-F0100, Mar. 2018 www.upi-semi.com Functional Block Diagram Control Logic Vref2pdn Vref2 Overcharge Detection Comparator 3 Oscillator Overcharge Detection / Release Delay Circuit VDD VC1 VC2 VC3 Overcharge Detection Comparator 2 Vref3 Vref1pdn Vref1 Overcharge Detection Comparator 1 Vref3pdn Shutdown Detection Comparator 1 Shutdown Detection Comparator 2 Shutdown Detection Comparator 3 Regulator VOUT VDD VDD CO Overcharge Detection Comparator 4 VC4 VSS Vref4 Vref4pdn Shutdown Detection Comparator 4

5uP8208P/Q-DS-F0100, Mar. 2018 www.upi-semi.com The uP8208P/Q series is used for secondary protection of lithium-ion rechargeable batteries, and incorporates a high accuracy voltage detection circuit and a delay circuit. Short circuits between cells accommodate series connection of two to four cells. In order to drive an external RTC. A voltage regulator of 3.3V(uP8208P) or 3.0V(uP8208Q) is incorporated in uP8208P/Q. Overcharge Detection The uP8208P/Q monitors VC1 to VC2, VC2 to VC3, VC3 to VC4, and VC4 to VSS voltage for over voltage protection. When the voltage of any cell exceeds VCU during charging and lasts for equal to or longer than Overcharge Detection Delay Time (tCU ), CO pin turns to H. This is called overcharge protection mode. CO pin drives the connecting FET to provide charge control and a second protection. Once the voltage of each cell is lower than VCUn + VHCn and lasts for 16ms(Typ.) or longer, uP8208P/Q enters normal mode. Test Mode Overchage Detection Delay Time (tCU ) can be shortened by entering the test mode. The test mode can be triggered by forcing a voltage equal to or higher than 4.0V between VDD pin and VC1 for 40ms or longer. The test mode is retained by internal latch even if the voltage of VDD pin drops to the same level as the voltage of VC1. After overcharge event occurs, uP8208P/Q resets the latch for retaining the test mode and exits test mode under the overcharge state. Functional Pin Description . ONe m aNn o i t c n u F n i P 1D DV. n i P t u p n I r e w o P e v i t i s o P 21 CV. 1 y r e t t a B f o n i P n o i t c e n n o C e g a t l o V e v i t i s o P 32 C V . 1 y r e t t a B f o n i P n o it c e n n o C e g a t l o V e v i t a g e N . 2 y r e t t a B f o n i P n o i t c e n n o C e g a t l o V e v i t i s o P 43 C V . 2 y r e t t a B f o n i P n o i t c e n n o C e g a t l o V e v i t a g e N . 3 y r e t t a B f o n i P n o i t c e n n o C e g a t l o V e v i t i s o P

54 C V 3 y r e t t a B f o n i P n o i t c e n n o C e g a t l o V e v i t a g e N

. 4 y r e t t a B f o n i P n o i t c e n n o C e g a t l o Ve v i t i s o P 6S S V . 4 y r e t t a B f o n i P n o i t c e n n o C e g a t l o V e v i t a g e N . n i P t u p n I r e w o P e v i t a g e N 7O C. e g r a h C r o f n i P n o i t c e n n o C e t a GT E F 8T U OV. n i P t u p t u O r o t a l u g e R e g a t l o V d a P d e s o p xEC N. d e t c n n o C t o N Functional Description Overcharge Timer Reset When an overcharge release noise that forces the voltage of the battery temporarily below the overcharge detection voltage (VCU ) is input during the overcharge detection delay time (tCU ) counting period. The overcharge detection delay time will be continuously counted if the period of overcharge release noise is shorter than the overcharge timer reset delay time (tTR ). Otherwise, counting of tCU will be reset if the period of overcharge release noise is equal to tTR or longer. After that, when VCU has been exceeded, counting tCU resumes. Shutdown Detection The uP8208P/Q monitors VC1 to VC2, VC2 to VC3, VC3 to VC4, and VC4 to VSS voltage for shutdown protection. When the voltage of any cell is less than the VSD during discharge and lasts for equal to or longer than shutdown delay time (tSD ), VOUT pin turns to L. Once the voltage of each cell exceeds VSDn + 0.3V(typ.) , uP8208P/Q enters normal mode and VOUT pin becomes to H.

Table 1. Constants for 4-Serial cell External Components

  1. The above constants are subject to change without prior
  2. It has not been confirmed whether the operation is normal

application to set the constant.

  1. Set the same constants to R1 to R4 and to C1 to C4 and
  2. Set RVDD , C1 to C4, and CVDD so that the condition (RVDD )
  3. Set R1 to R4, C1 to C4, and CVDD so that the condition

(R1 to R4) . (C1 to C4, CVDD ) > 1x10-4is satisfied.

  1. Cell connections: To prevent incorrect output activation,

Table 2. Constants for 3-serial cell External Components

  1. The above constants are subject to change without prior
  2. It has not been confirmed whether the operation is normal

application to set the constant.

  1. Set the same constants to R1 to R3 and to C1 to C3 and
  2. Set RVDD , C1 to C3, and CVDD so that the condition (RVDD )
  3. Set R1 to R3, C1 to C3, and CVDD so that the condition

(R1 to R3) . (C1 to C3, CVDD ) > 1x10-4is satisfied.

  1. Cell connections: To prevent incorrect output activation,

Table 3. Constants for 2-serial cell External Components depends on voltage drop on VDD pin.

  1. The above constants are subject to change without prior
  2. It has not been confirmed whether the operation is normal

application to set the constant.

  1. Set the same constants to R1 to R2 and to C1 to C2 and
  2. Set RVDD , C1 to C2, and CVDD so that the condition (RVDD )
  3. Set R1 to R2, C1 to C2, and CVDD so that the condition

(R1 to R2) . (C1 to C2, CVDD ) > 1x10-4is satisfied.

  1. Cell connections: To prevent incorrect output activation,

Do not connect batteries charged with VCU + VHC or more. evaluation with the actual application circuit.

8 uP8208P/Q-DS-F0100, Mar. 2018 www.upi-semi.com Functional Description The application conditions for the input voltage, output voltage, and load current should not exceed the package power dissipation. Do not apply to this IC an electrostatic discharge that exceeds the performance ratings of the built-in electrostatic protection circuit. uPI claims no responsibility for any disputes arising out of or in connection with any infringement of patents owned by a third party by products including this IC.

9uP8208P/Q-DS-F0100, Mar. 2018 www.upi-semi.com Functional Description Timing Chart Overcharge Protection Battery Voltage Shorter than tCU tCU VHCn VCUn ( n = 1, 2, 3, 4) \ \ CO Output Voltage shorter than tTR 16ms typ. Test Mode 16ms typ. 4.0V or more Battery Voltage tTST = 40ms max VDD Pin Voltage VC1 Pin Voltage (n = 1, 2, 3, 4) VCUn Test Mode CO Output Voltage a hundred twenty eighth of tCU VDD Pin Voltage VHCn

10 uP8208P/Q-DS-F0100, Mar. 2018 www.upi-semi.com Functional Description Overcharge Timer Reset Voltage Regulator Operation Battery Voltage-1 VCU VSDR VSD Battery Voltage-2 VCU VSDR VSD Battery Voltage-3 VCU VSDR VSD Battery Voltage-4 VCU VSDR VSD VOUT tSD Normal Mode Shutdown Mode Normal Mode Battery Voltage Shorter than tCU tCU VHCn VCUn ( n = 1, 2, 3, 4) CO Output Voltage shorter than tTR Longer than tTR Timer reset

11uP8208P/Q-DS-F0100, Mar. 2018 www.upi-semi.com (Note 1) ESD Rating (Note 2) (Note 4) Absolute Maximum Rating Thermal Information Recommended Operation Conditions Note 1. Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. θ JA is measured in the natural convection at TA = 25oC on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 4. The device is not guaranteed to function outside its operating conditions. Package Thermal Resistance (Note 3) Power Dissipation, PD @ TA = 25oC

12 uP8208P/Q-DS-F0100, Mar. 2018 www.upi-semi.com

Electrical Characteristics

(TA=25oC, unless otherwise specified) r e t e m a r aPl o b m ySs n o i t i d n o C t s eTn iMp yTx aMs t i n U t s e T ti u c r i C e g a t l o V n o i t c e t e D n e g a t l o V n o i t c e t e D e g r a h c r e v O ) 4 , 3 , 2 , 1 = n (V n U C V n U C 0 2 0 . 0-V n U C V n U C 0 2 0 . 0 + V1TA 0 =o 0 6 + o t CoC ) 1 * ( V n U C 5 2 0 . 0-V n U C V n U C 5 2 0 . 0 + n e g a t l o V s i s e r e t s y H e g r a h c r e v O ) 4 , 3 , 2 , 1 = n (V n C H 3 5 . 0-8 3 . 0-3 2 . 0-V 1 n e g a t l o Vd l o h s e r h T n w o d t u h S ) 4 , 3 , 2 , 1 = n (V n D S f o e g d e g n i l l a f t c e t e D e g a t l o v y l p p u sV n D S 5 0 . 0-V n D S V n D S 5 0 . 0+V 9 n e g a t l o V e s a e l e R n w o d t u h S ) 4 , 3 , 2 , 1 = n (V n R D S f o e g d e g n i s i r t c e t e D e g a t l o v y l p p u sV n R D S0 1 . 0-V n D S3 . 0+V n R D S0 1 . 0+V 9 d l o h s e r h T n o i t i s n a r T e d o M t s e TV T S T --- -4 V 2 e g a t l o V t u p n I D D V n e e w t e b e g a t l o V y l p p u S S S V d n a V P O S D 4- -4 2V - - t n e r r u C t u p n I g n i r u D n o i t p m u s n o C t n e r r u C n o i t a r e p O I E P O V 1 . 3 = 4 V = 3 V = 2 V = 1V- -5 .25 A u3 I 1 E P O V 5 1 . 4 = 4 V = 3 V = 2 V = 1V- -4 5 .6A u3 g n i r u D n o i t p m u s n o C t n e r r u C e g r a h c s i d r e v OI N D P V 0 . 2 = 4 V = 3 V = 2 V = 1V- -- -4 .0A u3 t n e r r u C n i P 1 C VI 1 C V V 1 . 3 = 4 V = 3 V = 2 V = 1V- -- -8 8 .0A u4 t n e r r u C n i P 2 C VI 2 C V V 1 . 3 = 4 V = 3 V = 2 V = 1V3 . 0-0 3 .0A u4 t n e r r u C n i P 3 C VI 3 C V V 1 . 3 = 4 V = 3 V = 2 V = 1V3 . 0-0 3 .0A u4 t n e r r u C n i P 4 C VI 4 C V V 1 . 3 = 4 V = 3 V = 2 V = 1V3 . 0-0 3 .0A u4 e m i T y a l e D y a l e D n o i t c e t e D e g r a h c r e v O e m i T tU C , V 1 . 3 = n C V V 5 . 4V 1 . 3 = 1 C V ) 4 , 3 , 2 = n ( tU C 8 . 0xt U C tU C 2 . 1xs 2 e m i T y a l e D e s a e l e R e g r a h c r e v OtL C , V 1 . 3 = n C V V 1 . 3V 5 . 4 = 1 C V ) 4 , 3 , 2 = n ( 8 . 216 12 . 91s m2 e m i T y a l e D n w o d t u h StD S , V 2 . 3 = n C V VV 2 . 3 = 1 C V1 D S V 2 . 0 - ) 4 , 3 , 2 = n ( tD S 8 . 0xt D S tD S 2 . 1xs 0 1 y a l e D t e s e R r e m i T e g r a h c r e v O e m i T tR T 26 0 1s m2 y a l e D n o i t c e t e D e g r a h c r e v O e d o M n e t r o h S y a l e D n i e m i Tt T U C tU C - . 0 X 8 2 1 / 1 x 8 tU C 8 2 1 / 1xt U C 2 . 1 X 8 2 1 / 1 xsm2 e d o M t s e T o t e m i T n o i t i s n a r Tt T S T --- -0 4s m- - *1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in production.

13uP8208P/Q-DS-F0100, Mar. 2018 www.upi-semi.com r e t e m a r aPl o b m ySs n o i t i d n o C t s eTn iMp yTx aMs t i n U t s e T ti u c r i C e g a t l o V t u p t u OO C e g a t l o V e v i r D n i P O C V 1 H O

3 C V - 2 C V r o 2 C V - 1 C V

V = S S V - 4 C V r o 4 C V - 3 C V r o, U C IO A m 0 = 47 .44 . 5 V V 2 H O V = S S V - 4 C V r o 4 C V - 3 C V r o, U C IO A m 1 - = V 1 H O5 . 0-V 1 H O1 . 0-- -6 V L O , V 5 1 . 4 = 4 C V = 3 C V = 2 C V = 1 C V IO A u 0 5 = --1 .05 .07 r o t a l u g e R e g a t l o V e g a t l o V t u p t u O RVV T U O I , V 5 2 o t 1 . 5 = D D VT U O A u 0 1 = 0 4 9 .20 .36 0 . 3 4 3 2 .33 .36 6 3 . 3 t n e r r u C t u p t u O RVI T U O V 5 2 o t 1 . 5 = D DV- -- -2 A m8

14 uP8208P/Q-DS-F0100, Mar. 2018 www.upi-semi.com 1.15 2.3 3.45 4.6 5.75 - 4 0 - 3 0 - 2 0 - 1 0 0 1 02 03 04 05 06 07 08 0 IOPE2 IOPE3 IOPE1 2.7 2.75 2.8 2.85 2.9 - 4 0 - 3 0 - 2 0 - 1 0 0 1 02 03 04 05 06 07 08 0 VSDR2 (V) VSDR4 (V) VSDR3 (V) VSDR1 (V) 2.45 2.47 2.49 2.51 2.53 2.55 - 4 0 - 3 0 - 2 0 - 1 00 1 02 03 04 05 06 07 08 09 0 VSD2 (V) VSD4 (V) VSD3 (V) VSD1 (V) 4.8 5.2 5.4 5.6 5.8 6.2 6.4 6.6 6.8 7.2 - 4 0 - 3 0 - 2 0 - 1 00 1 02 03 04 05 06 07 08 0 Sample 1 (s) 0.23 0.28 0.33 0.38 0.43 0.48 0.53 - 4 0 - 3 0 - 2 0 - 1 0 0 1 02 03 04 05 06 07 08 0 VHC2 (V) VHC4 (V) VHC3 (V) VHC1 (V) 4.475 4.48 4.485 4.49 4.495 4.5 4.505 4.51 4.515 4.52 - 4 0 - 3 0 - 2 0 - 1 00 1 02 03 04 05 06 07 08 09 0 VCU2 (V) VCU4 (V) VCU3 (V) VCU1 (V) Typical Operation Characteristics Overcharge Hysteresis Voltage Temperature (O C) (uP8208PDN8-NK) VHCn (V) Overcharge Detection Delay Time Temperature (O C) (uP8208PDN8-NK) tCU(s) Shutdown Voltage Temperature (O C) (uP8208PDN8-NK) VSDn (V) Current Consumption during Operation Temperature (O C) (uP8208PDN8-NK) IOPE (uA) Shutdown Release Voltage Temperature (O C) (uP8208PDN8-NK) VSDRn(V) Overcharge Detection Voltage Temperature (O C) (uP8208PDN8-NK) VCUn (V)

15uP8208P/Q-DS-F0100, Mar. 2018 www.upi-semi.com 0.11 0.22 0.33 0.44 0.55 0.66 0.77 0.88 - 4 0 - 3 0 - 2 0 - 1 00 1 02 03 04 05 06 07 08 0 IVC2 IVC4 IVC3 IVC1 0.1 0.2 0.3 0.4 - 4 0 - 3 0 - 2 0 - 1 0 0 1 02 03 04 05 06 07 08 0 IPDN2 IPDN3 IPDN1 Typical Operation Characteristics VC1,VC2,VC3, and VC4 Pin Current Temperature (O C) (uP8208PDN8-NK) IVC1,IVC2,IVC3,iVC4 (uA) Current Consumption during Overdischarge Temperature (O C) (uP8208PDN8-NK) IPDN (uA)

16 uP8208P/Q-DS-F0100, Mar. 2018 www.upi-semi.com Test Circuit 1. Overcharge Detection Voltage and Overcharge Hysteresis Voltage (Test Circuit 1) Set V1, V2, V3, and V4 to 3.5V. Overcharge detection voltage 1 (VCU1 ) is the V1 voltage when the CO turns to H after the voltage of V1 gradually increases. The overcharge hysteresis voltage (VHC1 ) is the difference between V1 and VCU1 when CO turns to L after the voltage of V1 gradually decreases. Overcharge detection voltage VCUn (n = 2, 3, 4) and overcharge hysteresis VHCn (n = 2, 3, 4) can be determined in the same way as when n = 1. 2. Overcharge Detection Delay Time and Overcharge Release Delay Time (Test Circuit 1) Set V1, V2, V3, and V4 to 3.5V, and within 10us, V1 is increased up to 5.0V. The overcharge detection delay time (tCU ) is the duration from when V1 reaches 5.0V until when CO turns to H. After that, V1 is lowered down to 3.5V within 10 us. The overcharge release delay time (tCL) is the duration from when V1 reaches 3.5V until when CO turns to L. 3. Overcharge Timer Reset Delay Time (tTR ) (Test Circuit 1) Set V1, V2, V3, and V4 to 3.5V. V1 is driven up to 5.0V and this is defined as the first rise. Then V1 is lowered down to 3.5V again and instantly resumes to 5.0V. This rise is defined as the second rise. When the duration between the V1 fall and the second rise is short enough, CO turns to H after the tCU following the first rise; when the duration between the V1 fall and the second rise is long enough, CO turns to H after the tCU following the second rise. The overcharge timer reset delay time (tTR ) is the duration from V1 fall to the second rise. For detailed illustration, please refer to the Timing Chart of Overcharge Timer Reset on page 10. 4. Transition Time to Test Mode (Test Circuit 2) Setting V1, V2, V3 and V4 to 3.5V and V5 to 0V. Bring V5 up to 4V(max) and halt for a quick pause and then drop back to 0V again. The transition time tTST (40ms max.) is defined as the duration between the rise and fall of V5. When the duration between the rise and fall of V5 is shorter than tTST . it will result in overcharge detection protection after going through tCU ; however, when the overcharge detection time is made longer than tTST , overcharge detection protection will occur within duration much shorter than tCU which is typically one sixty-fourth of tCU . For more detailed illustration, please refer to the Timing Chart of Test Mode on page 9. 5. Operation Current Consumption and Overdischarge Current Consumption (Test Circuit 3) The current consumption during operation (IOPE ) is the total of the currents that flow in the VDD pin and VC1 pin when V1, V2, V3, and V4 are set to 3.1V. The current consumption during over discharge (IPDN ) is the total of the currents that flow in the VDD pin and VC1 pin when V1, V2, V3, and V4 are set to 2.0V. 6. VC1, VC2, VC3, VC4 Current Consumption (Test Circuit 4) When V1, V2, V3, and V4 are set to 3.1V, the current of VC1 pin is IVC1 ; the current of VC2 pin is IVC2 ; the current of the VC3 pin is IVC3 ; and the current of the VC4 pin current is IVC4 . 7. CO Function Test (Test Circuit 5, Test Circuit 6, Test Circuit 7) Setting V1 or V2 or V3 or V4=VCU , the voltage of the rest of the cells is 3.5V. After tCU the CO will become High, the voltage of VOH1 is 4.7V (Typ). When CO is High, add 1mA load between CO and GND. The voltage of VOH2 is VOH1 - 0.1V (Typ). Setting V1=V2=V3=V4=4.15V, add 50uA current source between CO and GND. The voltage of VOL is 0.1V (Typ). 8. Voltage Regulation (Test Circuit 8, Test Circuit 9, Test Circuit 10) When V1+V2+V3+V4 voltage is 5.1V to 25V and each cell voltage is above VSD +0.3V(Typ.), the voltage of VOUT is 3V(uP8208Q) or 3.3V(uP8208P). The maximum capability of VOUT is 2mA. When V1 and V2 and V3 and V4 are supplied, any cell voltage drops below VSD , after tSD the VOUT will be turned off. At shutdown mode, when all cell voltage reaches VSD +0.3V (Typ), the Voltage Regulation will be turned on immediately.

17uP8208P/Q-DS-F0100, Mar. 2018 www.upi-semi.com Test Circuit Test Circuit 3 uP8208P/Q VDD VC1 VC2 VC4 VC3 CO VSS VOUTA Test Circuit 4 A A A A uP8208P/Q VDD VC1 VC2 VC4 VC3 CO VSS VOUT Test Circuit 5 V uP8208P/Q VDD VC1 VC2 VC4 VC3 CO VSS VOUT Test Circuit 6 V uP8208P/Q VDD VC1 VC2 VC4 VC3 CO VSS VOUT A Test Circuit 1 V V1 V V V V uP8208P/Q VDD VC1 VC2 VC4 VC3 CO VSS VOUT Test Circuit 2 V V1 V uP8208P/Q VDD VC1 VC2 VC4 VC3 CO VSS VOUT

18 uP8208P/Q-DS-F0100, Mar. 2018 www.upi-semi.com Test Circuit Test Circuit 7 V uP8208P/Q VDD VC1 VC2 VC4 VC3 CO VSS VOUT A Test Circuit 8 V uP8208P/Q VDD VC1 VC2 VC4 VC3 CO VSS VOUT A Test Circuit 9 V V1 V V V V uP8208P/Q VDD VC1 VC2 VC4 VC3 CO VSS VOUT Test Circuit 10 V V1 V uP8208P/Q VDD VC1 VC2 VC4 VC3 CO VSS VOUT

19uP8208P/Q-DS-F0100, Mar. 2018 www.upi-semi.com

Application Information

Recommended Footprint: CAUTION: The above information is for reference only. It may be adjusted based on the manufacturing parameters provided by PCB and assembly venders. 2.41.0 0.45 1.8 0.3 0.5 Tolerance: ±0.03 Unit: mm

20 uP8208P/Q-DS-F0100, Mar. 2018 www.upi-semi.com

Package Information

1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm. WDFN2x2 - 8L Package 0.18 - 0.300.50 BSC 1.90 - 2.10 1.90 - 2.10 0.50 - 0.80 0.00 - 0.050.20 REF 0.70 - 0.80

21uP8208P/Q-DS-F0100, Mar. 2018 www.upi-semi.com Important Notice uPI and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. uPI products are sold subject to the taerms and conditions of sale supplied at the time of order acknowledgment. However, no responsibility is assumed by uPI or its subsidiaries for its use or application of any product or circuit; nor for any infringements of patents or other rights of third parties which may result from its use or application, including but not limited to any consequential or incidental damages. No uPI components are designed, intended or authorized for use in military, aerospace, automotive applications nor in systems for surgical implantation or life-sustaining. No license is granted by implication or otherwise under any patent or patent rights of uPI or its subsidiaries. COPYRIGHT ( C ) 2015, UPI SEMICONDUCTOR CORP . uPI Semiconductor Corp. Headquarter 9F.,No.5, Taiyuan 1st St. Zhubei City, Hsinchu Taiwan, R.O.C. uPI Semiconductor Corp. Sales Branch Office 12F-5, No. 408, Ruiguang Rd. Neihu District, Taipei Taiwan, R.O.C.