UP8207 UPI | Alldatasheet
Document overview
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Technical content
1uP8207-DS-F0001, May 2018 www.upi-semi.com General Description Features The uP8207 series is used for secondary protection of lithium-ion rechargeable batteries, and incorporates a high- accuracy voltage detection circuit and a delay circuit. Short circuits between cells accommodate series connection of two to three cells. Battery Protection IC for 2-Serial/3-Serial-Cell Pack (Second Protection) Note: (1) Please check the sample/production availability with uPI representatives. (2) uPI products are compatible with the current IPC/JEDEC J-STD-020 requirement. They are halogen-free, RoHS compliant and 100% matte tin (Sn) plating that are suitable for use in SnPb or Pb-free soldering processes. High Accuracy Voltage Detection Circuit for Each Cell Overcharge Detection Voltage n (n = 1 to 3) 4.20V to 4.70V (in 50mV steps) Accuracy: 20mV (+25O C) Accuracy: 30mV (0O C to +60O C) Overcharge Hysteresis Voltage n (n = 1 to 3) Delay Time for Overcharge Detection Can Be Set by An Internal Circuit (No External Capacitors Required) High Withstand Voltage Devices: Absolute Maximum Rating 26V Wide Operating Voltage Range: 3.6V to 24V Wide Operating Temperature Range: -40O C to +85O C Low Current Consumption At 3.8V for Each Cell: 2.0uA max. (+25O C) At 2.0V for Each Cell: 0.3uA max. (+25O C) CO Pull Up Voltage : 4.7V Available in TSOT23-6L Package RoHS Compliant and Halogen Free
Applications
Lithium-Ion Rechargeable Battery Packs (for Secondary Protection) Notebook Computers Portable Instrumentation Portable Equipment
Ordering Information
r e b m u N r e d rOe g a k c aPg n i k r a Mp o T Y X - 6 T M P 7 0 2 8 PuL 6 - 3 2 T O S T Y X P 2 7 N V , e g a t l o V n o i t c e t e D e g r a h c r e v O: X U C . V 0 7 . 4 =M :Yt , e m i T y a l e Dn o i t c e t e D e g r a h c r e v OU C s 8 =D , s 6 =C , s 4 = B , s 2 = A Pin Configuration TSOT23-6L VDD VC1 VC2 VC3 VSS CO Marking Information N72PXY XXXXXX Line1 : Product Code Line2 : Date Code Number
2 uP8207-DS-F0001, May 2018 www.upi-semi.com Typical Application Circuit Cautions: 1. The above connection example does not guarantee operation. Perform thorough evaluation using the actual application. 2. Cell Connection: To prevent incorrect output activation, the VSS pin must be connected first. Follow the connecting sequence below: Configuration of 3 serial cell: BAT3 -> BAT2 -> BAT1 Configuration of 2 serial cell: BAT2 -> BAT1 VDD R VDD C VDD VC2 VSS VC3 VC1 CO PB PB+ SC Protector BAT1 BAT2 BAT3
3uP8207-DS-F0001, May 2018 www.upi-semi.com Functional Block Diagram Control Logic Vref2 Oscillator Overcharge Detection / Release Delay Circuit VDD VC1 VC2 VC3 VSS Vref3 Vref1 - Overcharge Detection Comparator 1 Overcharge Detection Comparator 2 - Overcharge Detection Comparator 3 VC1 Power Down Control VC2 Power Down Control VC3 Power Down Control VDD CO
4 uP8207-DS-F0001, May 2018 www.upi-semi.com Functional Pin Description . O Nn iPe m aNn o i t c n u F n i P 1D DVn i P t u p n I r e w o P e v i t i s o P 21 CV. 1 y r e t t a B f o n i P n o i t c e n n o C r e w o P e v i t i s o P 32 C V . 1 y r e t t a B f o n i P n o it c e n n o C e g a t l o V e v i t a g e N . 2 y r e t t a B f o n i P n o i t c e n n o C e g a t l o V e v i t i s o P 43 C V . 2 y r e t t a B f o n i P n o i t c e n n o C e g a t l o V e v i t a g e N . 3 y r e t t a B f o n i P n o i t c e n n o C e g a t l o V e v i t i s o P 5S S V . n i P t u p n I r e w o P e v i t a g e N . 3 y r e t t a B f o n i P n o i t c e n n o C e g a t l o V e v i t a g e N 6O C. e g r a h C r o f n i P n o i t c e n n o C e t a GT E F
FET to provide charge control and a secondary protection. Table 1. Constants for 3-serial cell External Components
- The above constants are subject to change without prior
- It has not been confirmed whether the operation is normal
application to set the constant.
- Set the same constants to R1 to R3 and to C1 to C3 and
- Set RVDD , C1 to C3, and CVDD so that the condition (RVDD )
- Set R1 to R3, C1 to C3, and CVDD so that the condition
(R1 to R3) . (C1 to C3, CVDD ) > 1x10-4is satisfied.
- Cell connections: To prevent incorrect output activation,
evaluation with the actual application circuit. Protection IC Connection Examples. Connect VDD capacitor to either VC1 or VSS. owned by a third party by products including this IC. Table 2. Constants for 2-serial cell External Components
- The above constants are subject to change without prior
- It has not been confirmed whether the operation is normal
application to set the constant.
- Set the same constants to R1 to R2 and to C1 to C2 and
- Set RVDD , C1 to C2, and CVDD so that the condition (RVDD )
- Set R1 to R2, C1 to C2, and CVDD so that the condition
(R1 to R2) . (C1 to C2, CVDD ) > 1x10-4is satisfied.
- Cell connections: To prevent incorrect output activation,
7uP8207-DS-F0001, May 2018 www.upi-semi.com Functional Description Timing Chart Overcharge Protection Battery Voltage Shorter than tCU tCU VHCn VCUn ( n = 1, 2, 3) CO Output Voltage shorter than tTR 1.95ms typ. Test Mode 1.95ms typ. 8.5V or more Battery Voltage tTST = 40ms min. VDD Pin Voltage VC1 Pin Voltage (n = 1, 2, 3) VCUn Test Mode CO Output Voltage A Sixty-fourth of tCU Pin Voltage VHCn
8 uP8207-DS-F0001, May 2018 www.upi-semi.com Functional Description Overcharge Timer Reset Battery Voltage Shorter than tCU tCU VHCn VCUn ( n = 1, 2, 3) CO Output Voltage shorter than tTR Longer than tTR Timer reset
9uP8207-DS-F0001, May 2018 www.upi-semi.com (Note 1) ESD Rating (Note 2) (Note 4) Absolute Maximum Rating Thermal Information Recommended Operation Conditions Note 1. Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. θ JA is measured in the natural convection at TA = 25oC on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 4. The device is not guaranteed to function outside its operating conditions. Package Thermal Resistance (Note 3) Power Dissipation, PD @ TA = 25oC
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Electrical Characteristics
(TA=25oC, unless otherwise specified) r e t e m a r aPl o b m ySs n o i t i d n o C t s eTn iMp yTx aMs t i n Ut s e T ti u c r i C e g a t l o V n o i t c e t e D n e g a t l o V n o i t c e t e D e g r a h c r e v O ) 3 , 2 , 1 = n ( V n U C --V n U C 0 2 0 . 0-V n U C V n U C 0 2 0 . 0 + V1TA 0 =o 0 6 + o t CoC ) 1 * ( V n U C 0 3 0 . 0-V n U C V n U C 0 3 0 . 0 + s i s e r e t s y H e g r a h c r e v O ) 3 , 2 , 1 = n ( V n C H V C H V 0 3 . 0 -=V n C H 0 5 0 . 0-V n C H V n C H 0 5 0 . 0+V 1 e g a t l o V r o t c e t e D n w o d t u h S d l o h s e r h T V D S e g d e g n i l l a f t c e t eD1 .35 .39 .3V 1 e g a t l o V t u p n I D D V n e e w t e b e g a t l o V y l p p u S S S V d n a V P O S D --6 .3- -4 2V - - t n e r r u C t u p n I g n i r u D n o i t p m u s n o C t n e r r u C n o i t a r e p O I E P O V 8 . 3 = 3 V = 2 V = 1V- -- -0 .2A u3 g n i r u D n o i t p m u s n o C t n e r r u C e g r a h c s i d r e v OI N D P V 0 . 2 = 3 V = 2 V = 1V- -- -3 .0A u3 t n e r r u C n i P 1 CVI 1 C V V 8 . 3 = 3 V = 2 V = 1V- -- -2 .1A u4 t n e r r u C n i P 2 CVI 2 C V V 8 . 3 = 3 V = 2 V = 1V3 . 0-0 3 .0A u4 t n e r r u C n i P 3 CVI 3 C V V 8 . 3 = 3 V = 2 V = 1V3 . 0-0 3 .0A u4 e g a t l o V t u p t u OO C 1 e g a t l o VN O h c POCV 1 H O IH O , A u 0 = V n L L E CV 7 . 4 = ) 3 , 2 , 1 = n ( 0 .47 .44 .5V 5 2 e g a t l o VN O h c POCV 2 H O IH O , A u 0 5 - = V n L L E CV 7 . 4 = ) 3 , 2 , 1 = n ( V 1 H O5 . 0-V 1 H O1 . 0-- -V 5 e g a t l o VN O h c NOCV L O IL O , A u 0 5 = V n L L E CV 9 . 3 = ) 3 , 2 , 1 = n ( --1 .05 .0V 6 e m i T y a l e D y a l e D n o i t c e t e D e g r a h c r e v O e m i T tU C --t U C 8 . 0xt U C tU C 2 . 1xs 1 e d o M t s e T o t e m i T n o i t i s n a rTt T S T , V 5 . 3 = 3 V = 2 V = 1 V V 5 . 8 + 1 V > D D V--- -0 4s m2 y a l e D t e s e R r e m i T e g r a h c r e v O e m i T tR T --6 5 .15 9 .15 3 .2s m1 y a l e D e s a e l e R e g r a h c r e v O e m i T tL C --6 5 .15 9 .15 3 .2s m1
11uP8207-DS-F0001, May 2018 www.upi-semi.com 4.8 5.2 5.4 5.6 5.8 6.2 6.4 6.6 6.8 7.2 - 4 0 - 3 0 - 2 0 - 1 0 0 1 02 03 04 05 06 07 08 09 0 Sample2 (s) Sample3 (s) Sample1 (s) - 4 0 - 3 0 - 2 0 - 1 00 1 02 03 04 05 06 07 08 09 0 IOPE2 IOPE3 IOPE1 0.5 1.5 - 4 0 - 3 0 - 2 0 - 1 00 1 02 03 04 05 06 07 08 09 0 IOPE2 IOPE3 IOPE1 1.56 1.66 1.76 1.86 1.96 2.06 2.16 2.26 - 4 0 - 3 0 - 2 0 - 1 0 0 1 02 03 04 05 06 07 08 09 0 Sample2 (ms) Sample3 (ms) Sample1 (ms) 0.25 0.27 0.29 0.31 0.33 0.35 - 4 0 - 3 0 - 2 0 - 1 00 1 02 03 04 05 06 07 08 09 0 VHC2 VHC3 VHC1 4.47 4.48 4.49 4.5 4.51 4.52 4.53 - 4 0 - 3 0 - 2 0 - 1 00 1 02 03 04 05 06 07 08 09 0 VCU2 VCU3 VCU1 Typical Operation Characteristics Overcharge Hysteresis Temperature (oC) uP8207PMT6-IC VHCn (V) Overcharge Detection Delay Time Temperature (oC) uP8207PMT6-IC tCU (s) Overcharge Release Delay Time Temperature (oC) uP8207PMT6-IC tCL (ms) Current Consumption during Overcharge Temperature (oC) uP8207PMT6-IC IOPE (uA) Current Consumption during Operation Temperature (oC) uP8207PMT6-IC IOPE (uA) Overcharge Detection Voltage Temperature (oC) uP8207PMT6-IC VCUn (V)
12 uP8207-DS-F0001, May 2018 www.upi-semi.com -0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 - 4 0 - 3 0 - 2 0 - 1 00 1 02 03 04 05 06 07 08 09 0 IVC2 IVC3 IVC1 0.05 0.1 0.15 0.2 0.25 0.3 - 4 0 - 3 0 - 2 0 - 1 0 0 1 02 03 04 05 06 07 08 09 0 IPDN2 IPDN3 IPDN1 Typical Operation Characteristics VCn Pin Current Temperature (oC) uP8207PMT6-IC IVC1 , IVC2 , IVC3 (uA) Current Consumption during Overdischarge Temperature (oC) uP8207PMT6-IC IPDN (uA)
13uP8207-DS-F0001, May 2018 www.upi-semi.com Test Circuit 1. Overcharge Detection Voltage, Overcharge Hysteresis Voltage (Test circuit 1)
1.1 Overcharge detection voltage n (VCUn )
Set V1 = V2 = V3 = VCU - 0.05 V. The Overcharge detection voltage 1 (VCU1 ) is the V1 voltage when the CO pin’s output changes after the voltage of V1 has been gradually increased. Overcharge detection voltage VCUn (n = 2, 3) can be determined in the same way as when n = 1.
1.2 Overcharge hysteresis voltage n (VHCn )
Set V1 = VCU + 0.05 V, V2 = V3 = 2.5 V. The overcharge hysteresis voltage 1 (VHC1 ) is the difference between V1 voltage and VCU1 when the CO pin’s output changes after the V1 voltage has been gradually decreased. Overcharge hysteresis voltage VHCn (n = 2, 3) can be determined in the same way as when n = 1. 2. CO Output Voltage (Test circuit 5, and Test circuit 6)
2.1 CO Pch ON Voltage (VOH1 and VOH2 )
As Test circuit 5, setting V1=V2=V3=4.7V. Sourcing IOH from CO pin and measuring its output voltage. VOH1 denotes 0A been sourced. VOH2 denotes 50uA been sourced.
2.2 CO Nch ON Voltage (VOL )
As Test circuit 6, setting V1=V2=V3=3.8V. Sinking 50uA into CO pin and measuring its output voltage, VOL . 3. Overcharge Detection Delay Time (tCU ) (Test circuit 1) Increase V1 up to 5.0V after setting V1=V2=V3=3.5V. The overcharge detection delay time (tCU ) is the time period until the CO pin output changes. 4. Transition Time to Test Mode (tTST ) (Test circuit 2) Setting V1, V2, V3, to 3.5V and V6 to 0 V, then V6 is increased to 8.5V and then halted for a quick pause and decreased back to 0V again. The transition time tTST (40ms max) is defined as the duration between the rise and fall of V6. When the duration between the rise and fall of V6 is shorter than tTST , it will result in overcharge detection protection after going through tCU ; however, when the overcharge detection time is made longer than tTST , overcharge detection protection will occur within duration much shorter than tCU . For detailed inllustration, please refer to the Timing Chart of Test Mode on page 7. 5. Overcharge Timer Reset Delay Time (tTR ) (Test circuit 1) Set V1, V2, and V3 to 3.5V. V1 is driven up to 5.0V and this is defined as the first rise. Then V1 is lowered down to 3.5V again, and instantly resumed to 5.0V. This rise is defined as the second rise. The overcharge timer reset delay time (tTR ) is a duration from V1 fall to the second rise. When the duration between the V1 fall and the second rise is shorter than tTR , CO turns to H after the tCU following the first rise; when the duration between the V1 fall and the second rise is longer than certain period of time, CO turns to H after the duration of tCU following the second rise. For detailed inllustration, please refer to the Timing Chart of Overcharger Timer Reset on page 8.
14 uP8207-DS-F0001, May 2018 www.upi-semi.com Test Circuit uP8207 VDD VC1 VC2 VSS VC3 CO A Test Circuit 3 uP8207 VDD VC1 VC2 VSS VC3 CO Test Circuit 4 A A A uP8207 VDD VC1 VC2 VSS VC3 CO V Test Circuit 1 Test Circuit 2 uP8207 VDD VC1 VC2 VSS VC3 CO V V3 VO HV uP8207 VDD VC1 VC2 VSS VC3 CO A IOH Test Circuit 5 V3 VO HV uP8207 VDD VC1 VC2 VSS VC3 CO A IOL Test Circuit 6
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Application Information
Recommended Footprint: CAUTION: The above information is for reference only. It may be adjusted based on the manufacturing parameters provided by PCB and assembly venders. Tolerance: ±0.10 Unit: mm 0.95 0.7 2.6 1.0 1.6 3.6
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Package Information
1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm. TSOT23 - 6L
1.90 BSC
0.00 - 0.10 0.08 - 0.25 0.30 - 0.60
0.9 MAX
0.30 - 0.51 2.80 - 3.02 2.60 - 3.00
0.95 BSC
1.50 - 1.70
17uP8207-DS-F0001, May 2018 www.upi-semi.com Important Notice uPI and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. uPI products are sold subject to the taerms and conditions of sale supplied at the time of order acknowledgment. However, no responsibility is assumed by uPI or its subsidiaries for its use or application of any product or circuit; nor for any infringements of patents or other rights of third parties which may result from its use or application, including but not limited to any consequential or incidental damages. No uPI components are designed, intended or authorized for use in military, aerospace, automotive applications nor in systems for surgical implantation or life-sustaining. No license is granted by implication or otherwise under any patent or patent rights of uPI or its subsidiaries. COPYRIGHT ( C ) 2014, UPI SEMICONDUCTOR CORP . uPI Semiconductor Corp. Headquarter 9F.,No.5, Taiyuan 1st St. Zhubei City, Hsinchu Taiwan, R.O.C. uPI Semiconductor Corp. Sales Branch Office 12F-5, No. 408, Ruiguang Rd. Neihu District, Taipei Taiwan, R.O.C.