UP8206 UPI | Alldatasheet
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Features
S TSSOP – 8L VDD SENSE VC1 VC2 VC3 CTL CO VSS UUTDFN1.97x2.46 – 8L
2 uP8206-DS-F0001, Apr. 2018 www.upi-semi.com r e b m u N r e d rOe g a k c aPg n i k r a Mp oTe t o N Y X - 8 X D P 6 0 2 8 PuL 8 - 6 4 . 2 x 7 9 . 1 N F D T UUY X P C E e g a t l o V n o i t c e t e D e g r a h C - r e v O : X e d o C V 0 6 . 4 : G ; V 5 5 . 4 : F e m i T y a l e D n o i t c e t e D e g r a h C - r e v O : Y e d o C s 4 : 3 ; s 5 . 3 : 2 ; s 5 . 6 : 1Y X - 8 A T A 6 0 2 8 PuL 8 - P O S STY X A 6 0 2 8
Ordering Information
Note: (1) Please check the sample/production availability with uPI representatives. (2) uPI products are compatible with the current IPC/JEDEC J-STD-020 requirement. They are halogen-free, RoHS compliant and 100% matte tin (Sn) plating that are suitable for use in SnPb or Pb-free soldering processes. TSSOP - 8L UUTDFN1.97x2.46 - 8L Line1: Product Code -ECP: Product Code -XY: Version Code Line2: Lot Number Line1: Product Code -8206A: Product Code -XY: Version Code Line2: Lot Number 8206AXY aaa bbb ECPXY aaa bbb Marking Rule
3uP8206-DS-F0001, Apr. 2018 www.upi-semi.com . o Nn iPe m a Nn iPn o i t c n u F n i P 1D D V . n i P t u p n I r e w o P e v i t i s o P 2E S N E S . 1 y r e t t a B f o n i P n o i t c e n n o C e g a t l o V e v i t i s o P 31 C V . 1 y r e t t a B f o n i P n o i t c e n n o C e g a t l o V e v i t a g e N . 2 y r e t t a B f o n i P n o i t c e n n o C e g a t l o V e v i t i s o P 42 C V . 2 y r e t t a B f o n i P n o i t c e n n o C e g a t l o V e v i t a g e N . 3 y r e t t a B f o n i P n o i t c e n n o C e g a t l o V e v i t i s o P 53 C V . 3 y r e t t a B f o n i P n o i t c e n n o C e g a t l o V e v i t a g e N . 4 y r e t t a B f o n i P n o i t c e n n o C e g a t l o V e v i t i s o P 6S S V . n i P t u p n I r e w o P e v i t a g e N . 4 y r e t t a B f o n i P n o i t c e n n o C e g a t l o V e v i t a g e N 7L T C . n i P l o r t n o C t u p t u OO C 8O C . e g r a h C r o f n i P n o i t c e n n o C e t a GT E F Functional Pin Description
4 uP8206-DS-F0001, Apr. 2018 www.upi-semi.com Functional Block Diagram Oscillator Overcharge detection/release delay circuit Control Logic Overcharge detection comparator 1 Reference voltage VDD SENSE VC1 VC2 VC3 VSS CTL CO VDD Overcharge detection comparator 2 Reference voltage Overcharge detection comparator 3 Reference voltage Overcharge detection comparator 4 Reference voltage
5uP8206-DS-F0001, Apr. 2018 www.upi-semi.com VDD R VDD C VDD SENSE VC2 VSS VC3 VC1 BAT1 BAT2 BAT3 BAT4 CTL CO EB EB+ PTC C CTL SC Protector Example of Application Circuit Cautions 1. The above connection example will not guarantee successful operation. Perform thorough evaluation using the actual application. 2. A pull-down resistor is included in the CTL pin. To perform overheat protection via the PTC in the uP8206A/P Series, connect the PTC before connecting batteries. 3. When the power fluctuation is large, connect the power supply of the PTC to the VDD pin of the uP8206A/P Series. 4. Cell connections: To prevent incorrect output activation, the VSS pin must be connected first. Connect sequences must be used as following: 4-series cell configuration BAT4 J BAT3 J BAT2 J BAT1 3-series cell configuration BAT3 J BAT2 J BAT1 2-series cell configuration BAT2 J BAT1 1. Overheat Protection Via PTC
6 uP8206-DS-F0001, Apr. 2018 www.upi-semi.com (1) Test Condition 1, Test Circuit 1 Set V1, V2, V3, and V4 to 3.5V. Overcharge detection voltage 1 (VCU1 ) is the V1 voltage when CO is H after the voltage of V1 has been gradually increased. The overcharge hysteresis voltage (VHC1 ) is the difference between V1 and VCU1 when CO is L after the voltage of V1 has been gradually decreased. Overcharge detection voltage VCUn (n = 2 to 4) and overcharge hysteresis VHCn (n = 2 to 4) can be determined in the same way as when n = 1. (2) Test Condition 2, Test Circuit 1 Set V1, V2, V3, and V4 to 3.5V and in a moment of time (within 10us) increase V1 up to 5.0V. The overcharge detection delay time (tCU ) is the period from when V1 reached 5.0V to when CO becomes H . After that, in a moment of time (within 10us) decrease V1 down to 3.5V. The overcharge release delay time (tCL ) is the period from when V1 has reached 3.5V to when CO becomes L. (3) Test Condition 3, Test Circuit 1 Set V1, V2, V3, and V4 to 3.5V and in a moment of time (within 10us) increase V1 up to 5.0V. This is defined as the first rise. Within tCU 20 ms after the first rise, in a moment of time (within 10us) decrease V1 down to 3.5V and then in a moment of time (within 10us) restore up to 5.0V. This is defined as the second rise. When the period from when V1 was fallen to the second rise is short, CO becomes H after tCU has elapsed since the first rise. If the period from when V1 falls to the second rise is gradually made longer, CO becomes H when tCU has elapsed since the second rise. The overcharge timer reset delay time (tTR ) is the period from V1 fall till the second rise at that time. VDD CO VC3 VC1 VSS SENSE uP8206 CTL VC2 V Test Circuit 1 Test Circuit (4) Test Condition 4, Test Circuit 2 In the uP8206A/P Series, set V1, V2, V3, and V4 to 3.5V and V5 to 14V. The CTL pin response time (tCTL ) is the period from when V5 reaches 0 V after V5 is in a moment of time (within 10us) decreased down to 0V to when CO becomes H . (5) Test Condition 6, Test Circuit 2 Set V1, V2, V3, and V4 to 3.5V and V5 to 0V. The CTL input H voltage (VCTLH ) is the maximum voltage of V5 when CO is L after V5 has been gradually increased. Next, set V5 to 14V. The CTL input L voltage (VCTLL ) is the minimum voltage of V5 when CO is H after V5 has been gradually decreased. VDD CO VC3 VC1 VSS SENSE uP8206 CTL VC2 V Test Circuit 2 (6) Test Condition 5, Test Circuit 3 After setting V1, V2, V3, and V4 to 3.5V and V5 to 0V, in a moment of time (within 10us) increase V5 up to 8.5V and decrease V5 again down to 0V. When the period from when V5 was raised to when it has fallen is short, if an overcharge detection operation is performed subsequently, the overcharge detection time is tCU . However, when the period from when V5 is raised to when it is fallen is gradually made longer, the overcharge detection time during the subsequent overcharge detection operation is shorter than tCU . The transition time to test mode (tTST ) is the period from when V5 was raised to when it has fallen at that time. VDD CO VC3 VC1 VSS SENSE uP8206 CTL VC2 V Test Circuit 3
7uP8206-DS-F0001, Apr. 2018 www.upi-semi.com Test Circuit (7) Test Condition 7, Test Circuit 4 The current consumption during operation (IOPE ) is the total of the currents that flow in the VDD pin and SENSE pin when V1, V2, V3, and V4 are set to 3.5V. The current consumption during over discharge (IOPED ) is the total of the currents that flow in the VDD pin and SENSE pin when V1, V2, V3, and V4 are set to 2.3V. VDD CO VC3 VC1 VSS SENSE uP8206 CTL VC2 A Test Circuit 4 (8) Test Condition 8, Test Circuit 5 The SENSE pin current (ISENSE ) is I1, the VC1 pin current (IVC1 ) is I2, the VC2 pin current (IVC2 ) is I3, the VC3 pin current (IVC3 ) is I4, and the CTL pin H current (ICTLH ) is I5 when V1, V2, V3, and V4 are set to 3.5V, and V5 to 14V. The CTL pin L current (ICTLL ) is I5 when V1, V2, V3, and V4 are set to 3.5V and V5 to 0V. VDD CO VC3 VC1 VSS SENSE uP8206 CTL VC2 A A A A A I3 I4 Test Circuit 5
time (tCL ) or longer, CO becomes L. VCU has been exceeded, counting tCU resumes. Table 1. uP8206 Control via CTL Pin pin voltage -2.9V (Typ.), does not have the hysteresis.
- Since the CTL pin implements high resistance of 8
9uP8206-DS-F0001, Apr. 2018 www.upi-semi.com Functional Description Test Mode In the uP8206 Series, the overcharge detection delay time (tCU ) can be shortened by entering the test mode. The test mode can be set by retaining the VDD pin voltage 8.5V or higher than the SENSE pin voltage for at least 80 ms (V1 = V2 = V3 = V4 = 3.5V, TA = 25O C). The status is retained by the internal latch and the test mode is retained even if the VDD pin voltage is decreased to the same voltage as that of the SENSE pin. When CO becomes “H” and when the delay time has elapsed after overcharge detection, the latch for retaining the test mode is reset and the uP8206 Series exits from the test mode. tCL 8.5V or more VDD , VSENSE Battery Voltage tTST = 80ms max VHCn VDD Pin Voltage SENSE Pin Voltage n = 1 to 4 VCUn Test Mode CO Pin *1. During normal mode, tCU = 6.5s (Typ). In the product tCU = 50ms(Typ.) During normal mode, tCU = 3.5s (Typ). In the product tCU = 28ms(Typ.) During normal mode, tCU = 4.0s(Typ.). In the product tCU = 32ms(Typ.) Caution 1. Set the test mode when no batteries are overcharged. 2. The overcharge release delay time (tCL ) is not shortened in the test mode. 3. The overcharge timer resets delay time (tTR ) is not shortened in the test mode. Timing Charts 1. Overcharge Detection Operation \ \ Battery Voltage CTL Pin tCL tTR or longer tCU or shorter tCU tTR or shorter VHCn VCUn ( n = 1 to 4) CO Pin 2. Overcharge Timer Reset Operation CO Pin Battery Voltage tCU tTR tCU or shorter tTR or longer tTR or shorter tTR or shorter VHCn Timer reset VCUn ( n = 1 to 4)
Table 2. Constants for 4-Serial cell External Components
- The above constants are subject to change without prior
- It has not been confirmed whether the operation is normal
application to set the constant.
- Set the same constants to R1 to R4 and to C1 to C4 and
- Set RVDD , C1 to C4, and CVDD so that the condition (RVDD )
- Set R1 to R4, C1 to C4, and CVDD so that the condition
(R1 to R4) . (C1 to C4, CVDD ) > 1x10-4is satisfied.
- In the uP8206A/P Series, normally input H to the
external input, and input L when setting CO to H .
- Cell connections: To prevent incorrect output activation,
Table 3. Constants for 3-serial cell External Components
- The above constants are subject to change without prior
- It has not been confirmed whether the operation is normal
application to set the constant.
- Set the same constants to R1 to R3 and to C1 to C3 and
- Set RVDD , C1 to C3, and CVDD so that the condition (RVDD )
- Set R1 to R3, C1 to C3, and CVDD so that the condition
(R1 to R3) . (C1 to C3, CVDD ) > 1x10-4is satisfied.
- In the uP8206A/P Series, normally input H to the
external input, and input L when setting CO to H .
- Cell connections: To prevent incorrect output activation,
Table 4. Constants for 2-serial cell External Components
- The above constants are subject to change without prior
- It has not been confirmed whether the operation is normal
application to set the constant.
- Set the same constants to R1 to R2 and to C1 to C2 and
- Set RVDD , C1 to C2, and CVDD so that the condition (RVDD )
- Set R1 to R2, C1 to C2, and CVDD so that the condition
(R1 to R2) . (C1 to C2, CVDD ) > 1x10-4is satisfied.
- In the uP8206A/P Series, normally input H to the
external input, and input L when setting CO to H .
- Cell connections: To prevent incorrect output activation,
Do not connect batteries charged with VCU + VHC or more. evaluation with the actual application circuit. Protection IC Connection Example”. by a third party by products including this IC.
12 uP8206-DS-F0001, Apr. 2018 www.upi-semi.com Note 1. Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. θ JA is measured in the natural convection at TA = 25O C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 4. The device is not guaranteed to function outside its operating conditions. Package Thermal Resistance (Note 3) Power Dissipation, PD @ TA = 25O C (Note 4) Absolute Maximum Rating Thermal Information Recommended Operation Conditions (Note 1) ESD Rating (Note 2)
13uP8206-DS-F0001, Apr. 2018 www.upi-semi.com
Electrical Characteristics
r e t e m a r aPl o b m ySs n o i t i d n o C t s eTn iMp yTx aMs t i n U t s e T n o i t d n o C t s e T t iu c r i C E G A T L O VN O I T C E T E D n o i t c e t e D e g r a h c r e v O ) 4 , 3 , 2 , 1 = n ( e g a t l o VV n U C , e l b a t s u j d a , V 0 8 . 4 o t V 0 2 . 4 TA 5 2 =oC V n U C- 5 2 0 . 0V n U C V n U C+ 5 2 0 . 0V1 1 , e l b a t s u j d a , V 0 8 . 4 o t V 0 2 . 4 TA 5 - =O 5 5 o t CO C 1 * V n U C- 0 3 0 . 0V n U C V n U C+ 0 3 0 . 0V1 1 s i s e r e t s y H e g r a h c r e v O ) 4 , 3 , 2 , 1 = n ( e g a t l o VV n C H V n C H- 5 1 . 08 3 . 0 -V n C H+ 5 1 . 0V1 1 n o i t c e t e D e g r a h c r e v O e g a t l o V V U C Y A - 8 X X X 6 0 2 8 Pu5 7 2 .40 3 .45 2 3 . 4 V Y B - 8 X X X 6 0 2 8 Pu5 2 3 .45 3 .45 7 3 .41 1 Y C - 8 X X X 6 0 2 8 Pu5 7 3 .40 4 .45 2 4 .41 1 Y D - 8 X X X 6 0 2 8 Pu5 2 4 .45 4 .45 7 4 .41 1 Y E -8 X X X 6 0 2 8 Pu5 7 4 .40 5 .45 2 5 .41 1 Y F - 8 X X X 6 0 2 8 Pu5 2 5 .45 5 .45 7 5 .41 1 Y G - 8 X X X 6 0 2 8 Pu5 7 5 .40 6 .45 2 6 .41 1 s i s e r e t s y H e g r a h c r e v O e g a t l o V V C H 3 5 . 0-8 3 . 0-3 2 . 0-V 11 E G A T L O V T U P N I e g a t l o V y l p p u S d n a D D V n e e w t e b S S V V P O S D 4- -4 2V - -- - e g a t l o V " H " t u p n I L TCV H L T C V D D 5 9 . 0--- -V 6 2 e g a t l o V " L " t u p n I L TCV L L T C --- - V D D 4 . 0V6 2 T N E R R U CT U P N I n o i t p m u s n o C t n e r r u C n o i t a r e p Og n i r u d I E P O V 5 . 3 = 4 V = 3 V = 2 V = 1V- -5 .20 .5A u74 n o i t p m u s n o C t n e r r u C e g r a h c s i D r e v Og n i r u d I D E P O V 3 . 2 = 4 V = 3 V = 2 V = 1V- -0 .20 .4A u74 t n e r r u C n i PE S N ESI E S N E S V 5 . 3 = 4 V = 3 V = 2 V = 1V- -5 .12 .3A u85 t n e r r u C n i P 1 CVI 1 C V V 5 . 3 = 4 V = 3 V = 2 V = 1V3 . 0-0 3 .0A u85 t n e r r u C n i P 2 CVI 2 C V V 5 . 3 = 4 V = 3 V = 2 V = 1V3 . 0-0 3 .0A u85 t n e r r u C n i P 3 CVI 3 C V V 5 . 3 = 4 V = 3 V = 2 V = 1V3 . 0-0 3 .0A u85 t n e r r u C " H " n i P L TCI H L T C , V 5 . 3 = 4 V = 3 V = 2 V = 1 V V L T CV =D D 1 .15 .18 .1A u85 t n e r r u C " L " n i P L TCI L L T C , V 5 . 3 = 4 V = 3 V = 2 V = 1 V V L T C V 0 = 5 1 . 0-- -- -A u85 (TA = 25oC, unless otherwise specified)
14 uP8206-DS-F0001, Apr. 2018 www.upi-semi.com r e t e m a r aPl o b m ySs n o i t i d n o C t s eTn iMp yTx a M st i n U t n e r r u C t u p t u O t n e r r u C k n i S n i POCI L O C 1 C V - E S N E S , E S N E S =D D V , V 1 . 0 =O C V 5 . 3 = S S V - 3 C V = 3 C V - 2 C V = 2 C V - 1 C V =5- -- -A u t n e r r u C e c r u o S n i POCI H O C r o 3 C V - 2 C V r o 2 C V - 1 C V r o 1 C V - E S N E S V = S S V - 3 C VU CV ,O C V =H O CV 1 - 1- -- -A m e g a t l o V t u p t u O e g a t l o V e v i r D n i POCV O C
3 C V - 2 C V r o 2 C V - 1 C V r o 1 C V - E S N E S
V = S S V - 3 C V r oU C I , V 4 1 =D D V , H O A m 0 = 679 V V 0 = L T C , V 3 . 4 =D DV5 .10 .2- - (TA = 25oC, unless otherwise specified) *1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in production.
15uP8206-DS-F0001, Apr. 2018 www.upi-semi.com r e t e m a r aPl o b m ySs n o i t i d n o C t s eTn iMp yTx aMs t i n U t s e T n o i t d n o C t s e T t iu c r i C E G A T L O VN O I T C E T E D n o i t c e t e D e g r a h c r e v O ) 4 , 3 , 2 , 1 = n ( e g a t l o VV n U C , e l b a t s u j d a , V 0 8 . 4 o t V 0 2 . 4 TA 5 2 =oC V n U C- 5 4 0 . 0V n U C V n U C+ 5 4 0 . 0V1 1 s i s e r e t s y H e g r a h c r e v O ) 4 , 3 , 2 , 1 = n ( e g a t l o VV n C H V n C H- 9 1 . 08 3 . 0 -V n C H+ 9 1 . 0V1 1 n o i t c e t e D e g r a h c r e v O e g a t l o V V U C Y A - 8 X X X 6 0 2 8 Pu5 5 2 .40 3 .45 4 3 . 4 V Y B - 8 X X X 6 0 2 8 Pu5 0 3 .45 3 .45 9 3 .41 1 Y C - 8 X X X 6 0 2 8 Pu5 5 3 .40 4 .45 4 4 .41 1 Y D - 8 X X X 6 0 2 8 Pu5 0 4 .45 4 .45 9 4 .41 1 Y E -8 X X X 6 0 2 8 Pu5 5 4 .40 5 .45 4 5 .41 1 Y F - 8 X X X 6 0 2 8 Pu5 0 5 .45 5 .45 9 5 .41 1 Y G - 8 X X X 6 0 2 8 Pu5 5 5 .40 6 .45 4 6 .41 1 s i s e r e t s y H e g r a h c r e v O e g a t l o V V C H 7 5 . 0-8 3 . 0-9 1 . 0-V 11 E G A T L O V T U P N I e g a t l o V y l p p u S d n a D D V n e e w t e b S S V V P O S D 4- -4 2V - -- - e g a t l o V " H " t u p n I L TCV H L T C V D D 5 9 . 0--- -V 6 2 e g a t l o V " L " t u p n I L TCV L L T C --- - V D D 4 . 0V6 2 T N E R R U CT U P N I n o i t p m u s n o C t n e r r u C n o i t a r e p Og n i r u d I E P O V 5 . 3 = 4 V = 3 V = 2 V = 1V- -0 5 .20 5 .5A u74 n o i t p m u s n o C t n e r r u C e g r a h c s i D r e v Og n i r u d I D E P O V 3 . 2 = 4 V = 3 V = 2 V = 1V- -0 0 .20 1 .4A u74 t n e r r u C n i PE S N ESI E S N E S V 5 . 3 = 4 V = 3 V = 2 V = 1V- -0 5 .14 7 .3A u85 t n e r r u C n i P 1 CVI 1 C V V 5 . 3 = 4 V = 3 V = 2 V = 1V2 4 . 0-0 2 4 .0A u85 t n e r r u C n i P 2 CVI 2 C V V 5 . 3 = 4 V = 3 V = 2 V = 1V2 4 . 0-0 2 4 .0A u85 t n e r r u C n i P 3 CVI 3 C V V 5 . 3 = 4 V = 3 V = 2 V = 1V2 4 . 0-0 2 4 .0A u85 t n e r r u C " H " n i P L TCI H L T C , V 5 . 3 = 4 V = 3 V = 2 V = 1 V V L T CV =D D 0 0 .10 5 .10 9 .1A u85 t n e r r u C " L " n i P L TCI L L T C , V 5 . 3 = 4 V = 3 V = 2 V = 1 V V L T C V 0 = 8 1 . 0-- -- -A u85 TA = -40oC to 85oC
16 uP8206-DS-F0001, Apr. 2018 www.upi-semi.com r e t e m a r aPl o b m ySs n o i t i d n o C t s eTn iMp yTx a M st i n U t n e r r u C t u p t u O t n e r r u C k n i S n i POCI L O C 1 C V - E S N E S , E S N E S =D D V , V 1 . 0 =O C V 5 . 3 = S S V - 3 C V = 3 C V - 2 C V = 2 C V - 1 C V =5 .5- -- -A u t n e r r u C e c r u o S n i POCI H O C r o 3 C V - 2 C V r o 2 C V - 1 C V r o 1 C V - E S N E S V = S S V - 3 C VU CV ,O C V =H O CV 1 - 1 .1- -- -A m e g a t l o V t u p t u O e g a t l o V e v i r D n i POCV O C r o 3 C V - 2 C V r o 2 C V - 1 C V r o 1 C V - E S N E S V = S S V - 3 C VU C I , V 4 1 =D D V , H O A m 0 = 4 9 .574 0 . 9 V V 0 = L T C , V 3 . 4 =D DV4 4 .12 - - TA = -40oC to 85oC *1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in production.
17uP8206-DS-F0001, Apr. 2018 www.upi-semi.com Detection Delay Time (1) uP8206PDX8-X1, uP8206ATA8-X1 (TA = 25oC, unless otherwise specified) r e t e m a r aPl o b m ySs n o i t i d n o C t s eTn iMp yTx aMs t i n U t s e T n o i t i d n o C t s e T t iu c r i C e m i T y a l e D n o i t c e t e D e g r a h c r e v O e m i T y a l e DtU C 2 .55 .68 .7s 2 1 r e m i T e g r a h c r e v O e m i T y a l e D t e s e RtR T 6 9 .34 3 .65 1 . 01s m3 1 e s a e l e R e g r a h c r e v O e m i T y a l e DtL C 5 6 . 048 7 . 054 9 . 06s m2 1 e s n o p s e R n i P L T C e m i T t L T C --- -5 .2s m4 2 t s e T o t e m i T n o i t i s n a r T e d o M t T S T , V 5 . 3 = 4 V =3 V = 2 V = 1 V V D D V = >E S N E SV 5 . 8 + --- -0 8s m5 3 (2) uP8206PDX8-X2, uP8206ATA8-X2 r e t e m a r aPl o b m ySs n o i t i d n o C t s eTn iMp yTx aMs t i n U t s e T n o i t i d n o C t s e T t iu c r i C e m i T y a l e D n o i t c e t e D e g r a h c r e v O e m i T y a l e Dt U C 8 .25 .32 .4s 2 1 r e m i T e g r a h c r e v O e m i T y a l e D t e s e RtR T 6 9 .34 3 .65 1 . 01s m3 1 e s a e l e R e g r a h c r e v O e m i T y a l e Dt L C 7 3 .11 7 .15 0 .2s m2 1 e s n o p s e R n i P L T C e m i T t L T C --- -5 .2s m4 2 t s e T o t e m i T n o i t i s n a r T e d o M t T S T , V 5 . 3 = 4 V =3 V = 2 V = 1 V V D D V = >E S N E S V 5 . 8 +--- -0 8s m5 3 (3) uP8206PDX8-X3, uP8206ATA8-X3 r e t e m a r aPl o b m ySs n o i t i d n o C t s eTn iMp yTx aMs t i n U t s e T n o i t i d n o C t s e T t iu c r i C e m i T y a l e D n o i t c e t e D e g r a h c r e v O e m i T y a l e DtU C 2 .348 .4s 2 1 r e m i T e g r a h c r e v O e m i T y a l e D t e s e RtR T 5 1 .31 9 .39 6 .4s m3 1 e s a e l e R e g r a h c r e v O e m i T y a l e DtL C 525 2 . 135 . 73s m2 1 e s n o p s e R n i P L T C e m i T t L T C --- -5 .2s m4 2 t s e T o t e m i T n o i t i s n a r T e d o M t T S T , V 5 . 3 = 4 V =3 V = 2 V = 1 V V D D V = >E S N E SV 5 . 8 + --- -0 8s m5 3
18 uP8206-DS-F0001, Apr. 2018 www.upi-semi.com Detection Delay Time (1) uP8206PDX8-X1, uP8206ATA8-X1 (TA = -40oC to 85oC) r e t e m a r aPl o b m ySs n o i t i d n o C t s eTn iMp yTx aMs t i n U t s e T n o i t i d n o C t s e T t iu c r i C e m i T y a l e D n o i t c e t e D e g r a h c r e v O e m i T y a l e DtU C 7 .35 .66 .9s 2 1 r e m i T e g r a h c r e v O e m i T y a l e D t e s e RtR T 24 3 .65 6 . 31s m3 1 e s a e l e R e g r a h c r e v O e m i T y a l e DtL C 5 8 . 638 7 . 054 3 . 56s m2 1 e s n o p s e R n i P L T C e m i T t L T C --- -3 s m4 2 t s e T o t e m i T n o i t i s n a r T e d o M t T S T --- -0 21s m5 3 (2) uP8206PDX8-X2, uP8206ATA8-X2 r e t e m a r aPl o b m ySs n o i t i d n o C t s eTn iMp yTx aMs t i n U t s e T n o i t i d n o C t s e T t iu c r i C e m i T y a l e D n o i t c e t e D e g r a h c r e v O e m i T y a l e DtU C 9 9 .15 .36 1 .5s 2 1 r e m i T e g r a h c r e v O e m i T y a l e D t e s e RtR T 24 3 .65 6 . 31s m3 1 e s a e l e R e g r a h c r e v O e m i T y a l e DtL C 4 2 .11 7 .10 2 .2s m2 1 e s n o p s e R n i P L T C e m i T t L T C --- -3s m4 2 t s e T o t e m i T n o i t i s n a r T e d o M t T S T --- -0 21s m5 3 (3) uP8206PDX8-X3, uP8206ATA8-X3 r e t e m a r aPl o b m ySs n o i t i d n o C t s eTn iMp yTx aMs t i n U t s e T n o i t i d n o C t s e T t iu c r i C e m i T y a l e D n o i t c e t e D e g r a h c r e v O e m i T y a l e DtU C 8 2 .249 8 .5s 2 1 r e m i T e g r a h c r e v O e m i T y a l e D t e s e RtR T 3 2 .11 9 .30 4 .8s m3 1 e s a e l e R e g r a h c r e v O e m i T y a l e DtL C 8 . 225 2 . 130 4s m2 1 e s n o p s e R n i P L T C e m i T t L T C --- -3s m4 2 t s e T o t e m i T n o i t i s n a r T e d o M t T S T --- -0 21s m5 3
19uP8206-DS-F0001, Apr. 2018 www.upi-semi.com -40 -20 0 20 40 60 80 100 5.5 5.75 6.25 6.5 6.75 7.25 7.5 -40 - 200 2 04 06 08 0 1 00 0.5 1.5 2.5 3.5 4.5 -40 -20 0 20 40 60 80 100 0.5 1.5 2.5 3.5 4.5 -40 -20 0 20 40 60 80 100 3.9 3.95 4.05 4.1 4.15 4.2 -40 -20 0 20 40 60 80 100 VC2 VSENSE VC3 VC1 4.2 4.25 4.3 4.35 4.4 4.45 4.5 -40 -20 0 20 40 60 80 100 VC2 VSENSE VC3 VC1 Overcharge Detection Delay Time vs. Temperature Temperature (O C) VSENSE = VC1 = VC2 = VC3 = 4.35V Overcharge Detection Delay Time (s) Overcharge Release Delay Time vs. Temperature Temperature (O C) VSENSE = VC1 = VC2 = VC3 = 4.05V Time (ms) Typical Operation Characteristics Current Consumption during Over Discharge vs. Temperature Temperature (O C) VSENSE = VC1 = VC2 = VC3 = 2.3V IOPED (uA) Current Consumption during Operation vs. Temperature Temperature (O C) VSENSE = VC1 = VC2 = VC3 = 3.5V IOPE (uA) Overcharge Release Voltage vs. Temperature Temperature (O C) VSENSE = VC1 = VC2 = VC3 = 4.05V Overcharge Release Voltage (V) Overcharge Detection Voltage vs. Temperature Temperature (O C) VSENSE = VC1 = VC2 = VC3 = 4.35V Overcharge Detection Voltage (V)
20 uP8206-DS-F0001, Apr. 2018 www.upi-semi.com 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 -40 -20 0 20 40 60 80 100 10.2 10.4 10.6 10.8 11.2 11.4 11.6 11.8 -40 -20 0 20 40 60 80 100 CTL Input “H ” Voltage CTL Input “L” Voltage Typical Operation Characteristics CTL Input Voltage vs. Temperature Temperature (O C) VSENSE = VC1 = VC2 = VC3 = 3.5V, VCTL = 0V increase and decrease Voltage (V) CTL Pin Response Time vs. Temperature Temperature (O C) VSENSE = VC1 = VC2 = VC3 = 3.5V, VCTL = 14V Time (ms)
21uP8206-DS-F0001, Apr. 2018 www.upi-semi.com
Application Information
Battery Protection Connections The following diagrams show the uP8206 package device in two to four cell configurations.
1 VDD
Figure 1. 2-Series Cell
4 VC3
Figure 2. 4-Series Cell Figure 3. 3-Series Cell
22 uP8206-DS-F0001, Apr. 2018 www.upi-semi.com
Package Information
UUTDFN1.97x2.46 - 8L Note 1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm. 0.40 - 0.50 1.87 - 2.07 0.00 - 0.050.127 REF 2.36 - 2.56 0.15 - 0.250.50 BSC Bottom View - Exposed Pad 0.15 - 0.25
23uP8206-DS-F0001, Apr. 2018 www.upi-semi.com 1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm.
0.65 TYP
4.30 - 4.50 0.05 - 0.15 0.45 - 0.75
0.22 TYP
1.20 MAX
0.80 - 1.05 2.90 - 3.10
0.127 TYP
6.40 BSC
24 uP8206-DS-F0001, Apr. 2018 www.upi-semi.com Important Notice uPI and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. uPI products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment. However, no responsibility is assumed by uPI or its subsidiaries for its use or application of any product or circuit; nor for any infringements of patents or other rights of third parties which may result from its use or application, including but not limited to any consequential or incidental damages. No uPI components are designed, intended or authorized for use in military, aerospace, automotive applications nor in systems for surgical implantation or life-sustaining. No license is granted by implication or otherwise under any patent or patent rights of uPI or its subsidiaries. COPYRIGHT ( C ) 2011, UPI SEMICONDUCTOR CORP . uPI Semiconductor Corp. Headquarter 9F.,No.5, Taiyuan 1st St. Zhubei City, Hsinchu Taiwan, R.O.C. uPI Semiconductor Corp. Sales Branch Office 12F-5, No. 408, Ruiguang Rd. Neihu District, Taipei Taiwan, R.O.C.