UP7534DSA8-XX

UP7534 UPI | Alldatasheet

Document overview

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Technical content

Features

(uP7534A) EN 4 5 OC# VOUT VOUT VOUT GND VIN VIN MSOP-8 (RA8) (uP7534B) EN# (uP7534A) EN GND 4 5 OC# VOUT VOUT VOUT GND VIN VIN PMSOP-8 (RU8) (uP7534B) EN# NC GND VIN VIN OC# VOUT VOUT EN (uP7534A) EN# (uP7534B SOP-8 (S8) uP7534A/B VOUTGND VOUT VOUT OC# VIN VIN (uP7534C) EN (uP7534D) EN# SOP-8 (SA8) uP7534C/D SOT23-5 (MA5) GND VINVOUT 1 uP7534G/H 3OC# EN(uP7534G) EN#(uP7534H) SOT23-5 (M5) GND VIN VOUTVOUT 1 uP7534B 3VIN SOT23-5 (MA5) GND VINVOUT 1 uP7534E/F 3NC EN(uP7534E) EN#(uP7534F) SOT23-5 (MA5) GND VIN VOUTOC# 1 uP7534C/D 3(uP7534C) EN (uP7534D) EN# SOT23-5 (M5) GND EN VOUTVOUT 1 uP7534A 3VIN

2 uP7534-DS-F0302, Mar. 2012 www.upi-semi.com Typical Application Circuit rebmuNredrOe gakcaPg nikraMpoTk rameR XX-8SA4357PuL 8-POSX X-A-41Sh giHevticAelbanE XX-8SB4357PuL 8-POSX X-B-41Sw oLevticAelbanE XX-8ASC4357PuL 8-POSX X-8SC4357Puh giHevticAelbanE XX-8ASD4357PuL 8-POSX X-8SD4357Puw oLevticAelbanE XX-5MA4357PuL 5-32TOSX X-A-41Sh giHevitcAelbanE XX-5MB4357PuL 5-32TOSX X-B-41Sn iPelbanEtuohtiW XX-5AMC4357PuL 5-32TOSX X-C-41Sh giHevitcAelbanE XX-5AMD4357PuL 5-32TOSX X-D-41Sw oLevticAelbanE XX-8ARA4357PuL 8-POSMX XA4357h giHevticAelbanE XX-8ARB4357PuL 8-POSMX XB4357w oLevticAelbanE XX-8URA4357PuL 8-POSMPX XA4357h giHevticAelbanE XX-8URB4357PuL 8-POSMPX XB4357w oLevticAelbanE XX-5AME4357PuL 5-32TOSX X-E-41Sh giHevticAelbanE XX-5AMF4357PuL 5-32TOSX X-F-41Sw oLevticAelbanE XX-5AMG4357PuL 5-32TOSX X-G-41Sh giHevticAelbanE XX-5AMH4357PuL 5-32TOSX X-H-41Sw oLevticAelbanE

Ordering Information

Note: uPI products are compatible with the current IPC/JEDEC J-STD-020 requirement. They are halogen-free, RoHS compliant and 100% matte tin (Sn) plating that are suitable for use in SnPb or Pb-free soldering processes. VOUT uP7534BS8 EN# VIN VIN OC# VOUT VOUT NC VIN GND ON OFF

3uP7534-DS-F0302, Mar. 2012 www.upi-semi.com emaNniPn oitcnuFniP #CO .galFtluaF 4357PuehT.hctiwsrewopehtproftuptuogalftluafniard-nepo,wol-evitcanasisihT .yaledemitgnihctilgedsm8lacipythtiwsruccotluafnehwwolnipsihtstressa TUOV .egatloVtuptuO ahtiwnipsihtssapyB.ecruoSTEFSOMlennahC-NmorftuptuoerasnipesehT .dnuorgotroticapacFu01muminim DNG .dnuorG #NE/NE .tupnIelbanE G/E/C/A4357PurofhgihevitcA.hctiwsrewopehtffo/nonrutottupnielbaneehtsisihT H/F/D/B4357Purofwolevitcadna NIV .tupnIylppuS ssapyB.tiucriclortnocotylppusdnaniarDTEFSOMlennahC-NotniptupniehtsisihT .dnuorgotroticapacFu22ahtiwnipsiht CN .detcennoCyllanretnItoN Functional Block Diagram Functional Pin Description Charge Pump Driver Thermal SenseUVLO Current Limit Deglitch VOUT OC# VIN (uP7534A/C/E/G) EN (uP7534B/D/F/H) EN# 7 7 Enable Logic GND VOUTVIN

4 uP7534-DS-F0302, Mar. 2012 www.upi-semi.com Power Switch The power switch is an N-channel MOSFET with a low on- state resistance. Configured as a high-side switch, the power switch prevents current flow from VOUT to VIN and VIN to VOUT when disabled. The power switch is controlled by a logic enable input (active high for uP7534A/C/E/G and active low for uP7534B/D/F/H) and driven by an internal charge pump circuit. When the output load exceeds the current-limit threshold or a short is present, the uP7534 asserts overcurrent protection and limits the output current to a safe level by driving the power switch into saturation mode. Charge Pump An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires little supply current. Driver The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall times of the output voltage. Chip Enable (for uP7534A/C/E/G) The EN pin receives a TTL or CMOS compatible input to enable/disable the uP7534A/C/E/G Logic low disables the power switch, charge pump, gate driver and other circuitry and reduces the supply current down to less than 1uA. Logic high restores bias to the drive and control circuits and turns the switch on. Chip Enable (for uP7534B/D/F/H) The EN# pin receives a TTL or CMOS compatible input to enable/disable the uP7534B/D/F/H. Logic high disables the power switch, charge pump, gate driver and other circuitry and reduces the supply current down to less than 1uA. Logic low restores bias to the drive and control circuits and turns the switch on. Soft Start The uP7534 features soft start function to eliminate the inrush current into downstream and voltage droop of upstream when hot-plug-in with capacitive loads. The soft start interval is 0.9ms typically. The input current to charge up the load capacitor is proportional to its capacitance. The uP7534 current limit function may be active during the plug-in of extreme large capacitive load. The fault flag is masked during the softstart interval. Over Current Limit The uP7534 continuous monitors the output current for overcurrent protection to protect the system power, the power switch, and the load from damage during output short circuit or soft start interval. When an overload or short circuit is encountered, the current-sense circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its saturation region, which switches the output into a constant-current mode and holds the current constant while varying the voltage on the load. The current limit level is typical 1A when the power switch operates in linear region and is typical 0.6A in saturation region (for uP7534A/BS8-06). The uP7534 asserts fault condition and pulls low OC# when overcurrent, overtemperature, input under voltage lockout condition is encountered. The output remains asserted until the overcurrent or overtemperature condition is removed. A 8ms deglitch circuit prevents the OC# signal from oscillation or false triggering. If an overtemperature shutdown occurs, the OC# is asserted instantaneously. Overtemperature Protection The uP7534 continuously monitor the operating temperature of the power switch for overtemperature protection. The uP7534 asserts overtemperature and turns off the power switch to prevent the device from damage if the junction temperature rises to approximately 135 OC due overcurrent or short-circuit conditions. Hysteresis is built into the thermal sense, the switch will not turns back on until the device has cooled approximately 20 degrees. The open- drain false reporting output (OC#) is asserted (active low) when an overtemperature shutdown or overcurrent occurs. If the fault condition is not removed, the switch will pulse on and off as the temperature cycles between these limits. Undervoltage Lockout A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2.2V, a control signal turns off the power switch. Output Voltage Discharge When Disabled The output voltage is discharged through an internal 100Ω resistor when the output voltage is disabled. Functional Description

5uP7534-DS-F0302, Mar. 2012 www.upi-semi.com (VIN= 5V, TA = 25OC, unless otherwise specified) (Note 1) Supply Input Voltage, VIN ESD Rating (Note 2) Package Thermal Resistance (Note 3) Power Dissipation, PD @ TA = 25°C (Note 4) retemaraPl obmySs noitidnoCtseTn iMp yTx aM stinU tupnIylppuS egatloVtupnIyppuS 7.2- -5 .5V tuokcoLegatloVrednUV OLVU VNI gnisir- -2 .25 .2V siseretsyHOLVU ΔV OLVU --5 7- -V m tnerruCnwodtuhSI DS delbasiD,TUOVnodaoloN- -1 .01A u tnerruCtnecseiuQI Q delbanE,TUOVnodaoloN- -5 20 5A u Absolute Maximum Rating Thermal Information Recommended Operation Conditions

Electrical Characteristics

6 uP7534-DS-F0302, Mar. 2012 www.upi-semi.com retemaraPl obmySs noitidnoCtseTn iMp yTx aM stinU elbanEpihC dlohserhThgiHcigoLV <V7.2 NI V5.5<4 .1- -- -V dlohserhTwoLcigoLV <V7.2 NI V5.5<- -- -4 .0V tnerruCtupnIelbanEV <V0 NE V, #NE V5.5<5 .0-- -5 .0A u )5etoN(emiTnOnruTT NO CL R,Fu1= L 01= Ω --1 - -s m )5etoN(emiTffOnruTT FFO CL R,Fu1= L 01= Ω --3 .0- -s m emiTesiRtuptuOT R CL R,Fu1= L 01= Ω 6.09 .02 .1s m emiTllaFtuptuOT F CL R,Fu1= L 01= Ω --2 .05 .0s m egrahcsiDtuptuO delbasiDnehwecnatsiseR .delbasiD- -0 01- - Ω hctiwSrewoP ecnaitseRNOTEFSOM-NR )NO(SD ,02-8ARB4357Pu,02-8ARA4357Pu VNI I,V0.5= TUO A5.0= --0 75 7 mΩV,)srehtO(D/C/B/A4357Pu NI ,V0.5= I TUO A5.0= --0 90 01 V,H/G/F/E4357Pu NI I,V0.5= TUO A5.0=- -0 010 11 tnerruCegakaeL delbasiD,DNGotdetcennocTUOV- -- -1 A u tnerruCegkaeLesreveRV TUO V,V5.5= NI V0=- -- -1 A u timiLtnerruC tnerruCtuptuOtiucriCtrohSI CS VNI TUOV,V0.5= ,DNGotdetcennoc otnidelbaneecived tiucric-trohs 60-XXXX4357Pu- -6 .09 .0 A 01-XXXX4357Pu- -0 .15 .1 51-XXXX4357Pu- -5 .13 .2 02-XXXX4357Pu- -0 .20 .3 dlohserhTpirTtnerrucrevOI PIRT_CS VNI pmartnerruc,V0.5= TUOVnos/A001< 60-XXXX4357Pu6 .00 .15 .1 A 01-XXXX4357Pu1 .18 .19 .1 51-XXXX4357Pu0 .25 .28 .3 02-XXXX4357Pu8 .23 .30 .5 )#CO(galFtluaF egatloVwoLtuptuOV LO I #CO Am5=- -- -4 .0V tnerruCetatSffOV #CO V5.5=- -- -1 A u hctilgeD#COy alednoitressa#CO5 8 5 1s m noitcetorPtnerruCrevO dlohserhTleveL-nwodtuhSn giseDyB- -5 31- - OC nwodtuhSlamrehT siseretsyH ngiseDyB- -0 2- - OC

7uP7534-DS-F0302, Mar. 2012 www.upi-semi.com Note 1. Stresses beyond those listed as the above Absolute Maximum Ratings may cause permanent damage to the device. These are for stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operation Condition section of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. θ JA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. These items are not tested in production, specified by design. OCP Event OTP Event OTP Release OC Trip Threshold ISC_TRIP EN# VOUT TON TR TOFF TF

8 uP7534-DS-F0302, Mar. 2012 www.upi-semi.com 100 120 -50 0 50 100 150 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.2 0.4 0.6 0.8 2.5 3.5 4.5 5.5 Low Level High Level Typical Operation Characteristics 2.5 3.5 4.5 5.5 OC# Delay Time vs. Input Voltage Input Voltage VIN (V) OC# Delay Time (ms) EN/EN# Threshold Level vs. Input Voltage Input Voltage VIN (V) High/Low Threshold Level (V) On Resistance vs. Input Voltage Input Voltage VIN (V) On Resistance (m Ω) Quiescent Current vs. Input Voltage Input Voltage VIN (V) Quiescent Current (uA) Short Circuit vs. Input Voltage Input Voltage VIN (V) Output Short Circuit Current (A) On Resistance vs. Temperature Junction Temperature ( OC) On Resistance (m Ω) 2.5 3 3.5 4 4.5 5 5.5 2.5 3 3.5 4 4.5 5 5.5

9uP7534-DS-F0302, Mar. 2012 www.upi-semi.com EN 2V/Div VOUT 2V/Div IIN 2A/Div0 0.2 0.4 0.6 0.8 -50 0 50 100 150 High Level Low Level VIN 2V/Div VOUT 2V/Div ILOAD 250mA/Div EN 2V/Div VOUT 2V/Div ILOAD 250mA/Div Turn Off Waveforms Time (100us/Div) VIN = 5V, COUT = 1uF, RLOAD = 10Ω -50 0 50 100 150 -50 0 50 100 150 EN/EN# Threshold Level vs. Temperature Junction Temperature ( OC) VIN = 5V High/Low Threshold Level (V) Turn On Waveforms Time (1ms/Div) VIN = 5V, COUT = 1600uF Quiescent Current vs. Temperature Junction Temperature ( OC) VIN = 5V Quiescent Current (uA) OC# Delay Time vs. Temperature Junction Temperature ( OC) VIN = 5V OC# Delay Time (ms) Power Off Waveforms Time (2.5ms/Div) CIN = COUT = 1uF, RLOAD = 10Ω Typical Operation Characteristics

10 uP7534-DS-F0302, Mar. 2012 www.upi-semi.com VOUT 5V/Div OC# 5V/Div IIN 2A/Div VOUT 5V/Div OC# 5V/Div ILOAD 2A/Div VIN 2V/Div VOUT 2V/Div ILOAD 250mA/Div OC# 2V/Div OC# Response Time (4ms/Div) Typical Operation Characteristics Power On Waveforms Time (2.5ms/Div) VIN = 5V, COUT = 1uF, RLOAD = 10Ω Short Circuit Protection and OTP Time (4ms/Div) VIN = 5V, COUT = 470uF, RLOAD = 0Ω

11uP7534-DS-F0302, Mar. 2012 www.upi-semi.com Supply Input Filtering VIN pins supply power to the power switch and internal circuit. Both of them should be connect to upstrem power supply with short and wide trace on the PCB. Events such as hot-plug/unplug, output short circuit and overtemperature result in step change of input current with sharp edges, which in turn causes voltage transient at supply input due to di/dit effect of parasitic inductance on the current path. A 0.1uF ceramic capacitor from VIN to GND, physically located near the device is strongly recommended to control the supply input transient. Minimizing the parasitic inductance along the current path also alleviate the voltage transient at the supply input. Output Voltage Filtering Bypassing the output voltage with a 0.1uF ceramic capacitor improves the immunity of the device against output short circuit and hot plug/unplug of load. A lower ESR capacitor results in lower voltage drop against a step load change. A large electrolytic capacitor from VOUT to GND is also recommended. This capacitor reduces power supply transient that may cause ringing on the input. USB supports dynamic attachment (hot plug-in) of peripherals. A current surge is caused by the input capacitance of downstream device. Ferrite beads are recommended in series with all power and ground connector pins. Ferrite beads reduce EMI and limit the inrush current during hot-attachment by filtering high-frequency signals. The DC resistance of the ferrite bead should be specially taken care to reduce the voltage drop. Voltage Drop and Power Dissipation Temperature effect should be well considered when dealing with voltage drop and power dissipation. The maximum R DS(ON) of the power switch is 100mΩ under 25OC junction temperature. If the device is expected to operate at 125OC junction temperature, the RDS(ON) will become where 0.5%/OC is the approximated temperature coefficient of the RDS(ON). If the maximum load current is expected to be 1.2A, the maximum voltage will become 1.2A * 150mΩ = 180mV This in turn will cause power dissipation as 1.2A * 180mV = 215mW The temperature raise is calculated as 215mW * 160 OC/W = 35OC The junction temperature is calculated as TA + 35OC, where TA is the expected maximum ambient temperature. A few iterations are required until get final solutions. Layout Consideration The power circuitry of usb printed circuit boards requires a customized layout to maximize thermal dissipation and to minimized voltage drop and EMI „ Place the device physically as close to the USB port as possible. Keep all traces wide, short and direct to minimized the parasitic inductance. This optimizes the switch response time to output short circuit conditions. „ Place both input and output bypass capacitors near to the device. „ If ferrite beads are used, use wires with minimum resistance and large solder pads to minimize connection resistance. „ All VOUT pins should be connected together on the PCB. All VIN pins should be connected together on the PCB.

Application Information

+ VBUS GNDBUS VOUT GND OC#EN# VIN uP7534BS8

12 uP7534-DS-F0302, Mar. 2012 www.upi-semi.com Note 1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm.

Package Information

0.32 - 0.52 5.80 - 6.20

1.27 BSC

3.80 - 4.00 4.80 - 5.00

8.00 MIN

1.85 REF

0.76 REF

1.27 REF

6.15 REF

Recommended Solder Pad Layout

4.00 MIN

3.81 BSC

0.10 - 0.25 0.18 - 0.25 0.41 - 0.89

0.20 BSC

1.75 MAX

1.45 - 1.60

13uP7534-DS-F0302, Mar. 2012 www.upi-semi.com 0.30 - 0.45

2.90 BSC

2.8 BSC

1.90 BSC

0.01 - 0.10

0.95 BSC

1.50 - 1.75 Recommended Solder Pad Layout 0.90 - 1.30

1.45 MAX

3.85 MAX

1.22 REF

0.62 MAX 0.95 REF 2.62 REF 1.40 MIN 0.08 - 0.22 0.30 - 0.60

0.25 BSC

1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm.

14 uP7534-DS-F0302, Mar. 2012 www.upi-semi.com 1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm. 0.22-0.38 0.00 - 0.15 0.08-0.23 0.40 - 0.80

4.50 REF

0.35 REF

0.65 REF

0.65 BSC

3.50 REF

Recommended Solder Pad Layout

1.10 MAX

0.75 - 0.95 1.00 REF 2.90 - 3.10 2.90 - 3.10 4.80 - 5.00

15uP7534-DS-F0302, Mar. 2012 www.upi-semi.com 1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm. 0.22 - 0.38 0.00 - 0.15 0.08-0.23 0.40 - 0.80 Recommended Solder Pad Layout 0.75 - 0.95 1.00 REF 1.40 - 2.15 1.42 - 2.15 1.38 - 1.85 1.30 - 1.90 2.90 - 3.10 4.80 - 5.00 2.90 - 3.10

16 uP7534-DS-F0302, Mar. 2012 www.upi-semi.com Important Notice uPI and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. uPI products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment. However, no res ponsibility is assumed by uPI or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of uPI or its subsidiaries. COPYRIGHT ( C) 2007, UPI SEMICONDUCTOR CORP . uPI Semiconductor Corp. Headquarter 9F.,No.5, Taiyuan 1st St. Zhubei City, Hsinchu Taiwan, R.O.C. uPI Semiconductor Corp. Sales Branch Office 12F-5, No. 408, Ruiguang Rd. Neihu District, Taipei Taiwan, R.O.C.