UP7501 UPI | Alldatasheet

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Technical content

Features

Note: uPI products are compatible with the current IPC/ JEDEC J-STD-020 requirement. They are halogen-free, RoHS compliant and 100% matte tin (Sn) plating that are suitable for use in SnPb or Pb-free soldering processes.

2 uP7501-DS-F0002, M ar. 2017 www.upi-se mi.com . o N e m a N n i P n o i t c n u F n i P 1 C C V 5 . t u p n I C C V 5 d l o h s e r h t R O P e h T . ) R O P ( t e s e r n o r e w o p r o f d e r o t i n o m y l s u o un i t n o c s i n i p s i h T . C C V 5 X T A o t n i p s i h t t c e n n o C . s i s e r e t s y h V 2 . 0 h t i wV 2 . 4 s i l e v e l

2 B S V 5

. t u p n I B S V 5 . R O P r o f d e r o t i n o m y l s u o u n i t n o c s i n i p s i h T . 1 0 5 7 P u e h t f o t up n i r e w o p s i n i p s i h T a h t i wB S V 5 X T A o t n i p s i h t d e t c e n n o C . s i s e r e t s y h V 2 . 0 h t i wV 2 . 4 s i l e v e l d l o h s e r h t R O P e h T . n i p D N Go t y l t c e r i d r o t i c a p a c g n i l p u o c e d c i m a r e c 3 D N G . d n u o r G

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. n o i t c e l e S e d o M 5 S / 4 S g n i r u d n o s y a t s r o n w o d t u h s s i L A U D V 5 r e h t e h w s m a r g o r pn i p s i h T e n a l p L A U D V 5 e h t s r e w o p h g i h c i g o L . e t a t s 5 S / 4 S g n i r u d L A U D V5 n w o d s t u h s w o l c i g o L . e t a t s . e t a t s 5 S / 4 S g n i r u d B S V 5 X T Am o r f 5 # 3 S . t u p n I # 3 S , 0 S ( e v i t c am o r f e t a t s g n i t a r e p o s ' C I e h t s e h c t i w s # 5 S h t i wd e i n a p m o c n i p s i h T . e c r u o s t n e r r u c A u 7 a y b n w o d d e l l u p y l l a n r e t n i s i n i p s i h T . se t a t s p e e l s 5 S / 4 S d n a 3 S o t ) 2 S / 1 S s ' m e t s y s r e t u p m o c e h t o t n i p s i h t t c e n n o C . h g i h s i # 5 S n e h w 3 Ss a d e d r a g e r s i # 3 S f o 0 e t a t S . s l a n g i s 3 S _ P L S 6 # 5 S . t u p n I # 5 S , 0 S ( e v i t c am o r f e t a t s g n i t a r e p o s ' C I e h t s e h c t i w s # 3 S h t i wd e i n a p m o c n i p s i h T . e c r u o s t n e r r u c A u 7 a y b n w o d d e l l u p y l l a n r e t n i s i n i p s i h T . se t a t s p e e l s 5 S / 4 S d n a 3 S o t ) 2 S / 1 S e h t o t n i p s i h t t c e n n o C . e t a t s # 3 Se h t f o s s e l d r a g e r 5 S / 4 S s a d e d r a g e r s i # 5 S f o 0 e t a t S . s l a n g i s 5 S _ P L S s ' m e t s y s r e t u p m o c 7 V R D _ B S V 5 . B S V 5 r o f t u p t u O r e v i r D s i r o t s i s n a r t e h T . S O M P e l b a t i u s a f o e t a g e h t o t n i p s i h t t c e nn o C . s u t a t s s n i p E D O Md n a # 3 S , # 5 S g n i d r o c c a f f o / n o d e h c t i w s

8 V R D _ C C V 5

. C C V 5 r o f t u p t u O r e v i r D s i r o t s i s n a r t e h T . S O M Ne l b a t i u s a f o e t a g e h t o t n i p s i h t t c e n n o C k 1 n A . t u p t u o n i a r d - n e p o n a s i n i p s i h T . s u t a t s s n i p # 3 S d n a # 5S g n i d r o c c a f f o / n o d e h c t i w s Ω e l b a t i u s f o s e t a g e h t l l u p o t t u p t u o C C V 2 1 X T A e h t o t n i p s i h t mo r f d e t c e n n o c e b t s u m r o t s i s e r d e r o t i n o mo s l a s i n i p s i h T . t u p t u o L A U D V 5 o t n i t u p t u o C C V 5 X T A s e h c t i w st a h t V 2 1 o t S O M N . s i s e r e t s y h V 1 h t i wV 9 s i l e v e l d l o h s e r h t R O P e h T . R O PC C V 2 1 r o f Functional Pin Description

3uP7501-DS-F0002, M ar. 2017 www.upi-se mi.com S5# MODE S3# 5VCC_DRV 5VSB_DRV 5VSB POR 4.2V 5VCC POR 4.2V 6.6ms delay 5VSB_POR 5VCC_POR POR 9V 12VCC_POR Control Logic Soft Start GND 4.7uA SoftStart Functional Block Diagram

stays on during S4/S5 state. even if S3# and S5# are both high. Figure 1. 12VCC POR Table 1. 5VDUAL Output Truth Table

0 X 1 B S V 5 5 S / 4 S

0 X 0 n w o d t u h S 5 S / 4 S

S5#=1, S3#=1 ,and MODE=X, 5VDAUL is 5VSB. ensure a seamless 5VDUAL output. drops below POR and rises again. Figure 2. Timing Diagram with MODE = L

8 uP7501-DS-F0002, M ar. 2017 www.upi-se mi.com (V5VSB = 5V, TA = 25OC, unless otherwise specified) ESD Rating (Note 2) Package Thermal Resistance (Note 3) Power Dissipation, PD @ TA = 25°C r e t e m a r a P l o b m y S s n o i t i d n o C t s e T n i M p y T x a M t i n U t u p n I y l p p u S t n e r r u C y l p p u S l a n i m o NI B S V 5 - - 3 . 0 - - A m t e s e R n O r e w o P d l o h s e r h T R O P B S V 5 g n i s i RV R O P _ B S V 5 8 . 3 2 . 4 5 . 4 V s i s e r e t s y H R O P B S V 5V S Y H _ B S V 5 - - 2 . 0 - - V R O P V R D _ C C V 5 g n i s i R d l o h s e r h T V R O P _ V R D C C V 5 k 1Ω C C V 2 1 d n a V R D _ C C V 5 n e e w t e b r o t s i s e r g n i s i r V R D _ C C V 5 ; l i a R- - 0 . 9 5 . 0 1V s i s e r e t s y H R O P V R D _ C C V 5V S Y H _ V R D C C V 5 k 1Ω C C V 2 1 d n a V R D _ C C V 5 n e e w t e b r o t s i s e r g n i l l a f V R D _ C C V 5 ; l i a R- - 0 . 1 - - V d l o h s e r h T R O P C C V 5 g n i s i RV R O P _ C C V 5 8 . 3 2 . 4 5 . 4 V d l o h s e r h T R O P C C V 5 g n i l l a FV S Y H _ C C V 5 - - 2 . 0 - - V e m i T y a l e D g n i s i R R O P C C V 5 g n i s i r V R D _ C C V 5 o t R O P g n i s i r C C V 5 m o r F1 5 0 1 s m Absolute Maximum Rating Thermal Information Recommended Operation Conditions

Electrical Characteristics

9uP7501-DS-F0002, M ar. 2017 www.upi-se mi.com r e t e m a r a P l o b m y S s n o i t i d n o C t s e T n i M p y T x a M s t i n U r e l l o r t n o C h c t i w S t n e r r u C e c r u o S V R D _ B S V 5I V R D _ B S V 5 V 5 = B S V 5 , V 0 = V R D _ B S V 50 2 - - 5 3 A m t n e r r u C k n i S V R D _ B S V 5I V R D _ B S V 5 V 5 = B S V 5 , V 5 = V R D _ B S V 50 2 - - 5 3 A m t r a t S t f o S V R D _ B S V 5 t n e r r u C g n i k n i SI V R D _ B S V 5 - - 0 . 4 - - A u t n e r r u C k n i S V R D _ C C V 5I V R D _ C C V 5 V 5 = B S V 5 , V 5 = V R D _ C C V 50 2 - - - - A m ) E D O M d n a , # 5 S , # 3 S ( O / I l o r t n o C d l o h s e r h T t u p n I l e v e L h g i H - - 0 . 2 V d l o h s e r h T t u p n I l e v e L w o L 8 . 0 - - V n w o D l l u P l a n r e t n I # 5 S , # 3 S D N G o t t n e r r u C - 7 - A u Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. θ JA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity te st board of JEDEC 51-3 thermal measurement standard. Note 4. The device is not guaranteed to function outside its operating conditions.

10 uP7501-DS-F0002, M ar. 2017 www.upi-se mi.com Typical Operation Characteristics Soft Start for 5VSB 2.5ms/Div MODE = High; CGD = 3.3nF at PMOS 5VSBDRV (2V/Div) 5VDUAL (2V/Div) 5VSB (2V/ Div) 5VCC Power On with 5VDUAL Ready 2.5ms/Div MODE = High; S3/S5 into S0 5VSBDRV (5V/Div) 5VDUAL (5V/Div) 5VCC (5V/Div) 5VCCDRV (10V/Div) 5VCC Power On with 5VDUAL Off 2.5ms/Div MODE = Low; S5 into S0 5VSBDRV (5V/Div) 5VDUAL (2V/Div) 5VCC (2V/Div) 5VCCDRV (5V/Div) 12VCC Power On with 5VDUAL Ready 2.5ms/Div MODE = High; S3/S5 into S0 5VCCDRV (5V/Div) 5VDUAL (5V/Div) 12VCC (5V/Div) 5VSBDRV (5V/Div) S0 into S5 with MODE = High 50us/Div MODE = High; S0 into S5 5VDUAL (5V/Div) 5VSBDRV (5V/Div) S5# (5V/Div) 5VCCDRV (10V/Div) S0 into S5 with MODE = Low 250us/Div MODE = Low; S0 into S5 5VDUAL (1V/Div/AC) 5VSBDRV (5V/Div) S5# (5V/Div) 5VCCDRV (10V/Div)