UP3861P UPI | Alldatasheet
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ATX Power Supplies Power Supplies for Microprocessors or Subsystem Power Supplies Cable Modems, Set Top Boxes, and xDSL Modems Industrial Power Supplies; General Purpose Supplies 5V or 12V Input DC-DC Regulators Low Voltage Distributed Power Supplies Note: uPI products are compatible with the current IPC/ JEDEC J-STD-020 requirement. They are halogen-free, RoHS compliant and 100% matte tin (Sn) plating that are suitable for use in SnPb or Pb-free soldering processes. RTFB1 SS FB2 COMP2 COMP1 OCSET1 GND 81 3 VCC BOOT1 UG1 PH1 OCSET BOOT2 UG2 PH2 LG1 PGND 11
12 LG2
2 uP3861P-DS-F0002, Feb. 2018 www.upi-semi.com Typical Application Circuit FB1 COMP1 UG2UG1 PH1 OCSET2 BOOT2 PH2 FB2 PGND LG2 COMP2 LG1 PGND OCSET1 uP3861 BOOT1 SS/EN GND VCC RT VCC VINVIN VOUT 2VOUT1 R1_1 R2_1 R1_2 R2_2 SEQ VCC Option pull high or low
3uP3861P-DS-F0002, Feb. 2018 www.upi-semi.com e m aNn o i t c n u F n i P 1 B F . t u p n i 1 k c a b d e e F e g a t l o V t u p t u Oat c e n n o C . 1 r e i f i l p m a r o r r e e h t f o t u p n i g n i t r e v n i e h t s i n i p eh T . e g a t l o v t u p t u o e h t t e s o t r e d i v i d e g a t l o v
1 P M O C
. t u p t u O1 n o i t a s n e p m o C fo t u p n i g n i t r e v n i - n o n e h t d n a 1 r e i f i l p m a r o r r e e h t f o t u p t u oe h t s i n i p s i h T kc a b d e e f l o r t n o c - e g a t l o v e h t e t a s n e p m o c o t n i p 1 B F o t k r o w t enC R a t c e n n o C . s r o t a r a p m o c 1 MWP . r e t r e v n o c 1 l e n n a h c e h t f o p o o l 1 T E S C O . g n i t t e S l e v e L 1 P C O tn e r r u c r e v o 1 l e n n a h c e h t t e s o t e g a t s r e w o p f o t u p n i y l p p u s o tr o t s i s e r a t c e n n o C e s i o n g n i h c t i w s e h t t u o r e t l i f o t r o t s i s e r e h t h t i w l e l l a r a pn i r o t i c a p a c A . l e v e l d l o h s e r h t n o i t c e t o r p D N G . d n u o r Gg o l a n A C C V . t i u c r i c l o r t n o C r o f e g a t l o V y l p p u Se h T . t i u c r i c l o r t n o c l a n r e t n i r o f e g a t l o v y l p p u s s e d i v o r p ni p s i h T - ll e w a t c e n n o c . V 1 F E R V d n a t i u c r i c l o r t n o c l a n r e t n i r o f D D V 5 ot d e t a l u g e r y l l a n r e t n i s i e g a t l o v y l p p u s ra e n d e c a l p s i r o t i c a p a c g n i l p u o c e d t a h t e r u s n E . n i p s i h t o t eg a t l o v y l p p u s V 2 . 3 1 o t V 8 . 0 1 d e l p u o c e d . C I e h t
1 T O O B
. r e v i r De t a G r e p p Ue h T r o f y l p p u S 1 p a r t s t o o B C r o t i c a p a c p a r t s t o o b e h t t c e n n o CT O O B ne e w t e b nr u t o t e g r a h c e h t s e d i v o r p r o t i c a p a c p a r t s t o o b e h T . t i u c r i cp a r t s t o o b am r o f o t n i p 1 H P d n a 1 T O O B . 1 T E F S O M r e p p u e h t n o
1 G U
. t u p t u O 1 r e v i r D e t a G r e p p U d e r o t i n o m s i n i p s i h T . 1 T E F S O M r e p p u f o e t a g e h t o t n i p s i h t t ce n n o C de n r u t s a h 1 T E F S O M r e p p u e h t n e h w e n i m r e t e d o t y r t i u c r i c n o i tc e t o r p h g u o r h t - t o o h s e v i t p a d a e h t y b . f f o
1 H P
. e d o N h c t i w S 1 E S A H P re w o l e h t f o n i a r d e h t d n a 1 T E F S O M r e p p u e h t e c r u o s e h t o t n i p s ih t t c e n n o C -t o o h s e v i t p a d a e h t y b d e r o t i n o ms i d n a e v i r d 1 G Ue h t r o f k n i s e h t s a d e s u s i n i p s i h T . 1 T E F S O M . f f o d e n r u t s a h 1 T E F S O M r e p p u e h t n e h w e n i m r e t e d o t y r t i u c r ic n o i t c e t o r p h g u o r h t 1 G L . t u p t u o r e v i r D e t a G r e w o L d e r o t i n o m s i n i p s i h T e i T . 1 T E F S O M r e w o l f o e t a g e h t o t n i p s i ht t c e n n o C . ff o n r u t d a h 1 T E F S O M r e w o l e h t n e h w e n i m r e t e d o t y r t i u c r i c n o it c e t o r p h g u o r h t - t o o h s e v i t p a d a e h t y b D N G P . C I e h T r o f d n u o r G r e w o P fo e c r u o s e h t n i p s i h t e i T . r e v i r d e t a g r e w o l e h t f o n r u t e r e h t si n i p s i h T . e c a r t t r o h s d n a e d i w h t i w T E F S O M r e w o l Q E S . e c n e u q e S n o r e w o P ni p e h t t c e n n o c f I . t s r i f t r a t s - t f o s 1 l e n n a h c t c e l e s o t w o l d es a i b - f l e s s i n i p e h T . t s r i f t r a t s - t f o s l l i w 2 l e n n a h c , C C V o t 2 G L . t u p t u O r e v i r D e t a G r e w o L d e r o t i n o m s i n i p s i h T e i T . 2 T E F S O M r e w o l f o e t a g e h t o t n i p s i ht t c e n n o C . ff o n r u t d a h 2 T E F S O M r e w o l e h t n e h w e n i m r e t e d o t y r t i u c r i c n o it c e t o r p h g u o r h t - t o o h s e v i t p a d a e h t y b
2 H P
. e d o N h c t i w S 2 E S A H P re w o l e h t f o n i a r d e h t d n a 2 T E F S O M r e p p u e h t e c r u o s e h t o t n i p s ih t t c e n n o C -t o o h s e v i t p a d a e h t y b d e r o t i n o ms i d n a e v i r d 2 G Ue h t r o f k n i s e h t s a d e s u s i n i p s i h T . 2 T E F S O M . f f o d e n r u t s a h 2 T E F S O M r e p p u e h t n e h w e n i m r e t e d o t y r t i u c r ic n o i t c e t o r p h g u o r h t
2 G U
. t u p t u O 2 r e v i r D e t a G r e p p U d e r o t i n o m s i n i p s i h T . 2 T E F S O M r e p p u f o e t a g e h t o t n i p s i h t t ce n n o C de n r u t s a h 2 T E F S O M r e p p u e h t n e h w e n i m r e t e d o t y r t i u c r i c n o i tc e t o r p h g u o r h t - t o o h s e v i t p a d a e h t y b . f f o
2 T O O B
. r e v i r De t a G r e p p Ue h T r o f y l p p u S 2 p a r t s t o o B C r o t i c a p a c p a r t s t o o b e h t t c e n n o CT O O B ne e w t e b nr u t o t e g r a h c e h t s e d i v o r p r o t i c a p a c p a r t s t o o b e h T . t i u c r i cp a r t s t o o b am r o f o t n i p 2 H P d n a 2 T O O B . 2 T E F S O M r e p p u e h t n o 2 T E S C O . g n i t t e S l e v e L 2 P C O tn e r r u c r e v o 2 l e n n a h c e h t t e s o t e g a t s r e w o p f o t u p n i y l p p u s o tr o t s i s e r a t c e n n o C e s i o n g n i h c t i w s e h t t u o r e t l i f o t r o t s i s e r e h t h t i w l e l l a r a pn i r o t i c a p a c A . l e v e l d l o h s e r h t n o i t c e t o r p
2 P M O C
. t u p t u O2 n o i t a s n e p m o C fo t u p n i g n i t r e v n i - n o n e h t d n a 2 r e i f i l p m a r o r r e e h t f o t u p t u oe h t s i n i p s i h T kc a b d e e f l o r t n o c - e g a t l o v e h t e t a s n e p m o c o t n i p 2 B F o t k r o w t enC R a t c e n n o C . s r o t a r a p m o c 2 MWP . r e t r e v n o c 2 l e n n a h c e h t f o p o o l Functional Pin Description
4 uP3861P-DS-F0002, Feb. 2018 www.upi-semi.com Functional Block Diagram e m aNn o i t c n u F n i P 2 B F . t u p n I 2 k c a b d e e F e g a t l o V t u p t u Otc e n n o c . 2 r e i f i l p m a r o r r e e h t f o t u p n i g n i t r e v n i e h t s i n i p e hT . e g a t l o v t u p t u o e h t t e s o t r e d i v i d e g a t l o v a / S S n w o D t u h S . n w o D t u h S / g n i t t e S t r a t S t f o Sp u - p m a r e h t t e s o t D N Go t n i p s i h t m o r f r o t i c a p a c a t c e n n o C V n e h w . e g a t l o v t u p t u o f o w e l sS S . C I e h t n w o d s t u h s V 7 . 0 w o l e b s l l u p T R . t u p n I g n i t t e S y c n e u q e r F . y c n e u q e r f h c t i w s t e s o t D N Go t n i p s i h t m o r f r o t s i s e r a t c e n n o C Functional Pin Description Gate Control Logic Amplifier Error Oscillator PWM1 COMP2 BOOT1 UG1 PH1 LG1Comparators PWM Soft Start FB2 Internal Regulator VCC12 VREF POR PWM2 BOOT2 UG2 LG2 RT SS/EN Gate Control LogicPH2 PGND Amplifier Error VREF COMP 1 FB1 OCP 2 VREF OCSET2 OVP 2 1.2V UVP 2 0.5V PGND OCP 1 OCSET 1 OVP 1 30uA 5VDD 0.5V 1.2V IOCSET IOCSET UVP 1 SEQ
discharged completely, another soft start cycle is initiated. 3 times and then latch off uP3861P. 3.) Consider the inductor ripple current. Figure 3. OCP Level Programming type protection and can only be reset by POR of the device. The FB1/2 voltage is monitored for over voltage protection. only be reset by POR of the device.
8 uP3861P-DS-F0002, Feb. 2018 www.upi-semi.com PH to GND BOOT to GND UG to PH LG to GND Storage Temperature Range ESD Rating (Note2) Package Thermal Resistance (Note 3) Power Dissipation, PD @ TA = 25°C Absolute Maximum Rating Thermal Information Recommended Operation Conditions
9uP3861P-DS-F0002, Feb. 2018 www.upi-semi.com r e t e m a r aPl o b m ySs n o i t i d n o C t s eTn iMp yTx a M st i n U t u p n I y l p p u S e g n a R e g a t l o V y l p p uSV C C 8 . 01- -2 . 31V t n e r r u C t u p n I y l p p uSI C C n e p OG L d n a GU- -50 1A m t e s e Rn O r e w o P d l o h s e r h T R O PC CVV H T R C CV C C . g n i s iR9 5.90 1V d l o h s e r h T R O PC CVV 1 _ H T F C CV C C g n i l l aF5 .70 .85 .8V V g n i s i RT E S C O d l o h s e r hTV H T _ T E S C O --6 .1- -V V T E S C O e g a t l o V s i s e r e t s yHV S Y H T E S C O --6 .0- -V r o t a l l i c s O y c a r u c c A y c n e u q e r F 5 1-- -5 1+% y c n e u q e r F g n i n n u R e e rFc s oFn e p O= TR- -0 5- -z H k e g n a R t n e m t s u j d A 05- -0 04z H k e d u t i l p m A p m aRc s oV- -9 .1- -V e l c y C y t u Dm u m i n i M --0- -% n o i t a R y t u D 0- -0 9% e c n e r e f e R e g a t l o V e c n e r e f eRV F E R --1 - -V e c n a r e l o T e g a t l o V e c n e r e f e R 8 . 0-- -8 . 0+% r e i f i l p m A r o r r EMWP n i a Gp o o L n e pOn i aGR L C , K 0 1 =L F p 0 1=0 70 8- -B d h t d i w d n a B p o o L n e pOP WBGR L C , K 0 1 =L F p 0 1=- -0 1- -z H M e t a Rw e lSR SR L C , K 0 1 =L F p 0 1=3 6 --s u / V t n e r r u c t u p n i BFI 2 / 1 B F --1 0 .01 .0A u e g a t l o V h g i HP M OCV H _ P M O C --5 .5- -V e g a t l o Vw o L P M OCV L _ P M O C --0- -V t n e r r u C e c r u o SP M O C --2- -A m t n e r r u C k n i SP M O C --2- -A m r e v i r DE T A G e c n a d e p m I e c r u o S e t a G r e p pUR C R S _ G UIG U g n i c r u o s A m 0 0 1=- -3 5 Ω e c n a d e p m I k n i S e t a G r e p pUR K N S _ G UIG U g n i k n i s A m 0 0 1=- -1 2 Ω e c n a d e p m I e c r u o S e t a G r e w oLR C R S _ G LIG L g n i c r u o s A m 0 0 1=- -5 .10 . 3 Ω e c n a d e p m I k n i S e t a G r e w oLR K N S _ G LIG L g n i k n i s A m 0 0 1=- --2 4 Ω y a l e D g n i s i RG L o t g n i l l a F HPV H P V o t V 2 . 1 <G L V 2 . 1>- -0 3- -s n y a l e D g n i s i RG U o t g n i l l a FGLV G L V ( o t V 2 . 1 <G U V -H P V 2 . 1 >)- -0 3- -s n
Electrical Characteristics
(VCC = PVCC = 12V, TA = 25O C, unless otherwise specified)
10 uP3861P-DS-F0002, Feb. 2018 www.upi-semi.com r e t e m a r aPl o b m ySs n o i t i d n o C t s eTn iMp yTx aMs t i n U n o i t c e t o r P t n e r r u C e g r a h C t r a t s - t f oSI S S V S S V 0=4 20 36 3A u l e v e L d l o h s e r h T P VOV P V O g n i s i r B FV- -3 .1- -V e m i T y a l e DP V O --5 2- -s u l e v e L d l o h s e r h T P VUV P V U V B F g n i l l a f - - 5 5 .0- -V e m i T y a l e DP V U --2- -s u l e v e l P T O --0 51- - 0C e c r u o S t n e r r u C k n i S T E S COI 2 / 1 T E S C OV 2 / 1 T E S C OV =C C 3 . 0-0 810 020 22A u e m i T y a l e D T E S C O --3- -s u Q E S h g i H t u p nIH Q ES6 .2- -- -V w o L t u p nIL Q ES- -- -4 .0V e c n a t s i s e Rw o L l l u PQ E S --0 01- -k Ω Note 1. Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. θJA is measured in the natural convection at TA = 25O C on a low effective thermal conductivity test board of JEDEC 51-7 thermal measurement standard. Note 4. The device is not guaranteed to function outside its operating conditions.
11uP3861P-DS-F0002, Feb. 2018 www.upi-semi.com VOUT 1 2V/Div VOUT 2 2V/Div VIN 5V/Div VSS 2V/Div VOUT 2V/Div PH 10V/Div IOUT 10A/Div SS 2V/Div VOUT 2V/Div PH 10V/Div IOUT 10A/Div Time (4ms/Div) VIN = 12V, VCC = 12V, ILOAD = 2A VOUT 1 2V/Div VOUT 2 2V/Div VSS 5V/Div VOUT 1 2V/Div VOUT 2 2V/Div VSS 5V/Div VOUT 1 2V/Div VOUT 2 2V/Div VIN 5V/Div Power On Waveforms Enable for uP3861 Time (2ms/Div) VIN = 12V, VCC = 12V, ILOAD = 2A Typical Operation Characteristics OCP Time (4ms/Div) SCP Time (10ms/Div) Disable for uP3861 Time (2ms/Div) VIN = 12V, VCC = 12V, ILOAD = 2A Time (4ms/Div) VIN = 12V, VCC = 12V, ILOAD = 2A Power Off Waveforms
12 uP3861P-DS-F0002, Feb. 2018 www.upi-semi.com 137 138 139 140 141 142 143 144 145 146 -40 -20 0 20 40 60 80 100 120 140 160 0.990 0.995 1.000 1.005 1.010 -40 -20 0 20 40 60 80 100 120 UG 10V/Div PH 10V/Div LG 10V/Div UG-PH 10V/Div Typical Operation Characteristics FB Voltage vs. Temperature Temperature (O C) FB Voltage (V) Switching Frequency vs. Temperature Temperature (O C) Switching Frequency (kHz) Gate Waveforms Time (40ns/Div) VIN = 12V, VCC = 12V, ILOAD = 10A e UG 10V/Div PH 10V/Div LG 10V/Div UG-PH 10V/Div Gate Waveforms Time (40ns/Div) VIN = 12V, VCC = 12V, ILOAD = 10A
13uP3861P-DS-F0002, Feb. 2018 www.upi-semi.com
Application Information
External component selection is primarily determined by the maximum load current and begins with the selection of power MOSFET switches. The uP3861P requires two external N-channel power MOSFETs for upper (controlled) and lower (synchronous) switches. Important parameters for the power MOSFETs are the breakdown voltage V(BR)DSS, on-resistance RDS(ON) , reverse transfer capacitance CRSS , maximum current IDS(MAX) , gate supply requirements, and thermal management requirements. The gate drive voltage is powered by VCC pin that receives 10.8V~13.2V supply voltage. When operating with a 12V power supply for VCC (or down to a minimum supply voltage of 8V), a wide variety of NMOSFETs can be used. Logic-level threshold MOSFET should be used if the input voltage is expected to drop below 8V. Since the lower MOSFET is used as the current sensing element, particular attention must be paid to its on-resistance. Look for RDS(ON) ratings at lowest gate driving voltage. Special cautions should be exercised on the lower switch exhibiting very low threshold voltage VGS(TH). The shoot- through protection present aboard the uP3861P may be circumvented by these MOSFETs if they have large parasitic impedances and/or capacitances that would inhibit the gate of the MOSFET from being discharged below its threshold level before the complementary MOSFET is turned on. Also avoid MOSFETs with excessive switching times; the circuitry is expecting transitions to occur in under 50 nsec or so. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty cycle. Since the uP3861P is operating in continuous conduction mode, the duty cycles for the MOSFETs are: IN OUT UP V VD = ; IN OUTIN LO V VVD −= The resulting power dissipation in the MOSFETs at maximum output current are: OS CSWINOUTUP)ON(DS LO)ON(DS OUTLO DRIP ××= where TSW is the combined switch ON and OFF time. Both MOSFETs have I2R losses and the top MOSFET includes an additional term for switching losses, which are largest at high input voltages. The bottom MOSFET losses are greatest when the bottom duty cycle is near 88%, during a short-circuit or at high input voltage. These equations assume linear voltage current transitions and do not adequately model power loss due the reverse-recovery of the lower MOSFET’s body diode. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. The gate-charge losses are dissipated by the uP3861P and don’theat the MOSFETs. However, large gate charge increases the switching interval, TSW that increases the MOSFET switching losses. The gate-charge losses are calculated as: OS CRSSINLO_ISSUP_ISSCCCCG f )CV)CC (V (VP ××++××= where CISS_UP is the input capacitance of the upper MOSFET, C ISS_LO is the input capacitance of the lower MOSFET, and CRSS_UP is the reverse transfer capacitance of the upper MOSFET . Make sure that the gate-charge loss will not cause over temperature at uP3861, especially with large gate capacitance and high supply voltage. Output Inductor Selection Output inductor selection usually is based the considerations of inductance, rated current, size requirement, and DC resistance (DC) Given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: V1 (VLf IN OUT OUT OUTOSC Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Highest efficiency operation is obtained at low frequency with small ripple current. However, achieving this requires a large inductor. There is a tradeoff between component size, efficiency and operating frequency. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX) . There is another tradeoff between output ripple current/ voltage and response time to a transient load. Increasing the value of inductance reduces the output ripple current and voltage. However, the large inductance values reduce the converter’s response time to a load transient.
14 uP3861P-DS-F0002, Feb. 2018 www.upi-semi.com Maximum current ratings of the inductor are generally specified in two methods: permissible DC current and saturation current. Permissible DC current is the allowable DC current that causes 40O C temperature raise. The saturation current is the allowable current that causes 10% inductance loss. Make sure that the inductor will not saturate over the operation conditions including temperature range, input voltage range, and maximum output current. The size requirements refer to the area and height requirement for a particular design. For better efficiency, choose a low DC resistance inductor. DCR is usually inversely proportional to size. Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs. size requirements and any radiated field/EMI requirements. Input Capacitor Selection The synchronous-rectified buck converter draws pulsed current with sharp edges from the input capacitor resulting in ripples and spikes at the input supply voltage. Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time upper MOSFET turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of upper MOSET and the source of lower MOSFET to avoid the stray inductance along the connection trace. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck converter is calculated as: IN OUTINOUT )MAX(OUT)RMS(IN V )VV (VII −= This formula has a maximum at VIN = 2VOUT , where IIN(RMS) = IOUT(RMS) /2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the capacitor manufacturer’s ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Always consult the manufacturer if there is any question. For a through-hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can also be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. Some capacitor series available from reputable manufacturers are surge current tested. Output Capacitor Selection An output capacitor is required to filter the output and supply the load transient current. The selection of COUT is primarily determined by the ESR required to minimize voltage ripple and load step transients. The output ripple ∆VOUT is approximately bounded by: )Cf 8 1ESR( IV OUTOSC Since ∆IL increases with input voltage, the output ripple is highest at maximum input voltage. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the necessary RMS current rating. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern components and loads are capable of producing transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor’s ESR will determine the output ripple voltage
15uP3861P-DS-F0002, Feb. 2018 www.upi-semi.com and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor’s ESR value is related to the case size with lower ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. Bootstrap Capacitor Selection An external bootstrap capacitor CBOOT connected to the BOOT pin supplies the gate drive voltage for the upper MOSFET. This capacitor is charged through the internal diode when the PHASE node is low. When the upper MOSFET turns on, the PHASE node rises to VIN and the BOOT pin rises to approximately VIN + VCC . The boot capacitor needs to store about 100 times the gate charge required by the upper MOSFET . In most applications 0.1uF to 0.47uF, X5R or X7R dielectric capacitor is adequate. PCB Layout Considerations High speed switching and relatively large peak currents in a synchronous-rectified buck converter make the PCB layout a very important part of design. Fast current switching from one device to another in a synchronous-rectified buck converter causes voltage spikes across the interconnecting impedances and parasitic circuit elements. The voltage spikes can degrade efficiency and radiate noise that result in overvoltage stress on devices. Careful component placement layout and printed circuit design minimizes the voltage spikes induced in the converter. Follow the layout guidelines for optimal performance of uP3861
1 The upper and lower MOSFETs turn on/off and conduct
pulsed current alternatively with high slew rate transition. Any inductance in the switched current path generates a large voltage spike during the switching. The interconnecting wires indicated by red heavy lines conduct pulsed current with sharp transient and should be part of a ground or power plane in a printed circuit board to minimize the voltage spike. Make all the connection the top layer with wide, copper filled areas.
2 Place the power components as physically close as
possible.
2.1 Place the input capacitors, especially the high-
frequency ceramic decoupling capacitors, directly to the drain of upper MOSFET ad the source of the lower MOSFET. To reduce the ESR replace the single input capacitor with two parallel units
2.2 Place the output capacitor between the converter
and load.
3 Place the uP3861P near the upper and lower MOSFETs
with pins 6 to 9 or 12 to 15 facing the power components. Keep the components connected to pins 1 to 5 or 17 to 20 close to the uP3861P and away from the inductor and other noise sources (noise sensitive components).
4 Use a dedicated grounding plane and use vias to ground
all critical components to this layer. The ground plane layer should not have any traces and it should be as close as possible to the layer with power MOSFETs. Use an immediate via to connect the components to ground plane including GND of uP3861P Use several bigger vias for power components.
5 Apply another solid layer as a power plane and cut this
plane into smaller islands of common voltage levels. The power plane should support the input power and output power nodes to maintain good voltage filtering and to keep power losses low. Also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. 6 The PHASE node is subject to very high dV/dt voltages. Stray capacitance between this island and the surrounding circuitry tend to induce current spike and capacitive noise coupling. Keep the sensitive circuit away from the PHASE node and keep the PCB area small to limit the capacitive coupling. However, the PCB area should be kept moderate since it also acts as main heat convection path of the lower MOSFET. 7 uP3861P sources/sinks impulse current with 2A peak to turn on/off the upper and lower MOSFETs. The connecting trance between the controller and gate/ source of the MOSFET should be wide and short to minimize the parasitic inductance along the traces. 8 Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power component.
9 Provide local VCC decoupling between VCC and GND
pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins.
16 uP3861P-DS-F0002, Feb. 2018 www.upi-semi.com
Package Information
1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm. SOP-20L 12.60 - 13.00 10.00 - 10.65 0.10 - 0.30 0.41 - 1.27
1.27 BSC
7.39 - 7.60 Recommended Solder Pad Layout
2.65 MAX
11.00 10±0. 1.50 10±0. 9.09 10±0. 7.70 10±0. 0.33 - 0.51 0.23 - 0.32
17uP3861P-DS-F0002, Feb. 2018 www.upi-semi.com Important Notice uPI and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. uPI products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment. However, no responsibility is assumed by uPI or its subsidiaries for its use or application of any product or circuit; nor for any infringements of patents or other rights of third parties which may result from its use or application, including but not limited to any consequential or incidental damages. No uPI components are designed, intended or authorized for use in military, aerospace, automotive applications nor in systems for surgical implantation or life-sustaining. No license is granted by implication or otherwise under any patent or patent rights of uPI or its subsidiaries. COPYRIGHT ( C ) 2011, UPI SEMICONDUCTOR CORP. uPI Semiconductor Corp. Headquarter 9F.,No.5, Taiyuan 1st St. Zhubei City, Hsinchu Taiwan, R.O.C. uPI Semiconductor Corp. Sales Branch Office 12F-5, No. 408, Ruiguang Rd. Neihu District, Taipei Taiwan, R.O.C.