UP1784

UP1784 UPI | Alldatasheet

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Features

Dual 1.5MHz, 1.3A, High-Efficiency Synchronous-Rectified Buck Converter Pin Configuration VIN1 GND LX1 FB1 EN2 LX2 EN1 FB2 VIN2 PSOP-8L GND LX1 GND1 VIN1 FB2 EN2 EN1 FB1 VIN2 GND2 LX2 VDFN3x3 – 10L GND LX1 EN2 EN1 LX2 VIN2 VIN1 WDFN3x3 - 12L

4 GND2FB1

Note: uPI products are compatible with the current IPC/ JEDEC J-STD-020 requirement. They are halogen-free, RoHS compliant and 100% matte tin (Sn) plating that are suitable for use in SnPb or Pb-free soldering processes.

2 uP1784-DS-F0000, Oct. 2013 www.upi-semi.com Functional Block Diagram 1/2 of uP1784 Control Logic Driver Current SenseCurrent Limit Detector Under Voltage Protection Slope Compensation OSC & Shutdown Control VREF EN GND FB VIN LX Typical Application Circuit LX2 EN2 FB2 GND2GND1 FB1 LX1 EN1 VIN1 VIN2 VOUT2VOUT1 VIN ON OFFOFF ON COUT1 COUT2 CIN1 CIN2 L1 L2 C1 C2 V N I V T U O C 2 N IC /1 N I L1 L /2 C 2 T U OC / 1 T U OC 1 C /2 R 1 R /3 R 2 R /4 V 3 .3V 2 .1F u 7 .4H u 2 .2F u 01F p 0 72K 01K 0 1 V 3 .3V 8 .1F u 7 .4H u 2 .2F u 01F p 0 81K 01K 0 2 V5V 1F u 7 .4H u 2 .2F u 01F n 2 .1K 01K 8 . 6 V5V 2 .1F u 7 .4H u 2 .2F u 01F p 0 72K 01K 0 1 V5V 8 .1F u 7 .4H u 2 .2F u 01F p 0 81K 01K 0 2 V5V 3 .3F u 7 .4H u 2 .2F u 01F p 72K 51K 8 6

3uP1784-DS-F0000, Oct. 2013 www.upi-semi.com . o N n i P e m a N n iPn o i t c n u F n i P A A DPB G DP8 U S P 162 1 N E 1 l e n n a h C r o f e l b a n E 1 l e n n a h c e h t n w o d s t u h s w o l c i g o L . ) h g i He v i t c A ( . r e t r e v n o c 247 1 B F . 1 l e n n a h C r o f e g a t l o V k c a b d e e Fro r r e e h t f o t u p n i g n i t r e v n i e h t s i n i p s i h T re d i v i d r o t s i s e r l a n r e t x e n a h g u o r h t t u p t u o r e h c t i w s e h t s e sn e s 1 B F . r e i f i l p m a . k r o w t e n 31 4 2 N I V . 2 l e n n a h C r o f t u p n I y l p p u Stu p t u o e h t o t t n e r r u c s e i l p p u s t a h t e g a t l o v t u p n I ah t i we g a t l o v t u p n i s s a p y B . t i u c r i c l o r t n o c l a n r e t n i e h t s r e w o p dn a e g a t l o v . r o t i c a p a c c i m a r e c R 7 X r o R 5 X F u 7 . 4m u m i n i m 9 /49 /3- -2 / 1 D N G . d n u o r G C f o l a n i m r e t e d o h t a c e h t o t y l t c e r i d n i p e h t s e i TIN Cd n aT U O d n a sa e b d l u o h s a e r a d a pD N Ge h T . e c n a d e p m i t s e w o l e h t h t i we n a l p d n u o r g d e i r u b e h t o t n i t a e h e h t t c u d n o c o t s a i v y n a mg n i s u d n a e l b i s s o p s a e g r a l kc a b d e e f d n a n o i t a s n e p m o c , l a n g i s - l l a m s l l A . r e y a l B C P f o e ta l pD N G . n i p s i h t o t t c e n n o c d l u o h s s t n e n o p m o c 525 2 X L . 2 l e n n a h C r o f t u p t u Os e h c t i w S l a n r e t n I tu p t u o e h t o t n i p s i h t t c e n n o C . r o t c u d n i 62 16 2 N E 2 l e n n a h C r o f e l b a n E 2 l e n n a h c e h t n w o d s t u h s w o l c i g o L . ) h g i He v i t c A ( . r e t r e v n o c 70 13 2 B F . 2 l e n n a h C r o f e g a t l o V k c a b d e e Fro r r e e h t f o t u p n i g n i t r e v n i e h t s i n i p s i h T re d i v i d r o t s i s e r l a n r e t x e n a h g u o r h t t u p t u o r e h c t i w s e h t s e sn e s 2 B F . r e i f i l p m a . k r o w t e n 878 1 N I V . 1 l e n n a h C r o f t u p n I y l p p u Stu p t u o e h t o t t n e r r u c s e i l p p u s t a h t e g a t l o v t u p n I ah t i we g a t l o v t u p n i s s a p y B . t i u c r i c l o r t n o c l a n r e t n i e h t s r e w o p dn a e g a t l o v . r o t i c a p a c c i m a r e c R 7 X r o R 5 X F u 7 . 4m u m i n i m 018 1 1 X L . 1 l e n n a h C r o f t u p t u Os e h c t i w S l a n r e t n I tu p t u o e h t o t n i p s i h t t c e n n o C . r o t c u d n i --1 1 /5- -C N . d e t c e n n o C y l l a n r e t n I t o N d a P d e s o p x E. d n u o r G ht i we n a l p d n u o r g o t d e r e d l o s l l e we b d l u o h s d a Pd e s o p x Ee h T . n o i t c u d n o c l a m r e h t e v i t c e f f e r o f s a i v e l p i t l u m Functional Pin Description

4 uP1784-DS-F0000, Oct. 2013 www.upi-semi.com The uP1784 contains two identical synchronous-rectified buck converters running in out of phase operation. With internal low RDS(ON) switches, each converter is capable of delivering 1.3A peak output current over a wide input voltage range from 2.6V to 5.5V. Fixed 1.5MHz operation allows possible smallest output ripple and external component size. With high conversion efficiency and small package, the uP1784 is ideally suitable for portable devices and USB/ PCIE-based interface cards where PCB area is especially concerned. The output voltage is adjustable from 0.6V to VIN by a voltage divider. Other features include internal soft- start, chip enable, under-voltage, over-temperature and over- current protections. Input Supply Voltage, VINX VIN1 and VIN2 supply currents to the internal control circuits and supply currents to the output voltages. The supply voltage range is from 2.6V to 5.5V. A power on reset (POR) continuously monitors the input supply voltage. The POR level is typically 2.5V at VIN rising. The uP1784 draws pulsed current with sharp edges each time the upper switch turns on, resulting in voltage ripples and spikes at supply input. A minimum 4.7uF ceramic capacitor with shortest PCB trace is highly recommended for bypassing the supply input. Chip Enable/Disable and Soft Start Pulling EN pin lower than 0.4V shuts down the uP1784 and reduces its quiescent current lower than 1uA. In the shutdown mode, both upper and lower switches are turned off. Pulling EN pin higher than 1.5V enables the uP1784 and initiates the soft start cycle. The uP1784 limits the in-rush current at start-up. This prevents unwanted shutdown otherwise may be triggered by voltage drop due to large inrush current. PWM Operation The uP1784 adopts slope-compensated, current mode PWM control capable of achieving 100% duty cycle. During normal operation, the uP1784 operates at PWM mode to regulate output voltage by transferring the power to the output voltage cycle by cycle at a constant 1.5MHz frequency. The uP1784 turns on the upper switch at each rising edge of the internal oscillator allowing the inductor current to ramp up linearly. The switch remains on until either the current-limit is tripped or the PWM comparator turns off the switch for regulating output voltage. The upper switch current is sensed, slope compensated and compared with the error amplifier output COMP to determine the adequate duty cycle. The VOUT pin senses output feedback voltage from an external resistive divider. When the load current increases, it causes a slight decrease in the feedback voltage relative to the 0.6V reference, which in turn, causes the error amplifier output voltage to increase until the average inductor current matches the new load current. The lower switch turns on with optimal deadtime and picks up the inductor current after the upper switch turns off, allowing the inductor current to ramp down linearly. The switch remains on until the next rising edge of oscillator turns on the upper switch. The uP1784 regulates the output voltage by controlling the ramp up/down duty cycle of inductor current. The high frequency switching ripple is easily smoothed by the output filter. A Pseudo Diode Emulator monitors inductor current by sensing voltage drop across the lower switch when it turns on. The lower switch acts a free wheel diode in an asynchronous buck converter when the inductor current is lower than 80mA. This allows the converter operating in discontinuous conduction mode (DCM) and reduces conduction loss and increase power conversion efficiency at light condition. PSM Operation A finite minimum on-time for both upper and lower switches is implemented for normal operation. Consequently, the converter will enter pulse-skipping mode (PSM) during extreme light load condition or when modulation index (VOUT / VIN) is extremely low. The equivalent switching frequency is reduced. This could reduce switching loss and further increase power conversion efficiency. Low Dropout Mode The uP1784 increases duty cycle to maintain output voltage within its regulation as the supply input drops gradually in the battery-powered applications. The uP1784 operates with 100% duty cycle and enters low dropout mode as the supply input approaches the output voltage. This maximizes the battery life. Current Limit Function The uP1784 continuously monitors the inductor current for current limit by sensing the voltage drop across the upper switch when it turns on. When the inductor current is higher than current limit threshold (1.4A typical), the current limit function activates and forces the upper switch to turn off to limit inductor current cycle by cycle. If the load continuously demands more current than what uP1784 could provide, uP1784 can not regulate the output voltage. Eventually under voltage protection will be triggered and shuts down the uP1784 if VOUT is too low. Functional Description

lower than 17% of its target level and shuts down uP1784. appropriate R1 according to required output voltage. Figure 1. Output Voltage Programming

6 uP1784-DS-F0000, Oct. 2013 www.upi-semi.com r e t e m a r aPl o b m ySs n o i t i d n o C t s eTn iMp yTx a M st i n U t n e r r u C y l p p u S t u o k c o L e g a t l o V r e d n U t u p nIV O L V U V N I g n i s ir6 .2- -- - V V N I g n i l l af- -- -2 t n e r r u C t n e c s e i uQI Q V N E V , V 3 . 3 =B F V >F E RI ,T U O , A m 0 = r e t r e v n o c h c a e , ) g n i h c t i w s o N (--0 60 01A u t n e r r u C n w o d t u hSI N D H SV N E V 0=- -1 0 .01 A u e c n e r e f e R e m i T t r a t S - t f oSn g i s e d y b d e e t n a r a uG- -0 52- -s u e g a t l o V e c n e r e f eRV B F I T U O A m 0 1=8 8 5 .06 .02 1 6 .0V t n e r r u C s a i B k c a b d e eFI B F n g i s e d yb0 3-- -0 3A n n o i t a l u g e R e n i L e g a t l o V t u p t u OΔV T U OV N I V 5 . 5 o t V 6 . 2=- -4 0 .04 .0V / % d a o L e g a t l o V t u p t u O n o i t a l u g e R ΔV T U OI T U O A m 0 0 0 1 o t 0 3=- -5 .0- -A / % (Note 1) Supply Input Voltage, VIN Storage Temperature Range ESD Rating (Note 2) (Note 4) (VIN = 3.3V, TA = 25O C, unless otherwise specified) Absolute Maximum Rating Thermal Information Recommended Operation Conditions

Electrical Characteristics

Package Thermal Resistance (Note 3) Power Dissipation, PD @ TA = 25O C

7uP1784-DS-F0000, Oct. 2013 www.upi-semi.com Note 1. Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. θJA is measured in the natural convection at TA = 25O C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 4. The device is not guaranteed to function outside its operating conditions. r e t e m a r aPl o b m ySs n o i t i d n o C t s eTn iMp yTx a M st i n U r o t a l l i c s O e s n e S t n e r r u C o t P M O C e c n a t c u d n o c s n a r T n g i s e d y b d e e t n a r a uG- -2- -V / A e g n a R y c n e u q e r F g n i h c t i wSf C S O 5 2 .15 .15 7 .1z H M e l c y C y t u Dm u m i x aMC DV N I V =T U OV ;B F V 5 5 . 0=0 01- -- -% s e h c t i w S r e w o P R ) N O ( S D h c t i w S r e p p U foR T E F _ PV N I I , V 3 . 3 =X L A m 0 0 1=- -0 03- -m Ω R ) N O ( S D h c t i w S r e w o L foR T E F _ NV N I I , V 3 . 3 =X L A m 0 0 1 -=- -0 52- -m Ω t u p n I c i g o L d l o h s e r h T w o L c i g o L NEV L I V N I n w o d t u h S , V 5 . 5 o t V 6 . 2=- -- -4 .0V d l o h s e r h T h g i H c i g o L NEV H I V N I e l b a n E , V 5 . 5 o t V 6 . 2=5 .1- -- -V n o i t c e t o r P n o i t c e t o r P e g a t l o V r e d n UB F Δ P V U _ B F g n i l l a F BF- -3 3 1 .0- -V n o i t c e t o r P t i m i L t n e r r uCI P C O _ T U O 3 .14 .1- -A e r u t a r e p m e T n o w d t u h S l a m r e hTT N D H S n g i s e d y b d e e t n a r a uG- -0 51- - O C s i s e r e t s y H n w o d t u h S l a m r e h TΔT N D H S n g i s e d y b d e e t n a r a uG- -0 2- - O C

8 uP1784-DS-F0000, Oct. 2013 www.upi-semi.com 1.14 1.16 1.18 1.20 1.22 1.24 1.26 VOUT (100mV/Div) LX (5V/Div) ILX(500mA/Div) Typical Operation Characteristics EN 5V/Div ILX 1A/Div VOUT 1V/Div LX 5V/Div EN 5V/Div ILX 1A/Div LX 5V/Div VOUT 1V/Div Power On from EN Time (100us/Div) VIN = 5V, VOUT = 1.2V, IOUT = 1A Power Off from EN Time (2us/Div) VIN = 5V, VOUT = 1.2V, IOUT = 1A Load Transient Time (100us/Div) VIN = 5V, VOUT = 1.2V, IOUT = 0A ~ 1A 1.48 1.49 1.50 1.51 1.52 1.53 1.54 1.55 1.56 Switching Frequency vs. Input Voltage Input Voltage (V) IOUT = 500mA Switching Frequency (MHz) Line Regulation VIN (V) Output Voltage Variation (%) Load Regulation IOUT (A) Output Voltage Variation (%) 1.15 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24

9uP1784-DS-F0000, Oct. 2013 www.upi-semi.com capacitance over temperature, they also become resistive at high frequencies. This reduces their ability to filter out high frequency noise. The capacitor with low ESR (equivalent series resistance) provides the small drop voltage to stabilize the input voltage during the transient loading. For input capacitor selection, the ceramic capacitors larger than 1uF is recommend. The capacitor must conform to the RMS current requirement. The maximum RMS ripple current is calculated as: IN OUTINOUT )MAX(OUT)RMS(IN V )VV (VII −××= This formula has a maximum at VIN = 2xVOUT , where IIN(RMS) = IOUT(MAX) /2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the capacitor manufacturer’s ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Always consult the manufacturer if there is any question. Output Capacitor Selection The uP1784 is specifically designed to operate with minimum 4.7uF X5R or X7R ceramic capacitor. The value can be increased to improve load/line transient performance. Y5V dielectrics, aside from losing most of their capacitance over temperature, they also become resistive at high frequencies. This reduces their ability to filter out high frequency noise. The ESR of the output capacitor determines the output ripple voltage and the initial voltage drop following a high slew rate load transient edge. The output ripple voltage can be calculated as: )Cf 8 1ESR(IV OUTOSC COUT ××+×Δ =Δ where fOSC = operating frequency, COUT = output capacitance and ΔIC = ΔIL = ripple current in the inductor. The ceramic capacitor with low ESR value provides the low output ripple and low size profile. Connect a 4.7uF ceramic capacitor at output terminal for good performance and place the input and output capacitors as close as possible to the device. Using Ceramic Capacitors Higher value, lower cost ceramic capacitors are now available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. Because the uP1784 control loop does not depend on the output capacitor’s ESR for stable operation, ceramic capacitors can be used to Output Inductor Selection Output inductor selection is usually based the considerations of inductance, rated current value, size requirements and DC resistance (DCR). The inductance is chosen based on the desired ripple current. Large value inductors result in lower ripple currents and small value inductors result in higher ripple currents. Higher VIN or VOUT also increases the ripple current as shown in the equation below. A reasonable starting point for setting ripple current is ΔIL = 400mA (40% of 1A). V1 (VLf IN OUT OUT OUTOSC L −×××=Δ For most applications, the value of the inductor will fall in the range of 1uH to 10uH. The output inductor is suggested as the table of suggested inductors for optimal performance. Maximum current ratings of the inductor are generally specified in two methods: permissible DC current and saturation current. Permissible DC current is the allowable DC current that causes 40O C temperature raise. The saturation current is the allowable current that causes 10% inductance loss. Make sure that the inductor will not saturate over the operation conditions including temperature range, input voltage range, and maximum output current. If possible, choose an inductor with rated current higher than 1.0A, so that it will not saturate even under current limit condition. The size requirements refer to the area and height requirement for a particular design. For better efficiency, choose a low DC resistance inductor. DCR is usually inversely proportional to size. Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends on the price vs. size requirements and any radiated field/EMI requirements. Table 1 shows some typical surface mount inductors that work well in uP1784 applications. Input Capacitor Selection The uP1784 draws pulsed current with sharp edges from the input capacitor resulting in ripple and noise at the input supply voltage. A minimum 1uF X5R or X7R ceramic capacitor is highly recommended to filter the pulsed current. The input capacitor should be placed as near the device as possible to avoid the stray inductance along the connection trace. Y5V dielectrics, aside from losing most of their Typical Operation Characteristics

achieve very low output ripple and small circuit size. if the junction temperature drops to 130O C. and high ambient temperatures. than its maximum rating 125O C. loop then acts to return VOUT to its steady state value. overshoot or ringing that would indicate a stability problem. guidelines for optimal performance of uP1784.

1 For the main current paths, keep their traces short,

2 Put the input/output capacitors as close as possible to

3 LX node is with high frequency voltage swing and should

LX node to prevent stray capacitive noise pick-up. 4 Connect feedback network behind the output capacitors.

5 A ground plane is preferred, but if not available, keep

should not share the high current path of CIN or COUT . 6 Flood all unused areas on all layers with copper.

7 An example of 2-layer PCB layout is shown in Figure

Figure 1. Top Layer Layout Example.

11uP1784-DS-F0000, Oct. 2013 www.upi-semi.com Note 1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm. WDFN3x3-12L Package

Package Information

0.70 - 0.80 0.15 - 0.280.45 BSC 2.90 - 3.10 2.90 - 3.10 1.30 - 1.80 0.00 - 0.050.20 REF

12 uP1784-DS-F0000, Oct. 2013 www.upi-semi.com Note 1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm. VDFN3x3-10L Package 0.80 - 1.00 0.18 - 0.300.50 BSC 2.90 - 3.10 2.90 - 3.10 1.40 - 1.80 0.00 - 0.050.20 REF

13uP1784-DS-F0000, Oct. 2013 www.upi-semi.com Note 1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm. 0.31 - 0.51 4.80 - 5.00 5.79 - 6.20 0.10 - 0.25 0.40 - 1.27

1.27 BSC

3.80 - 4.00 1.90 - 2.55 2.60 - 3.40 0.00 - 0.15

1.70 MAX

14 uP1784-DS-F0000, Oct. 2013 www.upi-semi.com Important Notice uPI and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. uPI products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment. However, no responsibility is assumed by uPI or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of uPI or its subsidiaries. COPYRIGHT ( C) 2011, UPI SEMICONDUCTOR CORP. uPI Semiconductor Corp. Headquarter 9F.,No.5, Taiyuan 1st St. Zhubei City, Hsinchu Taiwan, R.O.C. uPI Semiconductor Corp. Sales Branch Office 12F-5, No. 408, Ruiguang Rd. Neihu District, Taipei Taiwan, R.O.C.