UP1723PRUA

UP1723 UPI | Alldatasheet

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Technical content

Features

The uP1723 is a high-efficiency synchronous-rectified buck converter with internal power switch. With internal low RDS(ON) switches, the high-efficiency buck converter is capable of delivering 2A output current over a wide input voltage range from 4.5V to 18V. The output voltage is adjustable from 0.8V to 15V by a voltage divider. Other features for the buck converter include adjust soft-start, chip enable, over-voltage, under-voltage, over- temperature and over-current protections. It is available in a space saving SOP-8L, PSOP-8L, PMSOP-8L and PMSOP-10L packages. Note: (1) Please check the sample/production availability with uPI representatives. (2) uPI products are compatible with the current IPC/ JEDEC J-STD-020 requirement. They are halogen-free, RoHS compliant and 100% matte tin (Sn) plating that are suitable for use in SnPb or Pb-free soldering processes. SOP – 8L VIN LX BOOT GND COM P EN SS FB NC 1 5 6 PMSOP –10L VIN LX BOOT GND COMP EN SS FB NC GND GND PSOP – 8L VIN LX BOOT GND COM P EN SS FB PMSOP - 8L 4 5 VIN LX BOOT GND COM P EN SS FB GND Pin Configuration

2 uP1723-DS-P0001, Jan. 2015 www.upi-semi.com Typical Application Circuit BOOT FB COMP SS VIN 4.5V~18V VOUT VIN GND C IN 10uFx2 EN R 4 100K LX C SS 0.1uF C BOOT 10nF R 3 C 2 R 2 R 1 C OUT 22uFx2 C 3 Option C 1 Option R 5 V N I V T U O C N I 1LC T U O C 1 C 2 R1 R2 R3 V 21V 2 .12 x F u 01H u 2 .22 x F u 22F p 22F n 5 .1K 3K 01K 7 . 4 V 21V 3 .32 x F u 01H u 012 x F u 22F p 22F n 5 .1K 1 . 62K 01K 0 1 V 21V 52 x F u 01H u 512 x F u 22F p 22F n 5 .1K 2 . 44K 01K 3 1 e d o Mg n i v a S r e w oPe d o M r e w o P l l u F V N I 4R5 RN EV4 R5 RN E V V 5 .4k 0 01C NV 0 4 .4k 0 01k 0 81V 9 8 . 2 V 0 .5k 0 01C NV 0 8 .4k 0 01k 0 31V 2 8 . 2 V 0 .9k 0 01k 0 11V 1 7 .4k 0 01k 74V 7 8 . 2 V 21k 0 01k 26V 9 5 .4k 0 01k 03V 6 7 . 2 V 51k 0 01k 34V 1 5 .4k 0 01k 22V 0 7 . 2 BOM List for EN Pin Application: Note: * check BOM List for EN Pin Application table below.

3uP1723-DS-P0001, Jan. 2015 www.upi-semi.com . o N n i P e m a N n iPn o i t c n u F n i P/ 8 A S P / 8 U S P

8 U R P

--3 ,1C N . d e t c e n n o C l a n r e t n I t o N

12 T O O B

. r e v i r De t a G r e p p Ug n i t a o l F e h t r o f y l p p u Sp a r t s t o o B p a r t s t o o b e h t t c e n n o C C r o t i c a p a cT O O B e h T . t i u c r i c p a r t s t o o b am r o f o t n i p X L e h t d n a n i p T O O B n e e w t e b e u l a v l a c i p y T . T E F S O M r e p p u e h t n o n r u t o t e g r a h c e h t s e d i v o rp r o t i c a p a c p a r t s t o o b C r o fT O O B C t a h t e r u s n E . r e t a e r g r o F n 0 1 s iT O O B . C I e h t r a e n d e c a l p s i

24 N I V

t u p n I y l p p u S r e w o P d n a e g a t l o v t u p t u o e h t o t t n e r r u c s e i l p p u s t a h t e g a t l o v t u p nI . 2 x F u 0 1m u m i n i ma h t i w e g a t l o v t u p n i e h t s s a p y B . t i u c r i c l o r t n o c l a n r e t n i e ht s r e w o p . r o t i c a p a c c i m a r e c R 7 X r o R 5 X 35 X L . t u p t u O s e h c t i w S l a n r e t n I. r o t c u d n i t u p t u o e h t o t n i p s i h t t c e n n o C 46 D N G . d n u o r G . r e t r e v n o c k c u b e h t f o d n u o r G 57 B F . e g a t l o V k c a b d e e F r e h c t i w SB F . r e i f i l p m a r o r r e e h t f o t u p n i g n i t r e v n i e h t s i n i p s i h T . k r o w t e n r e d i v i d r o t s i s e r l a n r e t x e n a h g u o r h t t u p t u o r e h c ti w s e h t s e s n e s

68 P M O C

. n o i t a s n e p m o C ro t a r a p m o c t n e r r u c e h T . r e i f i l p m a r o r r e e h t f o t u p t u o s i n i p si h T ro f d n u o r g o t k r o w t e nC R n a t c e n n o C . e g a t l o v l o r t n o c s i h t h t i w s e s a e r c n i d l o h s e r ht . n o i t a s n e p m o c p o o l l o r t n o c 79 N E . ) h g i H e v i t c A ( e l b a n E r e t r e v n o C k c u B. r e t r e v n o c e h t n w o d s t u h s w o l c i g o L 80 1S S . n i P l o r t n o C t r a t S - t f o SC r o t i c a p a c t r a t s t f o s a t c e n n o CS S ro f n e p o e v a e L . n i p s i h t o t ni p N E n e h w d n u o r g o t d e g r a h c s i d s i r o t i c a p a c t r a t s t f o s e h T . no i t a c i l p p a t r a t s - t f o s o n . w o l s i d a P d e s o p x E. d n u o r G . r e t r e v n o c k c u b e h t f o d n u o r G Functional Pin Description Functional Block Diagram SS Control Logic Protect Logic Driver Current Sense Current Limit Detector Slope Compensation VREF GND VIN LX FB 6uA COMP BOOT Internal Regulator VAVCC VA 1.1V 0.4V OV UV VREF OTP OT EN Logic EN EN PORPOR POR

temperature and over-current protections. recommended for bypassing the supply input. power mode by pulling EN pin between 2.4V and 3V. Table 1. Mode Table Selection Figure 1. uP1723 Soft Start easily smoothed by the output filter. get appropriate COMP pin voltage. matches the new load current. therefore enhances total efficiency of the buck converter.

5uP1723-DS-P0001, Jan. 2015 www.upi-semi.com Functional Description Output Voltage Setting and Feedback Network For the adjustable output version, the output voltage can be set from VREF to VIN by a voltage divider as: 2 R 2 R1 R925. 0VOUT +×= The internal VREF is 0.925V with 1.5% accuracy. In real applications, a 22pF feed-forward ceramic capacitor is recommended in parallel with R1 for better transient response. Over Temperature Protection The OTP is triggered and shuts down the uP1723 if the junction temperature is higher than 150O C. The OTP is a non-latch type protection. The uP1723 automatically initiates another soft start cycle if the junction temperature drops below 120O C. Current Limit Function The uP1723 continuously monitors the inductor current for current limit by sensing the voltage drop across the upper switch when it turns on. When the inductor current is higher than current limit threshold (4A typical), the current limit function activates and forces the upper switch turning off to limit inductor current cycle by cycle. If the load continuously demands more current than what uP1723 could provide, uP1723 will not be able to regulate the output voltage, and the output voltage will drop accordingly. Eventually, under voltage protection will be triggered if VFB is lower than UVP threshold. When the output is shorted to ground, the current limit function activates immediately, and VOUT will be pulled down very fast. Eventually the under voltage protection will be triggered, and the IC will shut down to protect external components. The IC will restart after the UVP retry delay, and the above behavior may repeat if the output short condition is not released. This is the so-called Short Circuit Protection (SCP). Under Voltage Protection The uP1723 continuously monitors FB voltage for under voltage protection. When VFB < 0.4V (typical), the uP1723 triggers under voltage protection and enters frequency decay mode which the switching frequency of the uP1723 will decrease linearly according to the FB voltage drop. Eventually when VFB = 0V, the switching frequency of the uP1723 will be clamped at 100kHz. After triggering UVP , the SS voltage is also discharged to 0V. After VSS = 0V, the uP1723 will try to re-soft-start to establish the output voltage once again. In the end of re-soft-start (VSS = 1.2V), if the UVP condition is still not relieved, the uP1723 will turn-off all high-side and low-side MOSFETs and re-try to soft start every 8ms. Over Voltage Protection The uP1723 continuously monitors FB voltage for over voltage protection. When VFB > 1.1V (typical), the uP1723 triggers over voltage protection and the low-side MOSFET is turned on while high-side MOSFET is turned off to discharge the output voltage. At any time if the OVP condition is relieved, the uP1723 will restart the soft start sequence.

6 uP1723-DS-P0001, Jan. 2015 www.upi-semi.com (Note 1) Supply Input Voltage, VIN LX Pin Voltage ESD Rating (Note 2) (Note 5) Absolute Maximum Rating Thermal Information Recommended Operation Conditions Package Thermal Resistance (Note 3/4) Power Dissipation, PD @ TA = 25O C

Electrical Characteristics

(VIN = 12V, TA = 25O C, unless otherwise specified) r e t e m a r aPl o b m ySs n o i t i d n o C t s eTn iMp yTx a M st i n U t u p n I y l p p u S d l o h s e r h T R O PN IVV H T R N I 8 .32 .45 .4V s i s e r e t s y HR O PN IVV S Y H N I --2 3 .0- -V t n e r r u C t n e c s e i uQV N E V , V 5 =B F g n i h c t i w s o n , V 1=- -8 .02 .1A m t n e r r u C n w o d t u hSI D S V N E 0=- -5 .03 A u

7uP1723-DS-P0001, Jan. 2015 www.upi-semi.com Note 1. Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. qJA is measured in the natural convection at TA = 25O C on a low effective thermal conductivity test board of JEDEC 51-7 thermal measurement standard. Note 4. The “case temperature” location for measuring θJC is on the top of the package. Note 5. The device is not guaranteed to function outside its operating conditions. r e t e m a r aPl o b m ySs n o i t i d n o C t s eTn iMp yTx a M st i n U e g a t l o V k c a b d e e F e g a t l o V k c a b d e eFV B F V < V 5 . 4N I V 8 1<1 1 9 .05 2 9 .09 3 9 .0V e c n a t c u d n o c s n a r T r e i f i l p m A r o r rEA E G ∆ A u 0 1 - / + =CI- -0 49- -V / A u e c n a t c u d n o c s n a r T e s n e S t n e r r u C o t P M OCS CG- -4- -V / A s e h c t i w S r e w o P e c n a t s i s e R n O h c t i w S e d i S - e d iHR ) N O ( S D --0 31- -m Ω e c n a t s i s e R n O h c t i w S e d i S - w oLR ) N O ( S D --0 31- -m Ω t n e r r u C e g a k a e L h c t i w S e d i S h g iHI N E V N E V , 0 =W S 0=- -00 1A u t i m i L t n e r r u C h c t i w S e d i S r e p p U--4- -A r o t a l l i c s O y c n e u q e r F n o i t a l l i c sOf 1 C S O 0 030 430 83z H k y c n e u q e r F n o i t a l l i c s O t i u c r i C t r o hSf 2 C S O --0 01- -z H k e l c y C y t u Dm u m i x aMD X A MV B F V 7 . 0=- -3 9- -% e m i T n Om u m i n iMT N O --0 31- -s n e l b a n E h g i H c i g o L NEV N E g n i s ir4 .2- -5 .5V w o L c i g o L NEV N E g n i l l af- -- -2 .1V d l o h s e r h T y r t n E r e w o P l l uFV N E g n i s ir4 .2- -3 V d l o h s e r h T y r t n E g n i v a S r e w oPV N E g n i s ir8 .3- -5 .5V t r a t S t f o S t n e r r u C t r a t S t f oSI S S V S S V 0=5 .565 .6A u t c e t o r P t c e t o r P e g a t l o V r e d nUg n i l l a f BF- -4 .0- -V t c e t o r P e g a t l o V r e vOg n i s i r BF- -1 .1- -V e r u t a r e p m e T n w o d t u h S l a m r e hTT D S --0 51- - OC s i s e r e t s y H n w o d t u h S l a m r e hTT S Y H D S --0 3- - OC

8 uP1723-DS-P0001, Jan. 2015 www.upi-semi.com VIN (10V/Div) ILX (2A/Div) VOUT (10mV/Div) LX (10V/Div) VIN (10V/Div) LX (10V/Div) VOUT (10mV/Div) ILX (100mA/Div) EN (5V/Div) ILX (2A/Div) VOUT (2V/Div) LX (10V/Div) EN (5V/Div) ILX (2A/Div) VOUT (2V/Div) LX (10V/Div) VIN (5V/Div) ILX (2A/Div) VOUT (2V/Div) LX (10V/Div) VIN (5V/Div) ILX (2A/Div) VOUT (2V/Div) LX (10V/Div) Typical Operation Characteristics Power On Waveforms 4ms/Div VIN = 12V, VOUT = 3.3V, IOUT = 2A Power Off Waveforms 20ms/Div VIN = 12V, VOUT = 3.3V, IOUT = 2A Turn On Waveforms 4ms/Div VIN = 12V, VOUT = 3.3V, IOUT = 2A Turn Off Waveforms 400us/Div VIN = 12V, VOUT = 3.3V, IOUT = 2A Steady State Waveforms 100us/Div VIN = 12V, VOUT = 3.3V, IOUT = 0A at PSM Steady State Waveforms 2us/Div VIN = 12V, VOUT = 3.3V, IOUT = 2A at PSM

9uP1723-DS-P0001, Jan. 2015 www.upi-semi.com 3.20 3.25 3.30 3.35 3.40 100 0.01 0.1 1 10 VIN = 12V VIN = 5V LX (10V/Div) ILX (2A/Div) IOUT (2A/Div) VOUT (2V/Div) VOUT (100mV/Div) LX (10V/Div) IOUT (2A/Div) VIN (10V/Div) Load Transient Waveforms 200us/Div VIN = 12V, VOUT = 3.3V, IOUT = 0A Current Limit Waveforms 100us/Div VIN = 12V, VOUT = 3.3V, IOUT = 2A Typical Operation Characteristics Output Voltage vs. Output Current Output Current (A) VIN = 12V, VOUT = 3.3V, IOUT = 0A ~ 2A Output Voltage (V) Efficiency vs. Output Current Output Current (A) VIN = 5V ~ 12V, VOUT = 3.3V, IOUT = 0A ~ 2A Efficiency (%)

10 uP1723-DS-P0001, Jan. 2015 www.upi-semi.com

Application Information

Output inductor selection is usually based the considerations of inductance, rated current value, size requirements and DC resistance (DCR). The inductance is chosen based on the desired ripple current. Large value inductors result in lower ripple currents and small value inductors result in higher ripple currents. Higher VIN or VOUT also increases the ripple current as shown in the equation below. A reasonable starting point for setting ripple current is ∆IL = 900mA (30% of 3000mA). For most applications, the value of the inductor will fall in the range of 1uH to 10uH. ()  IN OUT OUT OUTOSC V V1VLf 1IL Maximum current ratings of the inductor are generally specified in two methods: permissible DC current and saturation current. Permissible DC current is the allowable DC current that causes 40O C temperature raise. The saturation current is the allowable current that causes 10% inductance loss. Make sure that the inductor will not saturate over the operation conditions including temperature range, input voltage range, and maximum output current. If possible, choose an inductor with rated current higher than 4.3A so that it will not saturate even under current limit condition. The size requirements refer to the area and height requirement for a particular design. For better efficiency, choose a low DC resistance inductor. DCR is usually inversely proportional to size. Different core materials and shapes will change the size, current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends on the price vs. size requirements and any radiated field/EMI requirements. Input Capacitor Selection The buck converter draws pulsed current with sharp edges from the input capacitor resulting in ripple and noise at the input supply voltage. A minimum 10uFx2 X5R or X7R ceramic capacitor is highly recommended to filter the pulsed current. The input capacitor should be placed as near the device as possible to avoid the stray inductance along the connection trace. Y5V dielectrics, aside from losing most of their capacitance over temperature, they also become resistive at high frequencies. This reduces their ability to filter out high frequency noise. The capacitor with low ESR (equivalent series resistance) provides the small drop voltage to stabilize the input voltage during the transient loading. For input capacitor selection, the ceramic capacitor larger than 10uFx2 is recommend. The capacitor must conform to the RMS current requirement. The maximum RMS ripple current is calculated as: OUTOSC COUT Cf8 1ESRIV This formula has a maximum at VIN = 2xVOUT , where IIN(RMS) = IOUT (MAX)/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the capacitor manufacturer’s ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Always consult the manufacturer if there is any question. Using Ceramic Capacitors Higher value, lower cost ceramic capacitors are now available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. Because the control loop does not depend on the output capacitor’s ESR for stable operation, ceramic capacitors can be used to achieve very low output ripple and small circuit size. However, care must be taken when these capacitors are used at the input and the output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN, large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (∆IOUT x ESR), where ESR is the effective series resistance of COUT . ∆IOUT also begins to discharge or charge C OUT , which generates a feedback error signal. The regulator loop then acts to return VOUT to its steady state value. During this recovery time VOUT can be monitored for overshoot or ringing that would indicate a stability problem.

11uP1723-DS-P0001, Jan. 2015 www.upi-semi.com PCB Layout Considerations High switching frequencies and relatively large peak currents make the PCB layout a very important part of switching mode power supply design. Good design minimizes excessive EMI on the feedback paths and voltage gradients in the ground plane, both of which can result in instability or regulation errors. Follow the PCB layout guidelines for optimal performance of uP1723.

1 For the main current paths, keep their traces short,

direct and wide.

2 Put the input/output capacitors as close as possible to

the device pins.

3 LX node is with high frequency voltage swing and

should be kept small area. Keep analog components away from LX node to prevent stray capacitive noise pick-up.

4 Connect feedback network behind the output

capacitors. Place the feedback components near the uP1723 and keep the loop area small. .

5 A ground plane is preferred, but if not available, keep

the signal and power grounds separated with small signal components returning to the GND pin at one point. They should not share the high current path of C IN or COUT . 6 Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. These copper areas should be connected to VIN or GND.

7 An example of 2-layer PCB layout is shown in Figure

1 for reference. GND Via to BOOT Via to CBOOT Via to GND VIN Plane VOUT Plane Figure 1. Top Layer Layout Example.

12 uP1723-DS-P0001, Jan. 2015 www.upi-semi.com

Package Information

1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm. SOP - 8L 0.31 - 0.51 4.80 - 5.00 5.80 - 6.20 0.10 - 0.25 0.10 - 0.25 0.40 - 1.27

1.27 BSC

3.80 - 4.00

1.75 MAX

13uP1723-DS-P0001, Jan. 2015 www.upi-semi.com 1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm. PSOP - 8L 0.31 - 0.51 4.80 - 5.00 5.79 - 6.20 0.10 - 0.25 0.40 - 1.27 3.80 - 4.00 1.80 - 2.40 1.80 - 2.40 0.00 - 0.15

1.7 MAX

14 uP1723-DS-P0001, Jan. 2015 www.upi-semi.com 0.22 - 0.38 0.00 - 0.15 0.08-0.23 0.40 - 0.80

0.65 BSC

1.10 MAX

1.40 - 2.15 1.30 - 1.90 2.90 - 3.10 4.80 - 5.00 2.90 - 3.10 1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm. PMSOP - 8L

15uP1723-DS-P0001, Jan. 2015 www.upi-semi.com 1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm. PMSOP-10L 0.17-0.33 4.80 - 5.00 0.00 - 0.15 0.08-0.23 0.40 - 0.80

0.50 BSC

2.90 - 3.10 2.90 - 3.10 1.40-1.90 1.70 - 2.10

16 uP1723-DS-P0001, Jan. 2015 www.upi-semi.com Important Notice uPI and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. uPI products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment. However, no responsibility is assumed by uPI or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of uPI or its subsidiaries. COPYRIGHT ( C ) 2011, UPI SEMICONDUCTOR CORP. uPI Semiconductor Corp. Headquarter 9F.,No.5, Taiyuan 1st St. Zhubei City, Hsinchu Taiwan, R.O.C. uPI Semiconductor Corp. Sales Branch Office 12F-5, No. 408, Ruiguang Rd. Neihu District, Taipei Taiwan, R.O.C.