UP1605

UP1605 UPI | Alldatasheet

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Technical content

Features

Note: uPI products are compatible with the current IPC/ JEDEC J-STD-020 requirement. They are halogen-free, RoHS compliant and 100% matte tin (Sn) plating that are suitable for use in SnPb or Pb-free soldering processes.

2 uP1605-DS-F0000, Jun. 2012 www.upi-semi.com Typical Application Circuit uP1605 VCC CSP CSN PH1 PH2 PSI VREF IOFS REFIN FB COMP FBRTN PVCC EAP RT/EN SS GND VIN VOUTVOUT RSET VID FBRTN BOOT1 HG1 SW1 LG1 BOOT2 HG2 SW2 LG2

3uP1605-DS-F0000, Jun. 2012 www.upi-semi.com .oNe maNniPn oitcnuFniP 1N IFER .tupnIecnerefeRlanretxE redividegatlovatcennoC.egatlovecnereferlanretxefoniptupnisisihT .egatlovecnereferehttesotNTRBFotNIFERotFERVmorf 2F ERV .egatloVecnerefeRroftuptuO .egatlovecnereferV2noisicerphgihfoniptuptuoehtsisihT .NTRBFotroticapaccimarecFu1ahtiwnipsihtssapyB 3N E/TR .gnitteSycneuqerFnoitarepO ehttesotDNGdnanipsihtneewtebrotsiseragnitcennoC .5061PuehtnwodtuhsotdnuorgotnipsihtlluP.ycneuqerfnoitarepo 4S FOI .tnemtsujdAecnalaBtnerruC ehttsujdaotDNGroFERVotnipsihtmorfrotsiseratcennoC .gnirahstnerruc 5P MOC .tuptuOreifilpmArorrE fotupnignitrevni-nonehtdna)AE(reifilpmarorreehtfotuptuoehtsisihT -egatlovehtetasnepmocotnipBFehthtiwnoitanibmocninipsihtesU.srotarapmocMWPeht .retrevnocehtfopoolkcabdeeflortnoc 6B F .egatloVkcabdeeF noitanibmocninipsihtesU.reifilpmarorreehtottupnignitrevniehtsinipsihT .retrevnocehtfopoolkcabdeeflortnocegatlovehtetasnepmocotnipPMOCehthtiw 7N TRBF .nruteRkcabdeeF .detalugerebotsiegatlovtuptuoehterehwnipdnuorgehtotnipsihttcennoC 8P AE .reifilpmArorrEfotupnIgnitrevnI-noN .epolspoordehttesotnipSSotrotsiseratcennoC 9S S .tuptuOtratStfoS .lavretnitratstfosehttesotNTRBFotroticapacatcennoC 01N SC .reifilpmAgnisneStnerruCroftupnIevitageN 11P SC .reifilpmAgnisneStnerruCroftupnIevitisoP 21I SP .edoMgnivaSrewoP dlohserhtedomgnivasrewopehttesotDNGotISPmorfrotsiseratcennoC dnuorgotnipsihttrohS.noitarepoesahpowtsyawlarofFERVotnipsihttcennoC.leveltnerruc .noitarepoesahpelgnissyawlarof 311 TOOB ylppuSpartstooB roticapacpartstoobehttcennoC.1lennahcforevirdetagreppugnitaolfehtrof C TOOB .tiucricpartstoobamrofotnip1WSehtdnanip1TOOBneewteb 411 GH .1lennahCroftuptuOrevirDetaGreppU sihT.TEFSOMreppufoetagehtotnipsihttcennoC reppuehtnehwenimretedotyrtiucricnoitcetorphguorht-toohsevitpadaehtybderotinomsinip .ffodenrutsahTEFSOM 511 WS .1lennahCrofedoNhctiwS niardehtdnaTEFSOMreppuehtfoecruosehtotnipsihttcennoC derotinomoslasinipsihT.revirdETAGUehtrofknisehtsadesusinipsihT.TEFSOMrewolehtfo denrutsahTEFSOMreppuehtnehwenimretedotyrtiucricnoitcetorphguorht-toohsevitpadaehtyb .ffo 611 GL .1lennahCroftuptuOrevirDetaGrewoL sihT.TEFSOMrewolfoetagehtotnipsihttcennoC rewolehtnehwenimretedotyrtiucricnoitcetorphguorht-toohsevitpadaehtybderotinomsinip .ffodenrutsahTEFSOM 71C CVP .revirDetaGrofegatloVylppuS tnerrucsaibgnidivorprofODLV9lanretnifotuptuoehtsinipsihT etagehtetarepodnaODLehtssapybotyltceridCCVotCCVPtcennoC.srevirdetaglanretnirof gniretlifyllacolrofderiuqersiroticapaccimarecFu1muminimA.egatlovylppusV21htiwsrevird .CCVPeht 81C CV .egatloVylppuS nipsihtssapyB.ODLV9dnatiucriclortnoclanretniroftnerrucsedivorpnipsihT .CIehtottxenroticapaccimarecFu1muminimahtiw Functional Pin Description

4 uP1605-DS-F0000, Jun. 2012 www.upi-semi.com Functional Block Diagram .oNe maNniPn oitcnuFniP 912 GL .2lennahCroftuptuOrevirDetaGrewoL sihT.TEFSOMrewolfoetagehtotnipsihttcennoC rewolehtnehwenimretedotyrtiucricnoitcetorphguorht-toohsevitpadaehtybderotinomsinip .ffodenrutsahTEFSOM 022 WS .2lennahCrofedoNhctiwS ehtdnaTEFSOMreppuehtfoecruosehtotnipsihttcennoC oslasinipsihT.revird2GHehtrofknisehtsadesusinipsihT.TEFSOMrewolehtfoniard reppuehtnehwenimretedotyrtiucricnoitcetorphguorht-toohsevitpadaehtybderotinom .ffodenrutsahTEFSOM 122 GH .2lennahCroftuptuOrevirDetaGreppU .TEFSOMreppufoetagehtotnipsihttcennoC ehtnehwenimretedotyrtiucricnoitcetorphguorht-toohsevitpadaehtybderotinomsinipsihT .ffodenrutsahTEFSOMreppu 222 TOOB ylppuSpartstooB partstoobehttcennoC.2lennahcforevirdetagreppugnitaolfehtrof Croticapac TOOB .tiucricpartstoobamrofotnip2WSehtdnanip2TOOBneewteb 32D IV .tupnIDIV TEFSOMlanretniehtnosnruthgihcigoL.egatlovecnerefertsujdaotdesusinipsihT .nipTESRotdetcennoc 42T ESR .gnitteSegatloVecnerefeR .hgih=DIVnehwwoldellupsitahttuptuoniardneponasinipsihT .egatlovecnereferehttesotnipNIFERotnipsihtmorfrotsiseratcennoC daPdesopxE DNG .dnuorGrewoP iT noitcennocecnadepmitsewolehthguorhtenalp/dnalsidnuorgehtotnipsihte .elbaliava Functional Pin Description Gate Control Logic PWM2 Amplifier Error Oscillator PWM1 Current Balance VREF BOOT1 HG1 SW1 LG1 BOOT2 HG2 SW2 LG2 Reference Voltage VCC REFIN PVCC Internal Regulator Gate Control Logic POR SS FBRTN EAP FB COMP CSN CSP PSI VID RSET IOFS RT/EN GND Power Saving Setting

9uP1605-DS-F0000, Jun. 2012 www.upi-semi.com A15I k80m2 k22V6.0I RDCRIV6.0 OUT OUT CSN PSIOUT Ω×Ω Ω××= ××= Note that when operated in single phase, the rated current is reduced to 80 percents of normal level. Continuous demanding high current may damage the converter. Connect PSI pin to VREF to disable the automatic phase reduction function. Since the VREF has no sinking capability, make sure the external loading is higher than 100uA when connecting PSI pin to VREF. Otherwise, VREF may loss its regulation. Over Voltage and Under Voltage Protection The FB voltage is continuously monitored for over voltage and under voltage protection. The uP1605 asserts over voltage protection if V FB > VSS + 300mV and turns on the lower MOSFETs and shuts down the converter. The uP1605 asserts under voltage protection if V FB < VSS - 300mV and shuts down the converter. The UVP function is disabled during soft start. Both UVP and OVP are latch-off type and can be reset only by toggling the RT/EN pin ro by VCC power on reset. Functional Description

10 uP1605-DS-F0000, Jun. 2012 www.upi-semi.com retemaraPl obmySs noitidnoCtseTn iMp yTx aM stinU tupnIylppuS egatloVylppuSV CC 8.01- -2 .31V tnerruCylppuSI CC V;nepOGLdnaGH CC ,V21= gnihctiwS 357 A m tnerruCylppuStnecseiuQI Q_CC I,gnihctiwSoN CCP Am0=2 4 6 A m egatloVylppuSdetalugeRV CCP I,V0=NE/TR CCP Am0=8 9 0 1V dlohserhTROPV HTRCC 89 0 1V siseretsyHROPV SYHCC --8 .0- -V Absolute Maximum Rating Thermal Information Recommended Operation Conditions

Electrical Characteristics

(VCC = 12V, TA = 25OC, unless otherwise specified) (Note 1) SWx to GND BOOTx to GND UGx to SWx LGx to GND ESD Rating (Note 2) Package Thermal Resistance (Note 3) Power Dissipation, PD @ TA = 25°C (Note 4)

11uP1605-DS-F0000, Jun. 2012 www.upi-semi.com retemaraPl obmySs noitidnoCtseTn iMp yTx aM stinU gnitteSycneuqerF/elbanEpihC tnerruCgnicruoSNE/TRI NE/TR .DNG=NE/TR- -0 12- -A u egatloVNE/TRV NE/TR R NE/TR k33= Ω 49.01 6 0.1V egnaRgnitteSycneuqerFgnihctiwS 05- -0 001z Hk ycneuqerFgnihctiwSnuReerFf CSO R NE/TR k33= Ω 0720 030 33z Hk ycaruccAycneuqerFgnihctiwS Δf CSO f CSO zHk005~zHk002=5 1-- -5 1% tratStfoS tnerruCtratStfoS I SS .tratstfosgniruD6 10 24 2 Au I SS .dnetratstfosretfA0 610 120 72 egatloVpUtooBV TOOB .ngisedybdeetnarauG,P5061Purof8 81.12 .12 12.1 V .ngisedybdeetnarauG,Q5061Purof1 98.09 .09 09.0 emiTpUdloHpUtooBT C .ngisedybdeetnarauG6 .02 .18 .1s m rotallicsO elcyCytuDmumixaM 085 80 9% elcyCytuDmuminiM --0- -% edutilpmApmaR ΔV CSO V CC .V21=3 5 .34 V edoMgnivaSrewoP lauDgniretnErofegatloVdlohserhT esahP V ISP V ISP .gnisir5 5.06 .05 6.0V gniretnErofegatloVsiseretsyH esahPelgniS ΔV ISP V ISP .gnillaf- -0 02- -V m egatloVecnerefeR ycaruccAegatloVecnerefeRV FER I FER Au001=8 9.10 0.22 0.2V noitalugeRdaoLegatloVecnerefeR ΔV FER I FER Am2~0=5 -- -5V m ycaruccAegatloVtuptuOV BF V NIFER V- BF V, CC ,daoLoN,V21= R PRD 0= Ω V, NIFER .V6.1~V8.0= 2-0 2V m reifilpmArorrE niaGCDpooLnepOO A. ngisedybdeetnarauG0 70 8- -B d tcudorPhtdiwdnaB-niaGW BGC DAOL .ngisedybdeetnarauG,Fp5=0 2- -- -z HM etaRwelSR S. ngisedybdeetnarauG5 10 2- -s u/V )ecruoS&kniS(tnerruCmumixaMI PMOC V PMOC V6.1=5 .10 .2- -A m esneStnerruClatoT tnerruCgnicruoSmumixaMI XAM_NSC 001- -- -A u tesffOreifilpmAMG 1-0 1V m dlohserhTnoitcetorPtnerruCrevO leveL I PCO_NSC 550 65 6A u ycaruccApoorDI PRD I/ NSC 090 010 11% ycaruccAISPI ISP I/ NSC 090 010 11%

12 uP1605-DS-F0000, Jun. 2012 www.upi-semi.com retemaraPl obmySs noitidnoCtseTn iMp yTx aM stinU esneStnerruCesahP ecnatcudnoc-snarT --0 .1- -S m egatloVSFOI V SFO k001 Ω FERVotSFOImorf5 4.15 .15 5.1 V k001 Ω DNGotSFOImorf5 4.05 .05 5.0 tupnIlortnoCDIV leveLdlohserhThgiHcigoLV LI 2- -- -V leveLdlohserhTwoLcigoLV LI --- -4 .0V TEFSOMTESRfoecnartsiseRnOR TESR hgiH=DIV0 10 20 4 Ω niPTESRfoegakaeLI TESR V TESER V0=DIV,V2=- -- -1 .0A u revirDetaG gnicruoSetaGreppUR CRS_GH I GH gnicruosAm001=- -3 6 Ω gnikniSetaGreppUR KNS_GH I GH gniknisAm001=- -2 4 Ω ecruoSetaGrewoLR CRS_GL I GL gnicruosAm001=- -5 .25 Ω kniSetaGrewoLR KNS_GL I GL gnikgnisAm001=- -3 .16 .2 Ω emiTdaeDT TD --0 3- -s n noitcetorP noitcetorPegatloVrevOV BF V- SS 0520 030 53V m noitcetorPegatloVrednUV BF V- SS 053-0 03-0 52-V m noitcetorPerutarepmeTrevO --0 51- - OC siseretsyHerutarepmeTrevO --0 2- - OC Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 4. The device is not guaranteed to function outside its operating conditions.

13uP1605-DS-F0000, Jun. 2012 www.upi-semi.com Typical Operation Characteristics PH1 (10V/Div) RT/EN (1V/Div) SS (1V/Div) VOUT (1V/Div) PH1 (10V/Div) RT/EN (1V/Div) SS (1V/Div) VOUT (1V/Div) PH1 (10V/Div) RT/EN (1V/Div) SS (1V/Div) VOUT (1V/Div) PH1 (10V/Div) RT/EN (1V/Div) SS (1V/Div) VOUT (1V/Div) PH1 (10V/Div) RT/EN (1V/Div) SS (1V/Div) VOUT (1V/Div) Power Off Waveforms Time (200us/Div) VIN = 12V, IOUT = 40A Power On Waveforms Time (2ms/Div) VIN = 12V, VOUT = 1.2V, IOUT = 40A Turn On Waveforms Time (200us/Div) VIN = 12V, VOUT = 1.2V, IOUT = 40A Turn Off Waveforms Time (100us/Div) VIN = 12V, IOUT = 40A PSI (1V/Div) PH2 (10V/Div) PH1 (10V/Div) PSI Function Time (2ms/Div) VIN = 12V, IOUT = 0A to 40A Turn On Waveforms Time (400us/Div) VIN = 12V, VOUT = 1.0V, IOUT = 40A

14 uP1605-DS-F0000, Jun. 2012 www.upi-semi.com 1.95 1.96 1.97 1.98 1.99 2.01 2.02 2.03 2.04 2.05 6 7 8 9 10 11 12 13 14 Typical Operation Characteristics FB (1V/Div) LG1 (10V/Div) PH1 (10V/Div) PSI (1V/Div) PH2 (10V/Div) PH1 (10V/Div) VOUT (1V/Div) Over Current Protection Time (20us/Div) Over Voltage Protection Time (2us/Div) VREF Load Regulation Loading Current (mA) VREF Variation (%) -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0.05 0.1 0.15 0.2 0 5 10 15 20 VREF Line Regulation Input Voltage (V) VREF Voltage (V) UG1 ( 5V/Div) LG1 (5V/Div) PH1 (5V/Div) UG1 ( 5V/Div) LG1 (5V/Div) PH1 (5V/Div) UG1 Falling Waveforms Time (40ns/Div) VIN = 12V, IOUT = 40A, 20MHz Bandwidth Limited UG1 Rising Waveforms Time (40ns/Div) VIN = 12V, IOUT = 40A, 20MHz Bandwidth Limited

15uP1605-DS-F0000, Jun. 2012 www.upi-semi.com 290 292 294 296 298 300 302 304 306 308 310 -50 -25 0 25 50 75 100 125 1.95 1.96 1.97 1.98 1.99 2.01 2.02 2.03 2.04 2.05 - 5 0- 2 5 0 2 5 5 0 7 51 0 0 1 2 5 100 1000 11 0 1 0 0 Typical Operation Characteristics Frequency vs. RT RT (kΩ) Frequency (kHz) Efficiency vs. Output Current with Auto PSI Output Current (A) Efficiency (%) VCC9 Voltage vs. Tempereture Junction Temperature (OC) VCC9 Voltage (V) VREF Voltage vs. Temperature Junction Temperature (OC) VREF Voltage (V) 100 0 1 02 03 04 05 06 07 0

1 Phase

2 Phase

9.27 9.28 9.29 9.3 9.31 9.32 9.33 -50 -25 0 25 50 75 100 125 Switching Frequency vs. Tempereture Junction Temperature (OC) Switching Frequency (kHz) 6789 1 0 1 1 1 2 1 3 1 4 VCC9 Line Regulation Input Voltage (V) VCC9 Voltage (V)

17uP1605-DS-F0000, Jun. 2012 www.upi-semi.com OSCUP_RSSINLO_ISSUP_ISSCCCCC_G f)CV)CC(V(VP ××++××= where C ISS_UP is the input capacitance of the upper MOSFET, CISS_LOW is the input capacitance of the lower MOSFET, and CRSS_UP is the reverse transfer capacitance of the upper MOSFET. Make sure that the gate-charge loss will not cause over temperature at uP1605, especially with large gate capacitance and high supply voltage. Output Inductor Selection Output inductor selection usually is based on the considerations of inductance, rated current, size requirements and DC resistance (DCR). Given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: V1(VLf IN OUT OUT OUTOSC L −×=Δ Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Highest efficiency operation is obtained at low frequency with small ripple current. However, achieving this requires a large inductor. There is a tradeoff between component size, efficiency and operating frequency. A reasonable starting point is to choose a ripple current that is about 20% of I OUT(MAX). There is another tradeoff between output ripple current/ voltage and response time to a transient load. Increasing the value of inductance reduces the output ripple current and voltage. However, the large inductance values reduce the converter’s response time to a load transient. Maximum current ratings of the inductor are generally specified in two methods: permissible DC current and saturation current. Permissible DC current is the allowable DC current that causes 40 OC temperature raise. The saturation current is the allowable current that causes 10% inductance loss. Make sure that the inductor will not saturate over the operation conditions including temperature range, input voltage range, and maximum output current. The size requirements refer to the area and height requirement for a particular design. For better efficiency, choose a low DC resistance inductor. DCR is usually inversely proportional to size. Input Capacitor Selection The synchronous-rectified Buck converter draws pulsed current with sharp edges from the input capacitor, resulting in ripples and spikes at the input supply voltage. Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time upper MOSFET turns on. Place the small ceramic capacitors physically close to the MOSFETs to avoid the stray inductance along the connection trace. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck converter is calculated as: IN OUTINOUT )MAX(OUT)RMS(IN V )VV(VII −= This formula has a maximum at VIN = 2VOUT, where IIN(REMS) = IOUT(RMS)/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the capacitor manufacturer’s ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Always consult the manufacturer if there is any question. For a through-hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can also be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. Some capacitor series available from reputable manufacturers are surge current tested. Output Capacitor Selection The selection of C OUT is primarily determined by the ESR required to minimize voltage ripple and load step transients. The equivalent ripple current into the output capacitor is half of the inductor ripple current while the equivalent frequency is double of phase operation frequency due to two phase operation The output ripple ΔV OUT is approximately bounded by: )Cf16 1ESR(2 IV OUTOSC L OUT ××+Δ=Δ Since ΔIL increases with input voltage, the output ripple is highest at maximum input voltage. Typically, once the ESR requirement is satisfied, the capacitance is adequate for

Application Information

21uP1605-DS-F0000, Jun. 2012 www.upi-semi.com -80 -60 -40 -20 0 1 10 100 1000 Frequency (Hz) Gain (dB) Compensator Gain Loop Gain Modulator Gain Figure 8. Frequency Response of Type III Compensation. by the regulator to return VOUT to its steady-state value. overshoot or ringing that would indicate a stability problem. interconnecting impedances and parasitic circuit elements.

1 The upper and lower MOSFETs turn on/off and conduct

generates a large voltage spike during the switching. connection the top layer with wide, copper filled areas.

2 Place the power components as physically close as

2.1 Place the input capacitors, especially the high

2.2 Place the output capacitor between the converter

3 Place the uP1605 near the upper and lower MOSFETs

with UGATE and LGATE facing the power components.

4 Use a dedicated grounding plane and use vias to ground

5 Apply another solid layer as a power plane and cut this

plane into smaller islands of common voltage levels. with heat sinking power components. 6 The PHASE node is subject to very high dV/dt voltages. heat convection path of the lower MOSFET.

7 The uP1605 sources/sinks impulse current with 2A peak

minimize the parasitic inductance along the traces. 8 Flood all unused areas on all layers with copper.

9 Provide local VCC decoupling between VCC and GND

22 uP1605-DS-F0000, Jun. 2012 www.upi-semi.com

Package Information

1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm. VQFN4x4-24L 3.90 - 4.10 Pin 1 mark Bottom View - Exposed Pad 2.30 - 2.80 2.30 - 2.80 0.18 - 0.30 3.05 - 3.15 4.40 - 4.60 3.90 - 4.10 0.0 - 0.05 0.80 - 1.00

0.20 REF

Recommended Solder Pad Pitch and Dimensions 0.18 - 0.30

23uP1605-DS-F0000, Jun. 2012 www.upi-semi.com Important Notice uPI and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. uPI products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment. However, no res ponsibility is assumed by uPI or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of uPI or its subsidiaries. COPYRIGHT ( C) 2010, UPI SEMICONDUCTOR CORP. uPI Semiconductor Corp. Headquarter 9F.,No.5, Taiyuan 1st St. Zhubei City, Hsinchu Taiwan, R.O.C. uPI Semiconductor Corp. Sales Branch Office 12F-5, No. 408, Ruiguang Rd. Neihu District, Taipei Taiwan, R.O.C.